TWI372975B - Method structure and computer program product for implementing a combined data/coherency cache - Google Patents
Method structure and computer program product for implementing a combined data/coherency cacheInfo
- Publication number
- TWI372975B TWI372975B TW095104364A TW95104364A TWI372975B TW I372975 B TWI372975 B TW I372975B TW 095104364 A TW095104364 A TW 095104364A TW 95104364 A TW95104364 A TW 95104364A TW I372975 B TWI372975 B TW I372975B
- Authority
- TW
- Taiwan
- Prior art keywords
- implementing
- computer program
- program product
- combined data
- method structure
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
- G06F12/082—Associative directories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/056,809 US8131936B2 (en) | 2005-02-11 | 2005-02-11 | Method and apparatus for implementing a combined data/coherency cache |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200636463A TW200636463A (en) | 2006-10-16 |
TWI372975B true TWI372975B (en) | 2012-09-21 |
Family
ID=36061655
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095104364A TWI372975B (en) | 2005-02-11 | 2006-02-09 | Method structure and computer program product for implementing a combined data/coherency cache |
Country Status (5)
Country | Link |
---|---|
US (1) | US8131936B2 (zh) |
EP (1) | EP1854010A1 (zh) |
CN (1) | CN100514311C (zh) |
TW (1) | TWI372975B (zh) |
WO (1) | WO2006084866A1 (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101782921B (zh) * | 2009-12-28 | 2013-01-16 | 北京握奇数据系统有限公司 | 一种目录创建、查询和删除方法及装置 |
US10089025B1 (en) | 2016-06-29 | 2018-10-02 | EMC IP Holding Company LLC | Bloom filters in a flash memory |
US10055351B1 (en) | 2016-06-29 | 2018-08-21 | EMC IP Holding Company LLC | Low-overhead index for a flash cache |
US10261704B1 (en) | 2016-06-29 | 2019-04-16 | EMC IP Holding Company LLC | Linked lists in flash memory |
US10037164B1 (en) | 2016-06-29 | 2018-07-31 | EMC IP Holding Company LLC | Flash interface for processing datasets |
US10146438B1 (en) | 2016-06-29 | 2018-12-04 | EMC IP Holding Company LLC | Additive library for data structures in a flash memory |
US10331561B1 (en) | 2016-06-29 | 2019-06-25 | Emc Corporation | Systems and methods for rebuilding a cache index |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4513367A (en) * | 1981-03-23 | 1985-04-23 | International Business Machines Corporation | Cache locking controls in a multiprocessor |
WO1984002799A1 (en) * | 1982-12-30 | 1984-07-19 | Ibm | A hierarchical memory system including separate cache memories for storing data and instructions |
US4785395A (en) * | 1986-06-27 | 1988-11-15 | Honeywell Bull Inc. | Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement |
US5265232A (en) | 1991-04-03 | 1993-11-23 | International Business Machines Corporation | Coherence control by data invalidation in selected processor caches without broadcasting to processor caches not having the data |
EP0713181A1 (en) * | 1994-11-16 | 1996-05-22 | International Business Machines Corporation | Data processing system including mechanism for storing address tags |
-
2005
- 2005-02-11 US US11/056,809 patent/US8131936B2/en active Active
-
2006
- 2006-02-08 EP EP06708122A patent/EP1854010A1/en not_active Withdrawn
- 2006-02-08 WO PCT/EP2006/050778 patent/WO2006084866A1/en active Application Filing
- 2006-02-08 CN CNB2006800045951A patent/CN100514311C/zh active Active
- 2006-02-09 TW TW095104364A patent/TWI372975B/zh active
Also Published As
Publication number | Publication date |
---|---|
US8131936B2 (en) | 2012-03-06 |
TW200636463A (en) | 2006-10-16 |
US20060184744A1 (en) | 2006-08-17 |
WO2006084866A1 (en) | 2006-08-17 |
CN100514311C (zh) | 2009-07-15 |
CN101116062A (zh) | 2008-01-30 |
EP1854010A1 (en) | 2007-11-14 |
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