TWI372394B - Programming a nand flash memory with reduced program disturb - Google Patents

Programming a nand flash memory with reduced program disturb

Info

Publication number
TWI372394B
TWI372394B TW096141741A TW96141741A TWI372394B TW I372394 B TWI372394 B TW I372394B TW 096141741 A TW096141741 A TW 096141741A TW 96141741 A TW96141741 A TW 96141741A TW I372394 B TWI372394 B TW I372394B
Authority
TW
Taiwan
Prior art keywords
programming
flash memory
nand flash
program disturb
reduced program
Prior art date
Application number
TW096141741A
Other languages
Chinese (zh)
Other versions
TW200832413A (en
Inventor
Mark Shlick
Mark Murin
Original Assignee
Sandisk Il Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/806,111 external-priority patent/US8059456B2/en
Application filed by Sandisk Il Ltd filed Critical Sandisk Il Ltd
Publication of TW200832413A publication Critical patent/TW200832413A/en
Application granted granted Critical
Publication of TWI372394B publication Critical patent/TWI372394B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
TW096141741A 2006-11-07 2007-11-05 Programming a nand flash memory with reduced program disturb TWI372394B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US86460706P 2006-11-07 2006-11-07
US80610807A 2007-05-30 2007-05-30
US11/806,111 US8059456B2 (en) 2006-11-07 2007-05-30 Programming a NAND flash memory with reduced program disturb

Publications (2)

Publication Number Publication Date
TW200832413A TW200832413A (en) 2008-08-01
TWI372394B true TWI372394B (en) 2012-09-11

Family

ID=41357101

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096141741A TWI372394B (en) 2006-11-07 2007-11-05 Programming a nand flash memory with reduced program disturb

Country Status (2)

Country Link
KR (1) KR101003163B1 (en)
TW (1) TWI372394B (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903495A (en) 1996-03-18 1999-05-11 Kabushiki Kaisha Toshiba Semiconductor device and memory system

Also Published As

Publication number Publication date
TW200832413A (en) 2008-08-01
KR101003163B1 (en) 2010-12-22
KR20090097863A (en) 2009-09-16

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees