TWI364844B - Liquid crystal display, active components array substrate and fabricating method of active components array substrate - Google Patents

Description

P070011ATZ1TW 24123twf.doc/p IX. Description of the invention: [Technical field of the invention] The present invention has a method and a display device, and particularly relates to an active component array substrate. And a manufacturing method thereof and a liquid crystal display (LCD). [Prior Art] For the rapid pace of multimedia society, most of them benefit from the dramatic advancement of semiconductor components or human-machine display devices. As for the display device, a flat display device having high quality, high efficiency, low efficiency, and low power consumption, such as power consumption and flawlessness, has gradually become the mainstream of the market. Among various flat display devices, the Thin Film Transistor (TFT) liquid crystal display device is the most mature flat display device of the current technology. However, since the development of liquid crystal display devices, there are still some problems to be improved, one of which is that there is a parasitic capacitance in the intersection of the data lines and the scanning lines on the active device array substrate, which causes a RC delay. Fig. 1A is a top view showing an active device array substrate of a thin film transistor liquid crystal display device. Figure 1B is a cross-sectional view taken along line I-Ι in Figure ία. Referring to FIG. 1A and FIG. 1B, the active device array substrate has an insulating substrate 1 , a plurality of scan lines ι 4 connecting the gates 102 , a plurality of lean lines 108 connecting the source/drain electrodes ι 6 , and a plurality of The individual halogen electrodes are 11〇. In the prior art, the scan line 1〇4 and the data line 1〇8 are separated by only a thin insulating layer 112 to prevent the scan line 104 and the data line 108 from being electrically connected to each other. However, when a voltage is applied to the scanning line 104 and the data line 1〇8, the staggered portion 114 still has a parasitic P070011ATZ1TW 24123 twf.doc/p electric valley generation' causing a delay in the RC to affect the display effect of the liquid crystal display device. With the enlargement of the liquid crystal display device, the data transmission speed is bound to increase, and the tolerance for the resistance-capacitance delay is relatively deteriorated. Moreover, the length of the signal line also increases due to the increase in size, which in turn causes an increase in impedance, resulting in a higher RC delay. SUMMARY OF THE INVENTION The present invention provides a method for fabricating an active device array substrate, which can reduce the parasitic capacitance effect at the intersection of the data line and the scan line and reduce the RC delay in the existing reticle process. The present invention provides an active device array substrate which has a small parasitic capacitance effect at the intersection of the data line and the scan line and is less prone to delay of the resistance. The invention provides a liquid crystal display device which improves the resistance delay of the intersection of the data line and the scanning line. One method of fabricating the active device array substrate of the present invention is to form a first (four) conductive layer on the substrate, which has a plurality of scan lines. Next, the insulating layer of the first patterned conductive layer is formed on the insulating substrate. After that, the semiconductor layer is formed on the Wei edge layer. In addition, the patterned insulating underlayer is removed. Next, a second patterned conductive layer is formed on the insulating layer, which has a plurality of data lines and correspondingly connected to these ί poles/drain electrodes. Wherein the 'connected to the data line may be the source or the 'poor line' above the patterned insulating mat and the scan line, and the area where the lean line intersects the scan line 箄'·曰缘塾The size of the layer. This — P070011AT21TW 24123tw£doc/p edge layer and these scan lines form multiple active components. In an embodiment of the method for fabricating an active device array substrate, the method of forming a patterned semiconductor layer and a patterned insulating underlayer includes: forming a semiconductor layer over the 纟'^ layer; forming a temporary layer on the semiconductor layer The insulating mat layer has a plurality of second regions of the plurality of first-region discs, and the thickness of the temporarily patterned insulating mat layer of the second region of the first patterned temporary insulating mat layer The first area is located at the intersection of the data line and the sweeping cat line; the temporary patterned insulating layer (4) is used as the mask to remninate the semiconductor layer, (4) the semiconductor layer is smeared; the second layer of the temporarily patterned insulating layer is removed. Zone to form a patterned insulating mat. Another method of fabricating the active device array substrate of the present invention is to first form a -first patterned conductive layer on the insulating substrate having a plurality of broom lines. And a "patterned insulating underlayer" is formed on the first conductive layer. Thereafter, an insulating layer covering the first patterned conductive layer and the patterned insulating underlayer is formed on the insulating substrate. Then, a patterned semiconductor layer is formed on the insulating layer. Next, a second patterned conductive layer is formed on the insulating layer, wherein the second patterned conductive layer has a plurality of data lines and a plurality of source/drain electrodes correspondingly connected to the data f. Among them, the connection to the data line can be the source or the pole. The data lines are interlaced with the scan lines above the patterned insulating pads and the area of the data lines and scan lines may not be equal to the area of the patterned insulating mat. These source/drain electrodes, patterned edge layers, and the chain-structured elements. In a certain embodiment of the method for fabricating the active device array substrate, the method for forming the first patterned conductive layer and the _ insulating insulating layer comprises: on a 1364844 P070011ATZ1TW 24123 twf.doc/p edge substrate Forming a first conductive layer; forming a patterned insulating insulating layer on the first conductive layer, wherein the temporarily patterned insulating underlayer has a plurality of first-regions and a plurality of second regions' The thickness of the patterned insulating germanium layer is greater than the thickness of the temporarily patterned insulating underlayer of the second regions, the first regions being located at the intersection of the data lines and the scan lines; and temporarily patterning the insulating mat as a mask Etching the first conductive layer to form a first patterned conductive layer; and removing the second region of the temporarily patterned insulating underlayer, and forming a patterned insulating underlayer. In the method of fabricating the above two active device array substrates, the method further includes forming a protective layer on the insulating substrate having a plurality of contact opening openings exposing a partial region of the source and/or the pole. Then, a plurality of pixel electrodes are formed in the protection, and the pads are connected to the secrets. - contact solid happiness in the production of the above two active component array boards - the implementation of the patterned insulating mat can be opened with a half-tone mask; the insulating full layer ds method can include a comprehensive reduction of temporary patterning And degrees until the second zone is removed. Furthermore, the method of reducing the thickness of the insulating layer (4) may include performing a method of fabricating a semiconductor device layer of the two active device array substrates. The step further includes forming a patterned ohmic contact layer on the patterned via. The first active device (four) substrate comprises an insulating substrate, a /, an electrical layer, an insulating layer, a patterned semiconductor layer, - Figure 8 1364844 24123 tw

P0700I1ATZ1TW" insulating insulating layer, - second patterned conductive layer. The first conductive layer is disposed on the insulating substrate and has a plurality of sweeping cat wires. The insulating layer is disposed on the insulating substrate and covers the first patterned conductive The patterned semiconductor layer is disposed on the insulating layer, and the patterned insulating layer is disposed on the insulating layer or between the insulating layer and the broom line. The second patterned conductive layer is disposed on the insulating layer and has multiple pieces of data. The line and the corresponding source/drain of the data line are connected. The data line is interlaced with the sweeping cat line above the patterned insulating layer, and the area of the patterned insulating layer is not equal to the data line and the sweeping line. The size of the area, the source/H meshing semiconductor layer, the insulating layer and the Sweep constituting a plurality of active components. In the embodiment of the active device array substrate, a protective layer = and a plurality of halogens are further included. The protective layer is disposed on the insulating substrate and has a plurality of contact window openings in a partial region of the source/drain of the storm. The halogen electrode is disposed on the protective layer and electrically connected to the source via the contact window opening. And a liquid crystal display device of the present invention includes the above-described active device array substrate '-protective layer, a plurality of pixel electrodes, a pair of substrates, and a liquid crystal layer. The protective layer has been placed on the insulating substrate, And having a multi-touch window opening σ exposing a part of the source/deep pole. The alizarin electrode is disposed on the riding layer, and is electrically connected to the active element through the contact window opening α. The substrate (four) is between the substrates. 曰 - In an embodiment of the liquid crystal display device, the backlight module is further included, and the active 7L array substrate, the opposite substrate and the liquid crystal layer are disposed above the backlight module. 9 P070011ATZ1TW 24123twf.doc/p In the main (four) array substrate and liquid crystal display example of the invention, the patterned insulating germanium layer is disposed between the insulating layer and the data line, and the divided patterned semiconductor layer is located in the insulating layer and patterned. Insulation layer=Inventive active device array substrate and liquid crystal display „, the active device array substrate further includes a patterned ohmic layer, disposed between the SiC layer and the source Λ and the pole. In the embodiment of the active device array substrate and the liquid crystal display device of the invention, (4) of the insulating insulating layer is an organic material. Another active device array substrate of the present invention has a plurality of active elements, a plurality of broom lines, a plurality of data lines and a patterned insulating layer. The sweeping cat line is essentially interlaced with the data line. The gate electrical connection of each active component = should be m and the source/secret connection of each wire component corresponds to the material line. The cased insulation mat is only located at the intersection of the sweep and data lines and between the scan line and the data line. Another liquid crystal display device of the present invention comprises an active device array substrate, a pair of substrates, and a liquid crystal layer. The active device array substrate has a plurality of active components, a plurality of halogen electrodes, a plurality of scan lines, a plurality of f-feed lines, and a patterned insulating underlayer. The scan lines are essentially interlaced with the data lines. The gates of the active components are electrically connected to the corresponding scan lines, and the source/drain electrodes of the respective active components are electrically connected to the corresponding data lines and the corresponding halogen electrodes. The patterned insulating underlayer is substantially only at the intersection of the scan line and the data line and between the scan line and the data line. Further, the liquid crystal layer is disposed between the active device array substrate and the opposite substrate. 1364844 24123twf.doc/p

P070011ATZ1TW In an embodiment of the liquid crystal display device of the present invention, further comprising a backlight module, the wire component _ substrate and the shaft substrate Wei layer are disposed above the backlight module. In an embodiment of the active device array substrate and the liquid crystal display device of the present invention, the active device is a transistor of a bottom gate structure. In an example of the active device array substrate and the liquid crystal display device of the present invention, the active device is a thin film transistor having a top interpole structure. In summary, the active device array substrate of the present invention and the manufacturing method thereof are formed by the existing photomask, and a patterned insulating germanium phase is added outside the (four) line and the scanning line to reduce the data line and the scanning line. The parasitic capacitance effect, which in turn reduces the turn-delay and improves the performance of the wire component _ substrate. The liquid crystal display device of the present invention is provided with the above-described active device array substrate, and therefore has the same advantages to improve the performance of the liquid crystal age device. * The above and other objects, miscellaneous and gamma energies of the present invention are more apparent and understood. The preferred embodiment, the conjugate, is described in detail below. [Embodiment] In the following description, the terms "first" and "second" attached to the front of each material layer are used only to distinguish different material layers, and do not represent the order of steps or other meanings. FIG. 2A to FIG. 21 are partial cross-sectional views showing the steps of the process of the active device array substrate according to an embodiment of the present invention, and FIGS. 3A to 3F are views showing a part of the steps in the process of FIG. 2A to FIG. . Referring to FIG. 2A and FIG. 3A, a patterned conductive layer 210 is formed on an insulating substrate 200. Fig. 2A is a cross-sectional view taken along line A-A of Fig. 3A. In the manner of forming the first patterned conductive layer 210, for example, a complete conductive layer is formed on the insulating substrate 200 by deplating or other suitable processes, and then the first mask process is performed to pattern the conductive layer to form The first patterned conductive layer 210. The first patterned conductive layer 21A has a plurality of scan lines 212. Additionally, the scan lines 212 can extend with a plurality of gates 214. Of course, in other embodiments, the gate can also be part of the scan line. Next, referring to Fig. 2B, an insulating layer 220 is formed on the insulating substrate 2A. The insulating layer 220 completely covers the insulating substrate 2 and the first patterned conductive layer 210. The material of the edge layer 220 is, for example, a stone oxide, a stone nitride or other insulating material. Referring to FIGS. 2F and 3C, a patterned semiconductor layer 230 and a patterned insulating underlayer 250 are formed on the insulating layer 220. Figure 2F is a cross-sectional view taken along line A-A of Figure 3C. A patterned ohmic contact layer 240 may be further formed after the step of forming the patterned semiconductor layer 23 and before forming the patterned insulating underlayer 250. For example, the patterned ohmic contact layer 240 may be formed by doping N-type ions on the surface of the patterned semiconductor layer 230 by ion doping. Alternatively, a suitable reaction gas such as phosphorus hydride (ph3) may be added to the film forming gas in a manner of chemical vapor deposition (CVD) to form a comprehensive ohmic contact layer (not shown). The patterned ohmic contact layer 240 is then formed while forming the patterned semiconductor layer 230. The patterned ohmic contact layer 240 can reduce the contact resistance between the patterned semiconductor layer 230 and the second patterned conductive layer to be formed later. 12 1364844 P070011ΑΤΖ1TW 24123twf.doc/p FIGS. 2C to 2F illustrate one of the methods of forming the patterned semiconductor layer 23 and the patterned insulating underlayer 250, but are not intended to limit the present invention. Referring to Fig. 2C', a semiconductor layer 23 is formed on the insulating layer 220. The semiconductor layer 230' completely covers the insulating layer 220. 2D and 3B, a temporarily patterned insulating pad layer 25', is formed on the semiconductor layer 230'. Figure 2D is a cross-sectional view taken along line A-A of Figure 3B. The temporarily patterned insulating pad layer 25 has a plurality of first regions 252 and a plurality of second regions 254 (only one of which is shown in FIG. 2D). The temporarily patterned insulating pad layer 25 of the first region 252 has a thickness 丄 that is greater than the thickness of the temporarily patterned insulating pad layer 25 of the second region 254, and the first region 252 is located on the scan line 212 and will be formed later. The data lines of the two patterned conductive layers are staggered. The temporarily patterned insulating underlayer 25 is formed, for example, using a halftone mask. Referring to Fig. 2E, the side insulating layer 250' is temporarily patterned to form a side semiconductor layer 23?. If the ohmic contact layer 240' is present, etching is performed together. Referring to FIG. 2F and FIG. 3c, the temporarily patterned insulating underlayer of the second 254 is removed to form a patterned insulating germanium layer. FIG. 2F is a cross-sectional view along line a_A of FIG. 3C. The method of removing the temporarily patterned insulating layer 25A of the second region 254 is, for example, to substantially reduce the temporary patterned insulating underlayer 25, thickness ' until the second regions (5) are removed. The method of resisting the thickness of the insulating layer includes forming a second 26 在 on the insulating layer 220 with reference to FIG. 2g and FIG. 3D. Subsequently, the second patterned conductive layer can be used to mask the photoresist of the conductive layer (not shown), and the back channel etching (Bce) is removed to remove the gate 13 1364844 24123 twf. Doc/p

A portion of the P0700UATZ1TW electrode 214 is patterned to ohmic contact layer 24A to expose a portion of the patterned semiconductor layer 230. Fig. 2G is a cross-sectional view taken along line A-A of Fig. 3D. The second patterned conductive layer 260 has a plurality of data lines 262 and a plurality of source/drain electrodes 264 correspondingly connected to the plurality of data lines 262. Source 264 and / and pole 264 are located on opposite sides of gate 214. The source 264 may be connected to the data line 262 or may be the drain 264. Data line 262 is interleaved with scan line 212 over patterned insulating pad layer 250. In the present embodiment, for convenience of description of the present invention, the area of the patterned insulating pad layer is equal to the area of the interlaced area of the data line 262 and the scanning line 212. However, the present invention does not limit the patterned insulating pad layer 25〇. area. For example, referring to FIG. 4, the area of the patterned insulating underlayer 25 may also be larger than the area of the interlacing of the line 262 and the scan line 212 to ensure complete isolation of the data line 262 and the scan line 212. 4 is a partial top view of another active device array substrate according to an embodiment of the invention. The source/drain 264 patterned semiconductor layer 230, the insulating layer 220, and the scan lines 212 constitute a plurality of wire elements. In the actual sealing towel, the active component is a thin film transistor with a bottom idler structure. In another embodiment of the invention, the active component can also be a thin film transistor of a top gate structure. Referring to FIG. 2H and FIG. 3E, the insulating substrate 200 can be further formed. The germanium layer 270 has a portion of the contact opening 272 that exposes the source/drain 264. When the data line 262 is, for example, connected to the corresponding one, the contact window opening 272 exposes a portion of the drain 264. When the lean line 262 is, for example, connected to the corresponding drain 264, the contact window opens: 272 exposes a portion of the source 264. Figure 2A is a cross-sectional view taken along line 1364844 P070011ATZ1TW 24123twf.doc/p. Referring to FIG. 21 and FIG. 3F', a plurality of pixel electrodes 280 are formed on the protective layer 270, and the source electrodes 264 or the drain electrodes 264 are electrically connected via the contact window openings 272. Figure 21 is a cross-sectional view taken along line B_B of Figure 3F. In addition, since the position and area of the halogen electrode 280 may vary depending on different requirements, the source 264 or the drain 264 may extend below the pixel electrode 280 to be electrically connected to the halogen electrode 280. for example, . Referring to Fig. 5', source 264a or 汲_pole 264a may extend to the pixel electrode 2g〇a I to be electrically connected to the halogen electrode 280a. FIG. 5 is a partial top view of still another active device array substrate according to an embodiment of the invention. As described above, in the active device array substrate of the embodiment and the manufacturing method thereof, the patterned insulating pad layer 25 is formed between the steps of forming the patterned semiconductor layer 230 and the second patterned conductive layer 260, and This patterned insulating pad layer 250 increases the distance at which the data lines 262 and the scan lines 212 are staggered and reduces the parasitic capacitance effect at the stagger. Therefore, the method for fabricating the active device array substrate of the present embodiment can improve the shortcoming of the RC delay, thereby improving the performance of the active cell array substrate. The ITO layer 250 can be formed by a general process 10 for defining the patterned semiconductor layer 23, so that no additional process equipment and cost are added. Further, the material of the insulating substrate 200 is, for example, glass or other transparent. The first patterned conductive layer 210 and the second patterned conductive layer 26 may include aluminum 'aluminum-niobium alloy, aluminum-niobium alloy, molybdenum, molybdenum nitride, titanium, copper, and other suitable materials. The material of insulating layer 220 and protective layer 270 may comprise tantalum nitride or other suitable material. The patterned semiconductor layer 2 is made of P070011ATZ1TW 24123twf.doc/p 7 which can include amorphous Aussie Semiconductor or other suitable materials. The patterned insulating germanium layer 0 is, for example, a germanium organic photoresist layer or other suitable material layer. The material of the halogen electrode 28A may include indium tin oxide (Indium Zinc idexide, IT〇), indium zinc oxide (Indium Zinc 〇xide, ΙΖ〇) or other suitable materials. 6A to FIG. 61 are cross-sectional views showing a process of an active device array substrate according to another embodiment of the present invention, and FIGS. 7A to 7F are partial top views of a portion of the process of FIGS. 6A to 61. . Referring to FIG. 6D and FIG. 7C, a first patterned conductive layer 410' is formed on the insulating substrate 4'' and a patterned insulating underlayer 420 is formed on the first patterned conductive layer 41'. Figure 6D is a cross-sectional view taken along line Α_Α in Figure 7c. The first patterned conductive layer 410 has a plurality of scans, lines 412. Additionally, the scan lines 412 can extend with a plurality of gates 414. Of course, in other embodiments the gate may also be part of the scan line. 6A to 6D illustrate one of the methods of forming the first patterned conductive layer 41A and the patterned insulating underlayer 420. Referring to FIG. 6A, the first conductive layer 41 is formed on the insulating substrate 400. Referring next to Figures 6A and 7B, a temporarily patterned insulating underlayer 420' is formed over the first conductive layer 410'. Figure 6 is a cross-sectional view taken along line Α-Α in Figure 7Α. Temporarily patterned insulating pad layer 420 has a plurality of first regions 422 and a plurality of second regions 424. The thickness of the temporarily patterned insulating underlayer 420 of the first region 422 is greater than the thickness of the temporarily patterned insulating underlayer 420 of the second region 424, and the first region 422 is located after the scan that will be formed by the first conductive layer 410'. The lines and the data lines of the second conductive layer to be formed are staggered. The temporarily patterned insulating underlayer 420 is formed, for example, using a halftone reticle. Please refer to the figure and figure 16 1364844

P070011ATZ1TW 24123twf.d〇c/p 7B, in the case of temporary insulation (four)·, is the side of the mask-guide 410,' to form the first patterned conductive layer 41〇. Fig.... is a cross-sectional view taken along line B-B of Fig. 73. Referring to FIG. 6D and FIG. %, the second region 424 of the temporary pattern/insulating germanium layer 42G is removed to form a patterned insulating germanium layer 42A. Figure 6D is a cross-sectional view taken along line A-A of Figure 7C. A second region-like method of removing the temporarily patterned insulating pad layer 420' is, for example, to substantially reduce the temporary pattern and the thickness of the insulating germanium layer 420' until the second regions 424 are removed. The method for reducing the thickness of the temporarily patterned insulating mat layer is, for example, advanced; the photoresist burn-off process. Referring to FIG. 6E', an insulating layer 43 is formed on the insulating substrate, which covers the first patterned conductive layer 410 and the patterned insulating underlayer 42A. Next, a patterned semiconductor layer 440 is formed on the insulating layer 430 with reference to FIG. 6F'. After the step of forming the patterned semiconductor layer 44, it may further include forming a patterned ohmic contact layer 450. For example, the surface of the patterned semiconductor layer 44 can be doped with N-type ions to form a patterned ohmic contact layer 45A by means of ion doping. Alternatively, chemical vapor deposition (CVD) can be used to form a suitable reaction gas, such as a tri-tank (ph3), into the film-forming gas to form a comprehensive ohmic contact layer (not labeled) ). A patterned ohmic contact layer 45A is then formed while forming the patterned semiconductor sound * 440. The patterned ohmic layer 450 can reduce the contact resistance between the patterned semiconductor layer 440 and the second patterned conductive layer to be formed later. Referring to Figures 6G and 7D, a second patterned conductive layer 460 is formed on the insulating layer 43A. Accordingly, the second patterned conductive layer 46^ or 17 1364844 24123twf.doc/p

P070011ATZ1TW The photoresist (not (4)) forming the second smear layer is a mask, and a back channel etching process is performed to remove the portion 450 above the gate 414 to expose a portion of the patterned semiconductor layer 働. A section along the line A_A' in Figure 忉. The second patterned conductive layer has a plurality of material lines 462 and a plurality of source/drain electrodes 464 correspondingly connected to the plurality of data lines. Source 464 manifold 464 can be located on opposite sides of interpole 414. The source 464 may be connected to the data line 462 or may be 464. The data lines 462 are interlaced with each other on the patterned insulating pad (4) square disk scan line 412. In the present embodiment, for convenience of description, the area of the insulating pad 42A of the present invention is equal to the area of the interlaced area of the data line 462 and the scan: 412, but the present invention does not limit the patterned insulating layer 420. Area. For example, referring to Fig. 8, the area of the patterned insulating underlayer may also be larger than the interlaced area of the data line 462 and the scan line 412 to ensure complete isolation of the data, line 462, and scan line. Figure 8 is a partial top view of the substrate of the present invention. These sources are not extremely pleasing, the patterned semiconductor layer 44〇, and the insulating layer are all these. Scanning lines constitute a plurality of active sections. In this embodiment, 70 pieces of the film are the thin film transistors of the bottom gate structure. In another embodiment of the invention, the active component can also be a thin film transistor of a top gate structure. Referring to FIGS. 6A and 7B, a protective layer 470 may be formed on the insulating substrate. Figure 6 is a cross-sectional view taken along line Α_Α in Figure 7Ε. The protective layer 470 has a plurality of contact windows 472 that expose portions of the source/drain 464. Contact window opening 472 may expose portions of drain 464 when data, line 462 is, for example, connected to a corresponding source. When the data line he 1364844 24123twf.doc/p

When the P070011ATZ1TW is connected to the corresponding drain 464, for example, the contact opening 472 may expose a portion of the source 464. Next, referring to Fig. 61 and Fig. 7F, a plurality of pixel electrodes 480 are formed on the protective layer 47A. Figure 61 is a cross-sectional view taken along line B_B of Figure 7F. The electrode 480 is electrically connected to the source 464 or the drain 464 via the contact window 472. In addition, since the position and area of the pixel electrode may vary depending on the deer's different needs, the source 464 or the electrodeless 464 may be extended under the electrode 480 to be electrically connected to the halogen electrode 480. . For example, referring to FIG. 9, the source 464a or the drain 464a may extend under the halogen electrode 480a to be electrically connected to the pixel electrode 48A. Fig. 9 is a partial top plan view showing still another active device array substrate according to an embodiment of the present invention. As described above, in the active device array substrate of the embodiment and the method of fabricating the same, the patterned insulating layer 42 is formed between the steps of forming the first patterned conductive layer 41 and the insulating layer 43? Patterning the insulating germanium layer 420 thereby increases the distance at which the data lines 462 and the scan lines 412 are staggered and reduces the parasitic capacitance effect at the stagger. Therefore, the active component of the present embodiment and the method of fabricating the array substrate can also improve the shortcoming of the RC delay, thereby improving the performance of the active component array substrate. In addition, the patterned insulating underlayer 4 can be formed by a photoresist layer used to define the first patterned conductive layer 410 in a conventional process, thereby not adding additional process equipment and cost. Further, the material of the insulating substrate 400 is, for example, glass or other transparent material. The material of the first patterned conductive layer 410 and the second patterned conductive layer may include aluminum, aluminum-bismuth alloy, aluminum-bismuth alloy, molybdenum, molybdenum nitride, titanium, 1364844 24123tvvf.doc/p

P070011ATZ1TW Gold, copper f other suitable materials. The material of the insulating layer 43A and the protective layer 47A may include nitride or other suitable material. The material of the patterned semiconductor layer 44 may comprise amorphous austenite or other suitable material. The patterned insulating germanium layer 420 is, for example, an organic photoresist layer or other suitable material layer. The material of the pixel electrode can be (10) oxide, oxide or other suitable material. Fig. 1G is a cross-sectional view showing a liquid crystal display device of the present invention. Referring to FIG. 10, the liquid crystal display device 6 of the present embodiment includes a main

The dynamic element array substrate 6Q2, the counter substrate 6() 4, and the liquid crystal layer are secret. The active component, column 602 may be each of the above-described embodiments of the wire element array, or other wire element substrate in accordance with the spirit of the present invention. That is, the two active component array board 6G2 has patterned insulating money disposed on the _ layer or between the insulating layer and the broom line, and the patterned insulating pad layer is located at the intersection of the data line and the scanning line. Therefore, the effect of the active device array substrate (4) is also excellent, and the display performance of the liquid crystal display device 6 is also improved. The opposite substrate 604 is disposed on the active device lowering substrate 6〇2

The crystal layer 606 is located between the opposite substrate 6〇4 and the active device array substrate 6〇2. In addition, the liquid crystal display device _ may further include a backlight module _, and the active device array substrate 〇2, the opposite substrate and the liquid crystal layer _ may be disposed above the backlight module 608. In summary, the active device array substrate of the present invention and the manufacturing method thereof have an additional layer of patterned insulation (4) between the scan line and the data line in the existing photomask process to increase the job line and the data gap. Since the value of the derivative capacitance is inversely proportional to the wire pitch, increasing the spacing between the scan line and the lean line reduces the difference between the scan line and the data line. 20 1364844

P070011ATZ1TW 24123twf.doc/p = effect, which in turn reduces the RC delay. In addition, since it can be carried out in the existing reticle process, the manufacturing method does not add additional manufacturing equipment and equipment. Since the RC delay phenomenon of the active device array substrate of the present invention is improved, the display performance of the liquid crystal display device can be improved when applied to a liquid crystal display device. The present invention has been disclosed in the preferred embodiments as above, but it is not intended to limit the invention, and any one of ordinary skill in the art is not

Without departing from the spirit and scope of the present invention, the scope of protection of the present invention is defined by the full scope of the attached towel. [Simple description of the map]

Fig. 1A is a top plan view showing a main body array substrate of a conventional thin film transistor liquid crystal display device. Figure 1B is a cross-sectional view taken along line A-A of Figure 1A. 2A to 21 are partial cross-sectional views showing the process steps of an active device array substrate according to an embodiment of the present invention. Elements Figures 3A to 3F are top views of some of the steps in the process of Figures 2A through 21. Figure 4 is a partial top plan view of another active device array substrate which is not an embodiment of the present invention. FIG. 5 is a partial top view of still another active device array substrate according to an embodiment of the invention. 6A to 61 are cross-sectional views showing processes of another main element array substrate according to an embodiment of the present invention. 21 1364844 P070011ATZ1TW 24123twf.doc/p FIGS. 7A to 7F are partial top views showing a part of the steps of the process of FIGS. 6A to 61. FIG. 8 is a partial top view of another active device array substrate according to an embodiment of the invention. FIG. 9 is a partial top view of still another active device array substrate according to an embodiment of the invention. Fig. 10 is a cross-sectional view showing a liquid crystal display device according to an embodiment of the present invention. [Description of main component symbols] 100, 200, 400: Insulating substrates 102, 214, 414: Gates 104, 212, 412: Scanning lines 106, 264, 264a, 464, 464a: Source/drain electrodes 108, 262, 462 : data lines 110, 280, 280a, 480, 480a: halogen electrodes 112, 220, 430: insulating layer 114: staggered 210, 410: first patterned conductive layer 230, 440: patterned semiconductor layer 230': semiconductor Layers 240, 450 · Patterned ohmic contact layer 240': ohmic contact layer 250, 250a, 420, 420a: patterned insulating pad layer 250', 420': temporarily patterned insulating pad layer 22 1364844 P070011ATZ1TW 24123twf.doc/p 252, 422 · first region 254, 424: second region 260, 460: second patterned conductive layer 270, 470: protective layer 272, 472: contact window 410': first conductive layer 600: liquid crystal display device 602 : Active device array substrate 604 : opposite substrate 606 : liquid crystal layer 608 : backlight module 23

Claims (1)

1364844 ict year q month>} day revision 100-9-23 X. Patent application scope: 1. A method for fabricating an active device array substrate, comprising: forming a first patterned conductive layer on an insulating substrate, The patterned conductive layer has a plurality of scan lines; an insulating layer is formed on the insulating substrate to cover the first patterned conductive layer - a semiconductor layer is formed on the insulating layer; a temporary patterned insulating layer is formed on the semiconductor layer塾层,立中亨, the patterned insulating layer has a plurality of first-regions and a plurality of second regions. The thickness of the temporarily patterned insulating layer is greater than the patterning of the second insulating layer. The thickness of the layer; the temporary patterning of the insulating germanium layer as a mask to engrave the half layer to form a patterned semiconductor layer; ^excluding the second region of the riding (four), in the Forming a patterned insulating underlayer on the germanium layer; and forming a second patterned conductive layer on the insulating layer; the conductive layer has a plurality of data lines and correspondingly connecting the "^ original = / bet, the data lines are in the The patterned insulating layer is interlaced with the layers The source/drain, the patterned semiconductor layer, the core layer and the scan lines form a plurality of active elements. The m is formed on the edge substrate of the active device array substrate according to the first item. a protective layer having a plurality of contact opening openings in a portion of the source region of the two source poles; and 24 100-9-23 via the contacts and a window electrode, wherein the halogen electrodes The manufacturing method is as follows: the cover of the active device array substrate described in the above-mentioned item 1. The temporarily patterned insulating underlayer is a time-sharing insulating layer of the active device array substrate according to the one-half mode light. The method of the second zone includes comprehensively reducing the temporary === until the second zones are removed. The maker, the go, and the JL by the active device array substrate of the fourth item include patterning during execution. The method for fabricating the thickness of the active device array according to the first aspect of the invention, the method for fabricating the active device array substrate comprises: forming a first conductive layer on the c; (4) 导电 on the conductive layer Forming a temporary patterned click The middle layer has a plurality of first-region=two: the thickness of the temporary layer is larger than the (2) layers, and the __ one conductive layer has a plurality of (four) clear L-patterned conductive strips to remove the temporarily patterned insulating germanium layer a region for forming an insulating insulating layer on the patterned conductive layer of the 25^04844 100-9-23; forming an insulating layer covering the first patterned insulating layer on the insulating substrate; (4) forming a conductive layer and Forming a patterned semiconductor layer on the insulating layer; and patterning the second patterned "layer, wherein the second source and the second data line are multi-selected", the source dipoles, the patterning; The insulating layer and the scan lines constitute a plurality of active components. The method for fabricating the active device array substrate according to Item 7 of the second aspect further includes: f the insulating substrate is formed as a layer, wherein the layer has a plurality of contact windows exposing the two source/recorded partial regions. Opening a plurality of halogen electrodes on the protective layer, and matching the openings of the contact windows to electrically connect the secret elements to the active device array substrate according to item 8 of the extremely advantageous range The |1, Ί玄 temporarily patterned insulating layer is formed using half-tone light f. The method of claim 4, wherein the method of removing the second regions comprises substantially reducing the thickness of the temporarily patterned insulating underlayer until the second regions are removed. The method of reducing the thickness of the temporarily patterned insulating underlayer by applying the method for image processing of the line element array substrate described in the above-mentioned item 1G includes conducting a photoresist burn-off process. In the step of forming the patterned semiconductor layer, the method further comprises forming a pattern on the semiconductor layer of the semiconductor layer. An ohmic contact layer. 13. An active device array substrate, comprising: an insulating substrate; a first patterned conductive layer disposed on the insulating substrate, the first patterned conductive layer having a plurality of shingles, each of the plurality of sweeping scales An insulating layer is disposed on the insulating substrate and covers the first patterned conductive layer; and a patterned semiconductor layer is disposed on the insulating substrate. a patterned insulating underlayer disposed on the insulating layer or between the insulating layer and the scan lines; and y a second patterned conductive layer ′ disposed on the insulating layer, the second patterned conductive layer having The recording data axis corresponds to a plurality of source/drain electrodes connected to the plurality of material lines, and the plurality of source/drain electrodes are interlaced with the scanning lines above the data line, and the source/drain electrodes, the pattern The semiconductor layer, the insulating layer, and the plurality of gates of the squeezing layer overlapping the slewing layer constitute a plurality of active elements. 14. The active device array substrate of claim 13, further comprising: - a protective layer disposed on the insulating substrate and having a plurality of contact windows exposing a portion of the source/drain And the plurality of halogen electrodes are disposed on the protective layer, and the source/no-pole are electrically connected correspondingly through the contact openings. 27 100-9-23 15. As in the patent application slate, wherein the lining insulation/layer is between the line element array bases, and the portion _ patterning half 2 is between the insulation layer and the plurality of material lines Between the insulation pads. The limb guiding layer is located between the insulating layer and the pattern 16· as in the patent application panel, and further includes a patterned active ohmic contact between the primary power component array base layer and the source/drain electrodes. (4) Arranged in the patterned semiconductor board, the material of the insulating insulating layer in the active device array substrate fR described in the above section 13 is an organic material. And a liquid crystal display device comprising: an active device array substrate, comprising: an insulating substrate; a first patterned conductive layer disposed on the insulating substrate, the first patterned conductive layer having a plurality of scan lines Each of the scan lines has a plurality of gates; an insulating layer disposed on the insulating substrate and covering the first patterned conductive layer; a patterned semiconductor layer disposed on the insulating layer; a patterned insulating layer a pad layer disposed on the insulating layer or between the insulating layer and the scan lines; a second patterned conductive layer disposed on the insulating layer, the second patterned conductive layer having a plurality of data lines and Corresponding to connecting a plurality of source/drain electrodes of the data lines, wherein the data lines are interlaced with the scan lines above the patterned insulating pad layer, the source/drain electrodes, the patterned conductors 28 1364844 100*9-23 a protective layer disposed on the insulating substrate and having a plurality of contact opening openings exposing a portion of the source/drain regions; and a plurality of halogen electrodes disposed thereon On the protective layer, Via the plurality of contact holes and correspondingly electrically connected to the plurality of source / no electrode; an opposite substrate; and - a liquid crystal layer 'in the active device array Miyazaki Prefecture plate without the counter substrate. 19. The liquid crystal display device of claim 18, wherein the patterned impurity layer is disposed on the insulating layer and the data lines and a portion of the patterned semiconductor layer is located on the insulating layer and the Patterned between the edges of the layer. 20. The liquid crystal display device of claim 18, wherein the active device array substrate further comprises a patterned ohmic contact layer between the S-patterned semiconductor layer and the source/drain electrodes . 21. The liquid crystal display according to the scope of claim 2, wherein the material of the patterned insulating mat is an organic material. The liquid crystal display as described in claim 18 includes a backlight module, wherein the active device array substrate, the pair and the liquid crystal layer are disposed above the backlight module. Soil 2 3. An active device array substrate having a plurality of active components, a scan line, a plurality of data lines and a patterned insulating mat layer, wherein the two lines are interlaced with the "four (4) lines, each The idler of the wire element is 29 1364844 100-9-23 wire 'and the source level of each active component is electrically connected to the motor": and the work: line: ! 2: 5 layer is substantially only located in the data lines The father of the line is between the faulty line and the broom line and the 24th. As in the scope of the patent application, the board: the active elements are the film of the bottom pole structure = column substrate, wherein the active elements It is a liquid crystal display device for the top-closed structure array, including ··専膜"日日体. A plurality of pixels of the electrode port are connected to the cat line, and the source/wrong of each active element And between the dielectric line and the intersection line of the data lines and the data lines; the opposite substrate; and the Γ liquid crystal layer disposed between the active device array substrate and the opposite substrate Display device, its 0Q& gate structure of the bonding film transistor. The liquid crystal display device of the above-mentioned item 26 is a thin film transistor having a top gate structure. ', the liquid crystal display device according to item 5% of the patent application, and 30 1364844 100-9-23 includes one The backlight module, wherein the active device array substrate, the opposite substrate and the liquid crystal layer are disposed above the backlight module.