1364836 /Μ年/b月巧曰條正替換頁 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種電阻式記憶體（resistance memory )以及其製造方法，尤其是有關於一種使用與CMOS 製程相容之材料的電極之電阻式記憶體以及製造該電阻式 記憶體之方法，以降低元件的製程整合的困難度。 【先前技術】 氧化物電阻式記憶體通常需要使用鉑（Pt)作為電極。 但由於鉑不易與其他元素反應，因此會造成元件在蝕刻上 非常的困難，而使得製程整合的難度提高許多。此外，單 價高的鉑也會造成整體的製造成本上升。 圖一為曰本富士通（Fujitsu)在2006 SSDM會議上所 發表的鉑/氧化鈦/氮化鈦（Pt/Ti02/TiN )的電阻式記憶體之 結構示意圖。在圖一中，該電阻式記憶體包括氮化鈦所形 成之下電極11、氧化鈦所形成之介電層12以及鉑所形成 之上電極13。該電阻式記憶體雖然可以呈現出不錯的電阻 轉換特性，但是鉑電極的使用將會造成元件在製程整合的 難度提高與製造成本的增加。 因此，為了改善上述缺失，亟需一種電阻式記憶體以 及其製造方法，使用與CMOS製程相容之材料的電極，以 降低元件的製程整合的困難度。 【發明内容】 本發明之一目的在於提供一種電阻式記憶體以及其製 5 1364836 年/>月A曰條正替換頁 造方法，使用與CMOS製程相容之材料的電極，以降低元 件的製程整合的困難度。 本發明之另一目的在於提供一種電阻式記憶體以及其 製造方法，使用兩種不同功函數的電極，其中功函數較大 的金屬做為元件的下電極，而功函數較低的金屬做為元件 的上電極。此元件在經過適當的熱處理後，會形成能穩定 操作的雙極性電阻轉換元件。 為達上述目的，本發明提供一種製造電阻式記憶體之 方法，包括以下步驟： 提供一基板； 依序沉積一第一導電材料、一非化學計量比氧化物以及 一第二導電材料於該基板上；以及 進行一熱處理程序； 其中該第一導電材料之功函數高於該第二導電材料之 功函數。 為達上述目的，本發明提供一種電阻式記憶體，包括： 一第一導電材料所形成之下電極、一非化學計量比氧化 物所形成之介電層以及一第二導電材料所形成之上 電極； 其中該第·一導電材料之功函數兩於該第二導電材料之 功函數。 【實施方式】 為使貴審查委員能對本發明之特徵、目的及功能有 更進一步的認知與瞭解，茲配合圖式詳細說明如後。 1364836 年%修正替換頁 在本發明中，係提供一種電阻式記憶體以及其製造方 法，一種電阻式記憶體以及其製造方法，使用與CMOS製 程相容之材料的電極，以降低元件的製程整合的困難度。 圖二為本發明之電阻式記憶體之橫截面示意圖。在圖 二中，該電阻式記憶體包括一第一導電材料所形成之下電 極21、一非化學計量比氧化物所形成之介電層22以及一 第二導電材料所形成之上電極23。其中，該第一導電材料 之功函數1¾於該第二導電材料之功函數。 在一具體實施例中，上電極23採用功函數較下電極 21低的導電材料。倘若下電極為氮化鈦（TiN)、釕（Ru)、 氮化鈕（TaN)等功率函數介於4·5至5.0eV之材料，則上 電極則可為鈦（Ti)、鋁（A1)、鋁銅（AlCu)合金等功 率函數介於4.0至4.5之材料。上述下電極與下電極之導電 材料的沉積方式可為物理氣相沉積（PVD)或化學氣相沉 積（CVD )，以形成厚度為5nm至500nm之薄膜。例如， 上、下電極可以分別採用物理氣相沉積所成長的鋁銅合金 和氮化鈦。 在一具體實施例中，介電層22則使用非化學計量比之 金屬氧化物，如氧化鈦（TiOx)、氧化铪（HfOx)、氧化 銅（CuOx)、氧化鋁（A10x)、氧化鈮（NbOx)以及氧化 锆（ZrOx)等。非化學計量比氧化物係以物理氣相沉積 (PVD)、化學氣相沉積（CVD)以及金屬氧化方式之一 者形成，以形成厚度為l〇nm至100nm之薄膜。例如，可 利用原子層化學氣相沉積（ALD)所形成的非化學計量比 氧化給。 7 1364836 _ |ί)ό年月负曰絛正替換頁 在完成記憶體早元的薄膜沉積後’為了使元件產生電 阻轉換的特性，須進行一道熱處理程序。在一具體實施例 中，熱處理程序可為爐管加熱或是快速熱退火（RTA)， 處理溫度可為300至800°C，熱處理時間可為l〇s至 10000s，在氮氣（N2)、氮氣與氫氣（N2+H2)、氬（Ar) 以及氬與氫氣（Ar+H2)之一種環境中進行。 圖三為本發明之電阻式記憶體之元件特性示意圖。在 圖三中，本發明之電阻式記憶體呈現穩定的電阻轉換的特 性。 圖四為本發明之電阻式記憶體之寫入/抹除測試結 果。其中，該電阻式記憶體係使用鋁銅合金/氧化铪/氧 化鈦（AlCu/HfO/TiN)結構作為展示範例。可知本發明之 電阻式記憶體除了因採用鋁銅合金與氧化鈦而可以降低元 件的製程整合難度與製作成本外，其穩定的寫入/抹除次 數（>104)也超越一般採用鉑電極元件的寫入/抹除次數 (<103)。 綜上所述，當知本發明提供一種電阻式記憶體以及其製 造方法，一種電阻式記憶體以及其製造方法，使用與CMOS 製程相容之材料的電極，以降低元件的製程整合的困難 度。故本發明實為一富有新穎性、進步性，及可供產業利 用功效者，應符合專利申請要件無疑，爰依法提請發明專 利申請，懇請貴審查委員早曰賜予本發明專利，實感德 便。 惟以上所述者，僅為本發明之較佳實施例而已，並非 用來限定本發明實施之範圍，即凡依本發明申請專利範圍 8 1364836 / μ年曰條正替換頁 所述之形狀、構造、特徵、精神及方法所為之均等變化與 修_，均應包括於本發明之申請專利範圍内。 1364836 车丨厶月幻日修正替換頁 【圖式簡單說明】 圖一為一習知電阻式記憶體之橫截面示意圖； 圖二為本發明之電阻式記憶體之橫截面示意圖； 圖三為本發明之電阻式記憶體之元件特性示意圖；以及 圖四為本發明之電阻式記憶體之寫入/抹除測試結果。 【主要元件符號說明】 11 下電極 12 介電層 13 上電極 21 第一導電層 22 介電層 第二導電層 231364836 / leap year / b month clever strip replacement page 9 , invention description: [Technical field of the invention] The present invention relates to a resistive memory (resistance memory) and a method of manufacturing the same, and particularly relates to a use A resistive memory of an electrode of a material compatible with a CMOS process and a method of manufacturing the resistive memory to reduce the difficulty of process integration of the device. [Prior Art] Oxide resistive memory generally requires the use of platinum (Pt) as an electrode. However, since platinum is not easily reacted with other elements, it is extremely difficult to etch the components, which makes the process integration much more difficult. In addition, high-priced platinum will also increase overall manufacturing costs. Figure 1 shows the structure of a resistive memory of platinum/titanium oxide/titanium nitride (Pt/Ti02/TiN) published by Fujitsu at the 2006 SSDM conference. In Fig. 1, the resistive memory includes an electrode 11 formed of titanium nitride, a dielectric layer 12 formed of titanium oxide, and an upper electrode 13 formed of platinum. Although the resistive memory can exhibit good resistance conversion characteristics, the use of the platinum electrode will increase the difficulty of component integration in the process and increase the manufacturing cost. Therefore, in order to improve the above-mentioned defects, there is a need for a resistive memory and a method of manufacturing the same, which uses an electrode of a material compatible with a CMOS process to reduce the difficulty of process integration of the device. SUMMARY OF THE INVENTION An object of the present invention is to provide a resistive memory and a method for fabricating the same, which uses a material compatible with a CMOS process to reduce the components. The difficulty of process integration. Another object of the present invention is to provide a resistive memory and a method of fabricating the same, using electrodes of two different work functions, wherein a metal having a larger work function is used as a lower electrode of the element, and a metal having a lower work function is used as The upper electrode of the component. This component, after proper heat treatment, forms a bipolar resistance-switching element that operates stably. To achieve the above object, the present invention provides a method of fabricating a resistive memory, comprising the steps of: providing a substrate; sequentially depositing a first conductive material, a non-stoichiometric oxide, and a second conductive material on the substrate And performing a heat treatment process; wherein a work function of the first conductive material is higher than a work function of the second conductive material. To achieve the above object, the present invention provides a resistive memory comprising: a lower electrode formed by a first conductive material, a dielectric layer formed of a non-stoichiometric oxide, and a second conductive material formed thereon An electrode; wherein a work function of the first conductive material is equal to a work function of the second conductive material. [Embodiment] In order to enable the reviewing committee to have a further understanding and understanding of the features, objects and functions of the present invention, the detailed description will be made in conjunction with the drawings. 1364836% Correction Replacement Page In the present invention, there is provided a resistive memory and a method of fabricating the same, a resistive memory and a method of fabricating the same using an electrode of a material compatible with a CMOS process to reduce process integration of components The difficulty. 2 is a schematic cross-sectional view of a resistive memory of the present invention. In FIG. 2, the resistive memory comprises a lower electrode 21 formed by a first conductive material, a dielectric layer 22 formed by a non-stoichiometric oxide, and an upper electrode 23 formed by a second conductive material. Wherein the work function of the first conductive material is a work function of the second conductive material. In a specific embodiment, the upper electrode 23 is made of a conductive material having a lower work function than the lower electrode 21. If the lower electrode is a material having a power function of 4·5 to 5.0 eV such as titanium nitride (TiN), ruthenium (Ru), or nitride button (TaN), the upper electrode may be titanium (Ti) or aluminum (A1). ), aluminum-copper (AlCu) alloy and other materials with a power function between 4.0 and 4.5. The conductive material of the lower electrode and the lower electrode may be deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form a film having a thickness of 5 nm to 500 nm. For example, the upper and lower electrodes may be respectively formed by physical vapor deposition of an aluminum-copper alloy and titanium nitride. In a specific embodiment, the dielectric layer 22 uses a non-stoichiometric ratio of metal oxides such as titanium oxide (TiOx), hafnium oxide (HfOx), copper oxide (CuOx), aluminum oxide (A10x), and antimony oxide ( NbOx) and zirconia (ZrOx) and the like. The non-stoichiometric oxide is formed by one of physical vapor deposition (PVD), chemical vapor deposition (CVD), and metal oxidation to form a film having a thickness of from 10 nm to 100 nm. For example, non-stoichiometric oxidation formed by atomic layer chemical vapor deposition (ALD) can be used. 7 1364836 _ | ί) ό 月 替换 替换 替换 替换 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在 在In a specific embodiment, the heat treatment process may be furnace tube heating or rapid thermal annealing (RTA), the treatment temperature may be 300 to 800 ° C, the heat treatment time may be l 〇 s to 10000 s, in nitrogen (N 2 ), nitrogen. It is carried out in an environment of hydrogen (N2+H2), argon (Ar), and argon and hydrogen (Ar+H2). Fig. 3 is a schematic view showing the characteristics of the components of the resistive memory of the present invention. In Fig. 3, the resistive memory of the present invention exhibits stable resistance conversion characteristics. Figure 4 is a graph showing the write/erase test results of the resistive memory of the present invention. Among them, the resistive memory system uses an aluminum-copper alloy/yttria/titanium oxide (AlCu/HfO/TiN) structure as an example of display. It can be seen that the resistive memory of the present invention can reduce the process integration difficulty and the manufacturing cost of the device by using aluminum-copper alloy and titanium oxide, and the stable write/erase times (>104) exceeds the general use of the platinum electrode. Number of write/erase times of the component (<103). In summary, the present invention provides a resistive memory and a method of fabricating the same, a resistive memory and a method of fabricating the same, using an electrode of a material compatible with a CMOS process to reduce the difficulty of process integration of the device. . Therefore, the present invention is truly novel, progressive, and available for industrial use. It should be in accordance with the requirements of the patent application, and the application for invention patents should be filed according to law, and the reviewing committee is required to give the invention patent as soon as possible. However, the above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the practice of the present invention, that is, the shape described in the patent application section 8 1364836 / μ Equivalent changes and modifications to the structure, features, spirits, and methods are intended to be included in the scope of the invention. 1364836 丨厶 幻 幻 修正 修正 修正 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 364 364 364 364 364 364 364 364 364 364 364 364 364 ; 364 ; 364 ; ; ; ; 364 ; 364 A schematic diagram of the element characteristics of the resistive memory of the invention; and FIG. 4 is a result of the write/erase test of the resistive memory of the present invention. [Main component symbol description] 11 Lower electrode 12 Dielectric layer 13 Upper electrode 21 First conductive layer 22 Dielectric layer Second conductive layer 23