1364099 S3U07-0015 26302twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明疋有關於一種線路結構(r〇uting stmcture)，且特 別疋有關於一種重配置線路層（re_distribution layer，RDL) 的線路結構。 【先前技術】 在尚度情報化社會的今曰，多媒體應用的市場不斷地1364099 S3U07-0015 26302twf.doc/n IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a circuit structure (r〇uting stmcture), and particularly to a re-distribution layer (re_distribution layer, Line structure of RDL). [Prior Art] In the future of the information society, the market for multimedia applications is constantly
急速擴張著。積體電路封裝技術亦需配合電子裝置的數位 化、、網路化、區域連接化以及使用人性化的趨勢發展。為 ，成上述的要求，必須強化電子元件的高速處理化多功 月^化積集化、小型輕量化及低價化等多方面的要求，於 是積體電路龍技術也跟著躺微型化、高密度化發展。、 所謂積體電路封裝密度所指的是單位面積所含有腳位 (pin)數目多募的程度。對於高密度積體電路封裝而言，縮 路與封裝基材間配線的長度，將有助訊號傳遞速 二二I ’是以藉由凸塊(bUmP)作為訊號傳遞之覆晶封裝 技術已漸成為高密度封裝的主流。 卜二，見的引線接合晶片（wirebondingchip)為例，其 ' ’ （bonding pad)通常為周圍分佈型態(peripheral 1、’、=引線電性連結至封裝基板上的引線接合墊；而 二:曰二f P chip)上的焊墊則通常是以陣列方式(讓y 的產品將改採勢r越ί越多 又j J乃八進订封裝。然而，為了封 5 S3U07-0015 26302twf.doc/n =改變而一併更改既有產品的晶片設計，並不符合 因此，在發展出焊墊重配置的技 ==2層設置一重配置線路層，將=合晶 ===態進行重配置，使其成為覆晶晶片焊 塾之^列分佈的型態，以配置覆晶封裝所需之凸塊。 如r:帝I知技術之重配置線路層的線路結構將焦點放 =::康:供至晶片中的核心電路(c。，而沒 1=:;衡線路結構中所產生的雜一 地降供—種重配置線路層的線路結構，能夠有效 片的置線路層的線路結構，配置於晶 停路結構包括電源走線、多條第-長 接相鄰兩個第中各第一連接線連 接地走線配胁騎走=長緣導線連接於電源走線。 二銲塾及多μ n的—側’且接地走線包括多個第 個第射各第二連躲連接相鄰兩 條狀導線盘第:=!線連接於接地走線，而第-長 分防/、第一長條狀導線彼此交錯配置且互不相交。 的線路’在上述之重配置線路層 ㈣Γ第—長錄導線例如是連接於第一鋅墊。 又“、、發明的一實施例所述，在上述之重配置線路層 1364099 S3U07-〇〇i5 26302twf.doc/n 、-路、、*〇構中，第—長條狀導線例如是連接於第一連接線。 依、、本發明的—實施例所述，在上述之重配置線路層 -路、構f，第二長條狀導線例如是連接於第二銲墊。 依,、、、本發明的—實施例所述，在上述之重配置線路層 〜路結構中，第二長條狀導線例如是連接於第二連接線。 依…、本發明的—實施例所述，在上述之重配置線路層Rapid expansion. Integral circuit packaging technology also needs to be developed in line with the digitalization, networking, regional connectivity and user-friendly trends of electronic devices. In order to meet the above requirements, it is necessary to strengthen the high-speed processing of electronic components, multi-function, integration, small size, light weight, and low cost, so that the integrated circuit technology is also miniaturized and high. Density development. The so-called integrated circuit package density refers to the extent to which the number of pins per unit area is increased. For high-density integrated circuit packages, the length of the wiring between the shrinkage and the package substrate will help the signal transmission speed of the second-two I' is based on the flip-chip package technology with bump (bUmP) as the signal transmission. Become the mainstream of high-density packaging. 2, see wirebonding chip as an example, its 'bonding pad' is usually a surrounding distribution type (peripheral 1, ', = lead electrically connected to the wire bond pad on the package substrate; and two: The pads on the chip are usually in an array (so that the product of y will change the potential r more and more, and the j J is eight-package. However, in order to seal 5 S3U07-0015 26302twf.doc /n = change and change the chip design of the existing product, it does not match. Therefore, in the development of the pad reconfiguration technology == 2 layers to set a reconfiguration line layer, the = crystal === state for reconfiguration It is made into the type of the distribution of the flip chip solder bumps to configure the bumps required for the flip chip package. For example, the line structure of the reconfigured circuit layer of the R-I know technology puts the focus =: : the core circuit (c., not 1 =:; the heterogeneous ground drop generated in the line structure), the line structure of the reconfiguration line layer, and the line structure of the effective layer The configuration of the crystal stop structure includes a power supply line, and a plurality of first-long connection adjacent two first ones of the first connection The wire is connected to the ground wire with the threatening ride = the long edge wire is connected to the power supply wire. The second welding wire and the multi-μ n-side 'and the grounding wire include a plurality of first first shots each second connected to the adjacent two The strip-shaped lead wire:=! line is connected to the grounding trace, and the first-long split prevention/the first long strip-shaped wires are staggered with each other and do not intersect each other. The line 'in the above-mentioned reconfigured circuit layer (four) Γ first- The long recording wire is connected, for example, to the first zinc pad. Further, as described in one embodiment of the invention, in the above-mentioned reconfiguration circuit layer 1364099 S3U07-〇〇i5 26302twf.doc/n, -路,, *〇 The first long strip conductor is connected to the first connecting line, for example, according to the embodiment of the present invention, in the above-mentioned reconfigured circuit layer-path, f, and the second long strip is, for example, Connected to the second bonding pad. According to the embodiment of the present invention, in the above-mentioned reconfiguration circuit layer to the road structure, the second elongated wire is connected to the second connecting wire, for example. According to the embodiment of the present invention, in the above reconfiguration circuit layer
^路結構t ’第-祕狀導線的延伸方向與電源走線的 k伸方向的失角例如是銳角。 依照本發明的一實施例所述，在上述之重配置線路層 、線路結構令’第二長條狀導線的延伸方向與接地走線的 延伸方向的夾角例如是銳角。 依照本發明的一實施例所述，在上述之重配置線路層 的線路結射’第—長條狀導_延伸方向與電源走線的 延伸方向的夾角例如是直角。^ The declination direction of the extension direction of the path structure t'th-secret wire and the k-direction of the power supply line is, for example, an acute angle. According to an embodiment of the present invention, the angle between the extending direction of the second long strip conductor and the extending direction of the ground trace in the reconfigurable wiring layer and the line structure is, for example, an acute angle. According to an embodiment of the present invention, the angle between the direction in which the line-elongation of the re-arrangement line layer and the direction in which the power supply trace extends is, for example, a right angle.
依照本發明的一實施例所述，在上述之重配置線路層 的線路結構中’第二長條狀導線的延伸方向與接地走線的 延伸方向的夾角例如是直角。 依照本發明的一實施例所述，在上述之重配置線路層 的線路結構中，線路結構的材料例如是金屬。 基於上述’由於在本發明所提出之重配置線路層的線 路結構中具有交錯配置且互不相交的第一長條狀導線與第 一長條狀導線，所以可以大幅地提升去耦合電容 (de-c〇upiing capacit〇r)，因此能夠過遽掉線路結構中的雜 訊，而有效地降低雜訊。 7 S3U07-0015 26302twf.d〇c/n ‘為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 明如下。 ' ° 【實施方式】 圖1所緣示為本發明一實施例之重配置線路層的線路 結構的上視圖。 請參照圖1 ’重配置線路層的線路結構102，配置於 晶片100的頂層金屬層’可用以將晶片100上之銲墊(未繪 示）進行重配置並提供電源至晶片100中的核心電路(未幹 示）。 線路結構102包括電源走線104、第一長條狀導線 、接地走線108及第二長條狀導線11〇。線路結構 的材料可為任何金屬，例如是銅。 電源走線104包括銲墊112及連接線114，其中各連 接線114連接相鄰兩個銲墊112。電源走線1〇4例如是沿 著延伸方向116進行延伸。 第一長條狀導線106連接於電源走線104。各第一長 條狀導線106例如是一端連接於銲墊112或連接線U4， 而另一端沿著延伸方向118進行延伸，且第一長條狀導線 106彼此之間例如是互為平行排列。其中，第一長條狀導 線106的延伸方向118與電源走線104的延伸方向ι16的 夾角θι例如是銳角。 在本實施例中，是以第一長條狀導線106同時連接於 銲塾112及連接線U4為例進行說明’但並不用以限制本 1364099 S3U07-0015 26302twf.doc/n 發明。於此技術領域具有通常知識者參照本實施例可知， 只要第一長條狀導線1〇6連接於銲墊U2及連接線114的 至少一者並與第二長條狀導線11〇交錯配置且互不相交， 即可達成本發明之增加去耦合電容的功效。 接地走線108配置於電源走線1〇4的一侧，且接地走 線108包括多個銲墊12〇及多條連接線122，其中各連接 線122連接相鄰兩個銲墊12〇。接地走線1〇8例如是沿著 延伸方向124進行延伸。接地走線1〇8的延伸方向124與 電源走線104的延伸方向116例如是互相平行。 第二長條狀導線11〇連接於接地走線1〇8，而第一長 條狀導線106與第二長條狀導線11〇彼此交錯配置且互不 相交。各第二長條狀導線H0例如是一端連接於銲墊12〇 或連接線122，而另一端沿著延伸方向126進行延伸，且 第一長條狀導線110彼此之間例如是互為平行排列。其 中，第二長條狀導線110的延伸方向126與接地走線1〇8 的延伸方向124的失角02例如是銳角。 在本實施例中，是以第二長條狀導線n〇同時連接於 銲墊120及連接線122為例進行說明，但並不用以限制本 發明。於此技術領域具有通常知識者參照本實施例可知， 只要第二長條狀導線110連接於銲墊12〇及連接線122的 至；一者並與苐一長條狀導線1〇6交錯配置且互不相交， 即可達成本發明之增加去耦合電容的功效。 由上述實施例可知，由於重配置線路層的線路結構 1〇2中具有交錯配置且互不相交的第一長條狀導線1〇6與 9 1364099 S3U07-0015 26302twf.doc/n 1. 藉由本發明所提出的重配置線路層的 幅地增加去耦合電容。 〜構可大 2. 本發明所提出的重置線路層的線路 雜訊的功效。 /、令降低 雖然本發明已以較佳實施例揭露如上，然其 限定本發明，任何熟習此技藝者，在不脫離本發明之 和範圍内’當可魅許之更動_飾，因此本發明之^ 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1所繪不為本發明一實施例之重配置線路層的線 結構的上視圖。 ' 圖2所繪不為本發明另一實施例之重配置線路層的線 路結構的上視圖。 【主要元件符號說明】 100 102 104 106 108 110 112 114 116 200 202 204 206 208 210 120 122 118 晶片 線路結構 電源走線 第一長條狀導線 接地走線 第二長條狀導線 212、220 :銲墊 214、222 :連接線 124、126、216、218 224、226 :延伸方 向 θι、θ2、θ3、θ4 :夾角 11According to an embodiment of the present invention, in the wiring structure of the reconfigurable wiring layer, the angle between the extending direction of the second elongated conductor and the extending direction of the grounding conductor is, for example, a right angle. According to an embodiment of the present invention, in the wiring structure of the reconfigurable wiring layer, the material of the wiring structure is, for example, a metal. The decoupling capacitor can be greatly improved based on the above-mentioned 'the first long strip wire and the first long strip wire which have staggered configurations and do not intersect each other in the line structure of the reconfigured circuit layer proposed by the present invention. -c〇upiing capacit〇r), so it is possible to eliminate noise in the line structure and effectively reduce noise. The above and other objects, features, and advantages of the present invention will become more apparent and understood from the <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; . [Embodiment] Fig. 1 is a top view showing the line structure of a reconfiguration wiring layer according to an embodiment of the present invention. Referring to FIG. 1 'Reconfiguring the wiring structure of the wiring layer 102, the top metal layer disposed on the wafer 100' can be used to reconfigure the pads (not shown) on the wafer 100 and provide power to the core circuit in the wafer 100. (not shown). The line structure 102 includes a power trace 104, a first elongated conductor, a ground trace 108, and a second elongated conductor 11〇. The material of the wiring structure can be any metal such as copper. The power trace 104 includes a pad 112 and a connection line 114, wherein each connection 114 connects adjacent two pads 112. The power supply line 1〇4 extends, for example, along the extending direction 116. The first elongated strip 106 is connected to the power trace 104. Each of the first elongated wires 106 is, for example, one end connected to the pad 112 or the connecting line U4, and the other end extending along the extending direction 118, and the first elongated wires 106 are, for example, arranged in parallel with each other. The angle θι between the extending direction 118 of the first elongated wire 106 and the extending direction ι 16 of the power supply line 104 is, for example, an acute angle. In the present embodiment, the description is made by taking the case where the first elongated wire 106 is simultaneously connected to the pad 112 and the connecting wire U4, but is not intended to limit the invention of 1364099 S3U07-0015 26302twf.doc/n. Referring to the present embodiment, the first long strip wire 1〇6 is connected to at least one of the pad U2 and the connecting wire 114 and is alternately arranged with the second elongated wire 11〇. The effects of the added decoupling capacitor of the present invention can be achieved by not intersecting each other. The grounding traces 108 are disposed on one side of the power supply traces 1-4, and the ground traces 108 include a plurality of pads 12A and a plurality of connection lines 122, wherein each of the connection lines 122 connects the adjacent two pads 12A. The ground traces 1〇8 extend, for example, along the extension direction 124. The extending direction 124 of the ground traces 1 〇 8 and the extending direction 116 of the power traces 104 are, for example, parallel to each other. The second long strip conductor 11 is connected to the ground trace 1〇8, and the first elongated strip conductor 106 and the second elongated strip conductor 11 are staggered with each other and do not intersect each other. Each of the second elongated wires H0 is, for example, one end connected to the pad 12 〇 or the connecting line 122, and the other end extending along the extending direction 126, and the first elongated wires 110 are, for example, arranged parallel to each other. . The missing angle 02 of the extending direction 126 of the second elongated wire 110 and the extending direction 124 of the grounding wire 1〇8 is, for example, an acute angle. In the present embodiment, the second long strip wire n is simultaneously connected to the pad 120 and the connecting wire 122 as an example, but is not intended to limit the present invention. Those skilled in the art can refer to the present embodiment as long as the second elongated wire 110 is connected to the pads 12 and the connecting wires 122; one is interleaved with the long strips 1〇6. The advantages of the decoupling capacitor of the present invention can be achieved by not intersecting each other. It can be seen from the above embodiment that the first long strip conductors 1〇6 and 9 1364099 S3U07-0015 26302twf.doc/n have the staggered configuration and do not intersect each other in the line structure 1〇2 of the reconfiguration line layer. The proposed method of reconfiguring the wiring layer increases the decoupling capacitance. ~ Structure can be large 2. The effect of the line noise of the reset circuit layer proposed by the present invention. Although the present invention has been disclosed in the above preferred embodiments, the present invention is defined by the present invention, and the present invention can be modified without departing from the scope of the present invention. The scope of the application is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top view of a line structure of a reconfigurable circuit layer which is not an embodiment of the present invention. Figure 2 is a top plan view of the wiring structure of the reconfiguration circuit layer which is not another embodiment of the present invention. [Main component symbol description] 100 102 104 106 108 110 112 114 116 200 202 204 206 208 210 120 122 118 Wafer line structure power supply line 1st long wire grounding wire 2nd long wire 212, 220: welding Pads 214, 222: connecting lines 124, 126, 216, 218 224, 226: extending directions θι, θ2, θ3, θ4: angle 11