1363895 九、發明說明 【發明所屬之技術領域】 本發明是有關於一種電路基板及其應用，且特別是有關 於一種供積體電路（ic)接合之電路基板及其在液晶顯示裝 置上的應用。 【先前技術】 請參照第1圖，其係繪示習知一液晶顯示模組之驅動電 路用基板上之接合墊的平面佈局示意圖。現行驅動電路用基 板100之接合墊佈局102中，設有複數個輸入接合墊（Input Pad) 104、複數個輸出接合塾1 〇8、以及一些虛設接合塾 (Dummy Pad)106,其中每個輸出接合墊1〇8均具有相對應 之導線110自輸出接合墊1〇8之一端延伸而出，而進入一液 晶顯不面板（未繪示），上述輸入接合墊1〇4為提供驅動電路 (例如為-閘極驅動積體電路)輸入端的接合，而輸出端接合 墊108則提供驅動電路輸出端與導線110的接合。驅動電路 用基板:〇〇通常為一印刷電路板（PCB)、一可挽式電路板 (FPCj或是液晶顯示膜組之薄膜t晶體（TF取璃基板本身。 明參照第2圖，其係繪示習知電路基板之輸出接合墊的 佈局放大示意圖。右•士拉人# & d 在此接5墊佈局102 _，每個輸出接合墊 108均具有相同之窗痄 ^ 見度114。每個輸出接合墊1〇8與相鄰之 導線11 0 ’例如輸出技人勒，Λ。 mu w a與導線UGa，之間的距離 116相等。此外，自於山秘人虹 ^ 輸出接合墊108起至位於同高度之相鄰 輸出接合墊108，似‘ 6认， π义 < 祁那 人私 輸出接合塾l〇8a起至i〇8c輪屮垃 合墊l〇8a或自輪出接 憨主1U8C輸出接 。墊l〇8b起至輪出接合墊1〇8d之距 1363895 =為接合塾間距（Pad Pitch)112，而每個接合塾間距u 等。目前，輸出接合塾108之排列係呈上下交錯排列，亦即 :相鄰輸出接合墊108上下交錯而位於不同高度。 。輸出接合替l〇8a完全位於相鄰之輪出接合塾⑽b之下 方’而另-與輸出接合墊勵相鄰之輸出接合塾1〇8 完全位於相鄰之輸出接合墊108b之下方。 利用上下二排交錯排列的佈局方式，可縮減二相 二墊108 <間的水平距離’因此相較於輸出接合墊位於同 一高度的佈局，接合墊佈局102的佈局密度可較高。另一方 面’如第1圖所示’若在相同輸出接合墊數量下，接合墊佈 局102之總長度118則可獲得縮減。 然而，在應用此一佈局於一玻璃覆晶技術（chip Μ GUSS;C0G)的源極驅動積體電路（或冑資料、線驅動積體電路） 時，因源極驅動積體電路其輸出接合塾又較閘極驅動積體電 路較為密集’使得距離116降至約12.5心左右。現行一般 接合製程設備其製程能力僅能控制確保其接合誤差在1 $ “ 、内如此今易產生在積體電路與基板接合製程時，對應 於某一輸出接合墊108的積體電路接腳與相鄰的一導線 因接合誤差過大而產生短路造成良率下降，因此習知的接合 墊佈局的製程窗口 (process wind〇w)已不能滿足逐漸升高的 線路積集度的產品或高解析度的液晶顯示器的需求。 【發明内容】 因此，本發明之目的就是在提供一種電路基板，適用於 積體電路之接合，其係將接合區之接合墊兩兩相對設置，並 1363895 將每個接合塾之導線集中設置在這些接合塾之-側，如此-來，可縮減整個接合區之佈局長度。 本發明之另一目的是在提供一種電路基板，可在現行設 .備的生產條件與製程能力下，擴大接合區之接合墊設置的製 程窗口，進一步提高接合製程的良率。 本發明之又一目的是在提供一種液晶顯示面板其接合 區可在相同寬度下，設置更多之接合墊，因此可增加液晶顯 示裝置之解析度。 • 根據本發明之上述目的，提出一種電路基板，至少包 括.基板，至少包括一表面，且此表面上設有至少一接合 ·.區；複數個第一接合墊，設置在接合區上之第-區域；複數 個第二接合塾，設置在接合區上之第二區域，其中第一區域 •與第二區域係不重疊；複數個第-導線’分別對應並接合至 上述第-接合墊’其中這些第—導線平行並列在上述第一接 合墊之下；以及複數個第二導線，分別對應並接合至上述第 一接&墊其中每一第二導線包括一連接部以及一延伸部， 鲁這些第二導線之延伸部平行並列在上述第一區域與第二區 域之外側且與第一導線平行，而第二導線之連接部自對應之 第二接合墊延伸而與對應之延伸部接合。 依照本發明-較佳實施例，上述之電路基板係一薄膜電 晶體（TFT)基板。 根據本發明之目的，提出一種液晶顯示面板，至少包 括.一背光模組；以及一液晶顯示模組，設於背光模組之上， 其中液晶顯示模組至少包括-薄膜電晶體基板，且薄膜電晶 體基至少包括：一基板’至少包括-表面，且此表面上設有 1363895 至少一接合區；複數個第一接合墊，設置在接合區上之第1363895 IX. Description of the Invention [Technical Field] The present invention relates to a circuit substrate and an application thereof, and more particularly to a circuit substrate in which an integrated circuit (ic) is bonded and its application to a liquid crystal display device . [Prior Art] Referring to Fig. 1, there is shown a plan layout view of a bonding pad on a substrate for a driving circuit of a conventional liquid crystal display module. In the bonding pad layout 102 of the current driving circuit substrate 100, a plurality of input pads 104, a plurality of output junctions 〇8, and a dummy dummy pad 106 are provided, wherein each output is The bonding pads 1〇8 each have a corresponding wire 110 extending from one end of the output bonding pad 1〇8, and enter a liquid crystal display panel (not shown), and the input bonding pad 1〇4 is provided with a driving circuit ( For example, the junction of the input terminal of the gate drive circuit and the output pad 108 provides the engagement of the output of the driver circuit with the conductor 110. Substrate for driving circuit: 〇〇 is usually a printed circuit board (PCB), a pullable circuit board (FPCj or thin film t crystal of liquid crystal display film group (TF glazing substrate itself. See Figure 2 for details) An enlarged schematic view of the layout of the output bond pads of the conventional circuit substrate is shown. Right-slopes # & d In this case, the 5-pad layout 102_, each output bond pad 108 has the same window visibility 114. Each of the output pads 1 〇 8 and the adjacent wires 11 0 ′, for example, the output technicians, Λ mu wa and the wires UGA, have the same distance 116. In addition, since the mountain squirrel rainbow output bond pads 108 Up to the adjacent output joint pad 108 at the same height, like '6 recognition, π yi' 祁 人 人 私 私 私 私 〇 〇 〇 a a a c c c c c c c c c c 或 或 或 或 或 或 或 或 或 或 或 或憨 main 1U8C output connection. Pad l 〇 8b up to the wheel joint pad 1 〇 8d distance 1363895 = pad pitch Pitch 112, and each joint u spacing u, etc. Currently, the output joint 塾 108 arrangement The arrays are staggered up and down, that is, the adjacent output bond pads 108 are staggered up and down at different heights. The replacement l〇8a is completely below the adjacent wheel joint 塾(10)b' and the other output joint 塾1〇8 adjacent to the output bond pad is completely below the adjacent output bond pad 108b. The arrangement of the staggered arrangement can reduce the horizontal distance between the two-phase two pads 108 < therefore, the layout density of the bond pad layout 102 can be higher than that of the output bond pads at the same height. As shown in Fig. 1, the total length 118 of the bond pad layout 102 can be reduced if the same number of output pads is used. However, in this application, a layout of a chip flip chip technology (chip Μ GUSS; C0G) is applied. In the case of a pole drive integrated circuit (or a data-driven, line-driven integrated circuit), the output of the integrated circuit of the source-driven integrated circuit is denser than that of the gate-driven integrated circuit, so that the distance 116 is reduced to about 12.5 centimeters. The current general bonding process equipment can only control the integrated circuit corresponding to an output bond pad 108 when the process tolerance is controlled to ensure that the bonding error is within 1 $", which is easy to occur in the integrated circuit and substrate bonding process. The foot and the adjacent one of the wires are short-circuited due to excessive joint error, resulting in a decrease in yield. Therefore, the process window of the conventional bond pad layout cannot satisfy the product or the height of the gradually increasing line accumulation. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a circuit substrate suitable for use in the bonding of integrated circuits by placing the bonding pads of the bonding pads in opposite directions, and 1363895 will each The wires of the joints are concentrated on the side of the joints, so that the layout length of the entire joint can be reduced. Another object of the present invention is to provide a circuit board which can expand the process window of the bonding pad setting of the bonding area under the current production conditions and process capabilities, thereby further improving the yield of the bonding process. Still another object of the present invention is to provide a liquid crystal display panel in which the bonding region can be provided with more bonding pads at the same width, thereby increasing the resolution of the liquid crystal display device. According to the above object of the present invention, a circuit substrate is provided, comprising at least a substrate including at least one surface, wherein the surface is provided with at least one bonding region; a plurality of first bonding pads disposed on the bonding region a region; a plurality of second joints disposed in the second region on the land, wherein the first region does not overlap with the second region; the plurality of first-wires respectively correspond to and are joined to the first-bond pad Wherein the first-conductor wires are juxtaposed in parallel under the first bonding pad; and the plurality of second wires are respectively corresponding to and bonded to the first connection & pad, wherein each of the second wires comprises a connecting portion and an extending portion, The extension portions of the second wires are parallel and juxtaposed on the outer sides of the first region and the second region and parallel to the first wire, and the connection portion of the second wire extends from the corresponding second bonding pad to be engaged with the corresponding extension portion . According to a preferred embodiment of the invention, the circuit substrate is a thin film transistor (TFT) substrate. According to the purpose of the present invention, a liquid crystal display panel includes at least a backlight module, and a liquid crystal display module disposed on the backlight module. The liquid crystal display module includes at least a thin film transistor substrate and a film. The transistor base comprises at least: a substrate 'comprising at least a surface, and the surface is provided with 1363895 at least one joint region; and a plurality of first joint pads disposed on the joint region
…〜吼μ w不一彳冰，/刀、別對應並接合至 第接5塾，其中母一第二導線包括一連接部以及一延伸 部’延些第二導線之延伸部平行並列在第一區域與第二區域 之外側且與第-導線平行，而這些第二導線之連接部自對應 之第二接合墊延伸而與對應之延伸部接合。 較佳實細*例，上述之液晶顯示面板可適用 例如液晶顯示器、液晶電視、筆記型電腦、 依照本發明一 於液晶顯示裝置，> 或可攜式電子設備之螢幕。 依照本發明另一較佳實施例，上述延伸部中與第一接合 墊及第二接合墊相鄰之一者和相鄰之第一接合墊及第二接 合墊之間的距離實質等於第一接合墊之間的間隔。 【實施方式】 本發明揭露一種電路基板及其應用，具有高密度接合墊 佈局及較佳的製程窗口，因而可縮短佈局總長度、增加:合 墊數而提高液晶顯示面板之解析度、或提高製程良率。為了 使本發明之敘述更加詳盡與完備，可參照下列描述並配合第 3圖至第5圖之圖示。 口 發明一較佳實施例的—種 電路基板200適用以供積 。在本發明中，電路基板 請參照第3圖，其繪示依照本發明 電路基板之接合墊的佈局示意圖。電路 體電路晶片（IC chip)接合於其上。右 1363895 200可為玻璃基板或軟性電路板，例如軟性印刷電路板 (Flexible Printed Circuit ; FPC)、捲帶式自動接合（Tape Automated Bonding ; TAB)膜或覆晶薄膜（Chip On Film ; COF) ^其中’破璃基板可為液晶顯示面板中之薄膜電晶體 (TFT)基板，此時驅動積體電路晶片覆晶接合在此薄膜電晶 體基板後即可形成覆晶玻璃接合（Chip On Glass ; COG)結 構0 電路基板200主要包括基板201，在基板201之一表面... 吼μ w not one ice, / knife, do not correspond and join to the fifth 塾, wherein the mother a second wire comprises a connecting portion and an extension portion of the extension of the second wire is parallel and juxtaposed A region is external to the second region and parallel to the first wire, and the connecting portions of the second wires extend from the corresponding second bonding pad to engage the corresponding extension. Preferably, the above liquid crystal display panel can be applied to a screen such as a liquid crystal display, a liquid crystal television, a notebook computer, a liquid crystal display device according to the present invention, or a portable electronic device. According to another preferred embodiment of the present invention, a distance between one of the extension portions adjacent to the first bonding pad and the second bonding pad and the adjacent first bonding pad and the second bonding pad is substantially equal to the first The spacing between the bond pads. [Embodiment] The present invention discloses a circuit substrate and an application thereof, which have a high-density bonding pad layout and a preferred process window, thereby shortening the total layout length, increasing the number of pads, and improving the resolution of the liquid crystal display panel, or improving Process yield. In order to make the description of the present invention more detailed and complete, reference is made to the following description and in conjunction with the drawings of Figures 3 through 5. A circuit substrate 200 of a preferred embodiment is suitable for use in accumulating. In the present invention, the circuit board is shown in Fig. 3, which is a schematic view showing the layout of the bonding pads of the circuit substrate in accordance with the present invention. A circuit IC chip is bonded thereto. The right 1363895 200 can be a glass substrate or a flexible circuit board, such as a Flexible Printed Circuit (FPC), a Tape Automated Bonding (TAB) film, or a Chip On Film (COF) ^ The 'glass substrate can be a thin film transistor (TFT) substrate in a liquid crystal display panel. At this time, the integrated circuit chip is flip-chip bonded to the thin film transistor substrate to form a flip-chip glass bond (Chip On Glass; COG) Structure 0 The circuit substrate 200 mainly includes a substrate 201 on one surface of the substrate 201
上，設置有至少一接合區（Block)230。其中，基板201之材 質可例如為前述之軟膜、或硬板，例如玻璃基板。一般而言， 電路基板200包括複數個供輸入訊號之接合墊204、數個供 訊遽輸出之接合塾208與210、以及一些虛設接合塾2〇6。 在本實施例中，電路基板200包括數個接合區230，而輸出 訊號之接合墊佈局202延伸設置在這些接合區23〇上。在一 接合區230中，一組接合墊208並排設置在接合區23〇上， 而另一組接合墊210同樣並排設置在接合區23〇上，其中這 些接合墊210之位置分別與接合墊2〇8相對且相隔一段距離 而互相對齊。在本發明之一較佳實施例中，接合墊之間 可為等距’且接合墊210之間亦對應於這些接合墊2〇8而成 等距排列。 請參照第4圖，其係繪示依照本發明—較佳實施例的一 種電路基板之輸出接合墊的佈局放大示意圖。每個接合墊 2〇8均對應設有-導線212，且每個接合墊21()亦均對應設 有-導線214。這些導線212較佳係平行並列在接合塾川 之下，並分別與對應之接合墊21G接合，且分別自對應之接 1363895 合塾210直接延伸而下。另一方面，每—條導線2i4包括連 接部216與延伸部2丨8,其中每條導線214之連接部216之 -端與對應之接合& 208接合並沿一水平方向朝所有接合 墊208與210之-外側延伸而出，而所有導線2M之延伸部 218則平行並列在所有接合#繼肖21()之一外側的區域 上，而與對應之連接部216的另一端接合，而所有導線214 之延伸部218較佳與導線212平行，如第4圖所示。 在本發明之一較佳實施中，為了縮短導線214之長度， 以避免導線過長使阻抗大為增加，因此將接合墊佈局2〇2 设置在多個接合區230中，每個接合區23〇設置預定通道數 (Channel)之接合墊2〇8與21〇,而最末端之接合區23〇可依 設計需求（例如：積體電路腳位數）或佈局長度（例如：積體 電路長度）限制減少通道數而不一定要與前面各接合區通道 數相同，其中每一排通道中包括一對相對之接合墊2〇8與 210。 在接合區230中，相鄰二接合墊2〇8或相鄰二接合墊 210之間均相隔一段距離224，且任二相鄰之接合塾208或 任二相鄰之接合墊210之間的距離224較佳係均相等。此 外，每個接合墊208與210之寬度222較佳係均相等。因此， 自一接合墊208或210起至相鄰之下一接合墊2〇8或21〇 處之接合塾間隔220，即等於一個接合墊2〇8或2 1 〇之寬度 222與一相鄰之接合墊208或210之間的距離224和，較佳 係均相等。在本發明之一較佳實施中，每個接合區23〇中， 與接合墊20 8及210相鄰之一個延伸部218,其與接合墊208 或210之間的距離226較佳係等於任二相鄰之接合墊2〇8 10 1363895 或任二相鄰之接合墊21〇之間的距離224，如第4圖所示。 此外，整個接合區230中，自一延伸部218起至相鄰之下一 延伸部218處止之導線間距228較佳係相等，由圖可知任 兩鄰之延伸部218由於不會有接合時短路的問題，因此其間 距228係可小於距離224或距離226(接合動作僅產生於有 接合墊208的區域），而由於導線所在區域與接合墊區域 I、Π係有所區分，不再有每一導線與每一接合墊採交互排 列的方式，如此一來相較於習知之佈局，可進一步再拉近接 合墊間的距離。 在本發明之一實施例中，二相鄰接合區23〇之距離，亦 即一接合區230申相鄰於下一接合區23〇之延伸部218與下 一接合區230中相鄰之接合墊208/21〇之間的距離，較佳係 等於任二相鄰之接合墊2〇8或任二相鄰之接合墊21〇之間的 距離224 〇 另外，任何在此技術領域中具有通常知識者皆可認知到 接合墊208與210亦可不互相完全對齊而有一定程度之偏移 量，只要不使距離226小於製程設備的最大接合誤差值即 *crj~ 〇 藉由這樣的接合墊佈局設計，本發明可在相同製程設備 月b力下’提南接合墊之設置密度。舉例而言，請同時參照第 2圖與第4圖，若在目前製程設備能力下，習知技術之輸出 接合塾108的接合墊間距112為70// m，而接合墊1〇8寬 40/zm，導線11〇寬5"m，因而距離116僅餘i2.5"m，如 此提供的製程窗口尚無法滿足現行製程設備能力需求，而本 發明的佈局在各寬度不變的相同條件下之接合塾間距Above, at least one junction 230 is provided. The material of the substrate 201 may be, for example, the aforementioned soft film or a hard plate such as a glass substrate. In general, the circuit substrate 200 includes a plurality of bond pads 204 for input signals, a plurality of bond pads 208 and 210 for outputting signals, and dummy bonding ports 〇2. In the present embodiment, the circuit substrate 200 includes a plurality of bonding regions 230, and the bonding pad layout 202 of the output signals is extended over the bonding regions 23A. In a land 230, a set of bond pads 208 are disposed side by side on the land 23, and another set of bond pads 210 are also disposed side by side on the land 23, wherein the pads 210 are respectively positioned with the bond pads 2 〇8 are aligned relative to one another and at a distance. In a preferred embodiment of the invention, the bond pads may be equidistant and the bond pads 210 may also be arranged equidistantly corresponding to the bond pads 2〇8. Please refer to FIG. 4, which is a schematic enlarged plan view showing the output bonding pad of a circuit substrate according to the preferred embodiment of the present invention. Each of the bonding pads 2 〇 8 is provided with a --wire 212, and each of the bonding pads 21 () is also provided with a --wire 214. Preferably, the wires 212 are juxtaposed in parallel and joined to each other and are respectively joined to the corresponding bonding pads 21G and extend directly from the corresponding 1363895 splicing 210. On the other hand, each of the wires 2i4 includes a connecting portion 216 and an extending portion 2丨8, wherein the end of the connecting portion 216 of each of the wires 214 is engaged with the corresponding joint & 208 and faces all of the bonding pads 208 in a horizontal direction. Extending from the outer side of 210, the extensions 218 of all the wires 2M are parallel and juxtaposed on the outer side of one of the joints 21(), and are joined to the other end of the corresponding connecting portion 216, and all The extension 218 of the wire 214 is preferably parallel to the wire 212 as shown in FIG. In a preferred embodiment of the present invention, in order to shorten the length of the wire 214, to avoid the wire being too long, the impedance is greatly increased. Therefore, the bond pad layout 2〇2 is disposed in the plurality of land 230, each land 23 〇Set the bonding pads 2〇8 and 21〇 of the predetermined channel number, and the endmost bonding area 23〇 can be designed according to the design requirements (for example: the number of integrated circuit pins) or the layout length (for example: the length of the integrated circuit) Limiting the number of channels is not necessarily the same as the number of channels in the previous land, each of which includes a pair of opposing bond pads 2〇8 and 210. In the land 230, the adjacent two bond pads 2〇8 or the adjacent two bond pads 210 are separated by a distance 224 between any two adjacent bond pads 208 or any two adjacent bond pads 210. The distance 224 is preferably equal. Moreover, the width 222 of each of the bond pads 208 and 210 is preferably equal. Therefore, the bonding gap 220 from a bonding pad 208 or 210 to an adjacent bonding pad 2〇8 or 21〇 is equal to a width 222 of a bonding pad 2〇8 or 2 1 与 adjacent to The distance 224 between the bond pads 208 or 210 is preferably equal. In a preferred embodiment of the invention, in each of the land 23's, an extension 218 adjacent the bond pads 20 and 210, the distance 226 from the bond pads 208 or 210 is preferably equal to any The distance 224 between two adjacent bond pads 2〇8 10 1363895 or any two adjacent bond pads 21〇, as shown in FIG. In addition, in the entire land 230, the wire spacing 228 from the extension 218 to the adjacent lower extension 218 is preferably equal. It can be seen that the two adjacent extensions 218 are not joined. The problem of short circuit, so the spacing 228 can be less than the distance 224 or the distance 226 (the bonding action is only generated in the area with the bonding pad 208), and since the area where the wire is located is different from the bonding pad area I, the Π system, there is no longer Each of the wires is arranged in an alternating manner with each of the bonding pads, so that the distance between the bonding pads can be further retracted compared to the conventional layout. In one embodiment of the invention, the distance between two adjacent land 23 ,, that is, a land 230 adjacent to the extension 218 of the next land 23 与 and the adjacent bond pad 208 of the next land 230 The distance between /21〇 is preferably equal to the distance 224 between any two adjacent bond pads 2〇8 or any two adjacent bond pads 21〇. In addition, any person having ordinary knowledge in the technical field It can be recognized that the bonding pads 208 and 210 may not be completely aligned with each other and have a certain degree of offset, as long as the distance 226 is not smaller than the maximum bonding error value of the process device, that is, *crj~ 〇 by such a bonding pad layout design, The invention can set the density of the tipping pad in the same process equipment under the monthly b force. For example, please refer to FIG. 2 and FIG. 4 at the same time. Under the current process equipment capability, the bonding pad spacing 112 of the output bonding port 108 of the prior art is 70//m, and the bonding pad 1〇8 is 40. /zm, the wire 11 〇 width 5 " m, so the distance 116 is only i2.5 " m, so the process window provided can not meet the current process equipment capacity requirements, and the layout of the present invention under the same conditions of the same width Joint spacing
< S 11 1363895 不僅可縮為55/zm，距離224或226仍有i5//m，可提供足 夠製程窗口。從下表-中可知，當上述習知第i圖之接合塾 佈局1G2中接合塾1()8之數量為384肖，整個接合塾佈局 之總長度118為13370/z m，而運用本發明之佈局設計， 如表一第一實施例所示，接合墊佈局2〇2中接合墊與 21〇之數量為384時，整個接合墊佈局202之總長度232為 11 724 // m，因此本發明之接合墊佈局在較小範圍内即可設 置數量與習知佈局相同之接合墊，本發明之接合墊佈局密度 明顯較習知饰局高。 另一方面，如下表一中本發明第二實施例所示，若運用 本發明之佈局設計，在接合墊佈局202之總長度232為 13196ym時，接合墊2〇8與21〇之總數量則可達43〇，而 另一方面，在習知技術的佈局設計中，接合墊佈局1〇2之總 長度118為13370 /z m時，接合墊1〇8之數量僅為384。由 此可見，本發明可在佈局總長度較短的情況下，可佈設遠多 於習知的接合墊數量。 PP (β m) PW (u m) LP (β m) LW (U m) PN BN BCN LBCN TL (μ, m) 習知 70 40 本木 5 384 * * *本 本本 13370 第一 實施例 55 40 9 5 384 10 20 12 11724 第二 實施例 55 40 9 5 430 10 22 17 13196 (表一） 在表中’ PP代表接合墊間距（Pad Pitch) ; PW代表接 12 < S ) 1363895 合塾寬度（Pad Width) ; LP代表導線間距（Line Pitch) ; LW 代表導線寬度（Line Width) ; PN代表接合墊數量（Pad Number) ;BN代表接合區數量（B1〇ck Number) ; BCN代表接 合區中接合墊之通道數（Bl〇ck channel Number) ; LBCN代 表最後一個接合區中接合墊之通道數（Last Bi〇ck Channel Number):而TL則代表整個接合墊佈局之總長度（T〇tal Length) °< S 11 1363895 Not only can be reduced to 55 / zm, distance 224 or 226 still i5 / / m, can provide enough process window. As can be seen from the following table, when the number of the joints (1() 8 in the joint layout 1G2 of the above-mentioned prior art diagram is 384 xiao, the total length 118 of the entire joint layout is 13370/zm, and the present invention is applied. Layout design, as shown in the first embodiment of Table 1, when the number of bonding pads and 21 turns in the bonding pad layout 2〇2 is 384, the total length 232 of the entire bonding pad layout 202 is 11 724 // m, so the present invention The bond pad layout can be set in a small range to provide the same number of bond pads as the conventional layout. The bond pad layout density of the present invention is significantly higher than that of the conventional decoration. On the other hand, as shown in the second embodiment of the present invention in Table 1 below, if the layout design of the present invention is applied, when the total length 232 of the bond pad layout 202 is 13196 μm, the total number of the bonding pads 2〇8 and 21〇 is Up to 43 〇, on the other hand, in the layout design of the prior art, when the total length 118 of the bond pad layout 1 为 2 is 13370 /zm, the number of the bonding pads 1 〇 8 is only 384. From this, it can be seen that the present invention can be arranged far more than the conventional number of bonding pads in the case where the total length of the layout is short. PP (β m) PW (um) LP (β m) LW (U m) PN BN BCN LBCN TL (μ, m) Conventional 70 40 Wood 5 384 * * * Book 13370 First Embodiment 55 40 9 5 384 10 20 12 11724 Second Embodiment 55 40 9 5 430 10 22 17 13196 (Table 1) In the table 'PP stands for Pad Pitch; PW stands for 12 < S ) 1363895 Width ( Pad Width) ; LP stands for Line Pitch; LW stands for Line Width; PN stands for Pad Number; BN stands for B1〇ck Number; BCN stands for joint in the joint The number of channels of the pad (Bl〇ck channel Number); LBCN represents the number of pads in the last land: (Last Bi〇ck Channel Number): TL represents the total length of the entire pad layout (T〇tal Length) °
因此，運用本發明之接合墊佈局設計，可縮短接合墊佈 局的總長度、或可在預定佈局長度下增加接合墊數量、亦或 者可在無需增加接合墊數量與縮短佈局總長度的情況下獲 得較大之製程窗口，有效提高製程良率。 本發明之電路基板可應用在液晶顯示面板中的薄膜電 晶體基板，而液晶顯示面板可應用於液晶顯示裝置中，例如 液晶顯示器、液晶電視、筆記型電腦、或可攜式電子設備之 螢幕。舉例而言，請參照第5圖，其係繪示依照本發明一較 佳實施例的一種液晶顯示面板之裝置示意圖。液晶顯示面板 300主要可用於製作液晶顯示裝置，其中此液晶顯示面板 3〇〇主要包括背光模組302以及液晶顳示模組3〇4。背光模 組302設於液晶顯示模組3〇4之背面，以提供背光源予液晶 顯不模組304。液晶顯不模組3〇4 —般包括彩色渡光片（CF) 基板308、薄膜電晶體基板3〇6、以及封設在彩色遽光片基 板308與薄膜電晶體基板3〇6所構成之空間内的液晶層（未 繪示於圖中）。在本發明中’薄膜電晶體基板3〇6可採用上 述之電路基板200。由於薄膜電晶體基板3〇6採用了電路基 板200’因此可提高薄膜電晶體基板3〇6之接合區上二 13 1363895 接合墊佈局密度，而可大幅提升液晶顯示面板300之解析戶 及製程良率。將液晶顯示面板300應用於液晶顯示裝置時二 可提而產品規格及良率’強化產品之市場競爭力。 由上述本發明較佳實施例可知，本發明之一優點就是因 為本發明之電路基板係將每個接合墊之導線集中設置在這 些接合墊區域之一側，進一步將接合墊兩兩對應設置，因此 可縮減整個接合區之佈局長度。 由上述本發明較佳實施例可知，本發明之另一優點就是 • 因為本發明之電路基板可在現行設備的生產條件與製程能 力下，擴大接合區之接合墊設置的製程窗口，進一步達到提 南接合製程之良率的目的。 由上述本發明較佳實施例可知，本發明之又一優點就是 因為本發明之液晶顯示面板的接合區可在相同寬度下，設置 更多之接合墊，因此可提升佈局積集度，增加液晶顯示裝置 之解析度。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 • 限定本發明，任何在此技術領域中具有通常知識者，在不脫 離本發明之精神和範圍内，當可作各種之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係繪示習知電路基板之接合墊的佈局示意圖。 第2圖係繪示習知電路基板之輸出接合墊的佈局放大 示意圖。 第3圖係繪示依照本發明一較佳實施例的一種電路基 1363895 板之接合墊的佈局示意圖。 第4圖係繪示依照本發明一較佳實施例的一種電路基 板之輸出接合墊的佈局放大示意圖。 第5圖係繪示依照本發明一較佳實施例的一種液晶顯 示面板之裝置示意圖。 【主要元件符號說明】Therefore, with the bond pad layout design of the present invention, the total length of the bond pad layout can be shortened, or the number of bond pads can be increased under a predetermined layout length, or can be obtained without increasing the number of bond pads and shortening the total length of the layout. Larger process window, effectively improve process yield. The circuit substrate of the present invention can be applied to a thin film transistor substrate in a liquid crystal display panel, and the liquid crystal display panel can be applied to a liquid crystal display device such as a liquid crystal display, a liquid crystal television, a notebook computer, or a screen of a portable electronic device. For example, please refer to FIG. 5, which is a schematic diagram of an apparatus for a liquid crystal display panel according to a preferred embodiment of the present invention. The liquid crystal display panel 300 is mainly used for fabricating a liquid crystal display device. The liquid crystal display panel 3 includes a backlight module 302 and a liquid crystal display module 3〇4. The backlight module 302 is disposed on the back surface of the liquid crystal display module 3〇4 to provide a backlight to the liquid crystal display module 304. The liquid crystal display module 3〇4 generally includes a color light-emitting sheet (CF) substrate 308, a thin film transistor substrate 3〇6, and a color light-emitting sheet substrate 308 and a thin film transistor substrate 〇6. The liquid crystal layer in the space (not shown in the figure). In the present invention, the thin film transistor substrate 3〇6 can employ the above-described circuit substrate 200. Since the thin film transistor substrate 3〇6 adopts the circuit substrate 200', the layout density of the bonding pads on the bonding region of the thin film transistor substrate 3〇6 can be improved, and the resolution of the liquid crystal display panel 300 and the process can be greatly improved. rate. When the liquid crystal display panel 300 is applied to a liquid crystal display device, the product specifications and yields can be enhanced to enhance the market competitiveness of the product. According to the preferred embodiment of the present invention, one of the advantages of the present invention is that the circuit substrate of the present invention is provided with one of the bonding pad wires on one side of the bonding pad regions, and the bonding pads are further disposed correspondingly. Therefore, the layout length of the entire land can be reduced. According to the preferred embodiment of the present invention, another advantage of the present invention is that the circuit board of the present invention can expand the process window of the bonding pad setting of the bonding area under the production conditions and process capabilities of the current equipment, and further improve The purpose of the yield of the South Bonding Process. According to the preferred embodiment of the present invention, another advantage of the present invention is that since the bonding area of the liquid crystal display panel of the present invention can be provided with more bonding pads under the same width, the layout degree can be improved and the liquid crystal can be increased. The resolution of the display device. While the present invention has been described above in terms of a preferred embodiment, it is not intended to be construed as limiting the scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the layout of a bonding pad of a conventional circuit substrate. Fig. 2 is a schematic enlarged plan view showing the output bonding pads of the conventional circuit substrate. 3 is a schematic view showing the layout of a bonding pad of a circuit board 1363895 according to a preferred embodiment of the present invention. Figure 4 is a schematic enlarged plan view showing an output bonding pad of a circuit board in accordance with a preferred embodiment of the present invention. Figure 5 is a schematic diagram of an apparatus for a liquid crystal display panel in accordance with a preferred embodiment of the present invention. [Main component symbol description]
100 ： 電路基板 102 ： 接合墊佈局 104 ： 輸入接合墊104 108 ： 輸出接合塑* 108a :輸出接合墊 108b :輸出接合整 108c :輸出接合墊 108d •輸出接合塑* 110 ： 導線 110a :導線 112 ： 接合墊間距 114 ： 寬度 116 ： 距離 118 ： 總長度 200 ： 電路基板 201 ： 基板 202 ： 接合塾佈局 204 ： 接合墊 206 ： 虛設接合塾 208 ： 接合塾 210 ： 接合塾 212 ： 導線 214 ： 導線 216 ： 連接部 218 ： 延伸部 220 ： 接合墊間距 222 ： 寬度 224 ： 距離 226 ： 距離 228 ： 導線間距 230 ： 接合區 232 ： 總長度 300 ： 液晶顯示面板 302 ： 背光模組 304 ： 液晶顯示模組 306 ： 薄膜電晶體基板 15100 : circuit substrate 102 : bond pad layout 104 : input bond pad 104 108 : output bond pad * 108a : output bond pad 108b : output bond pad 108c : output bond pad 108d • output bond pad * 110 : wire 110a : wire 112 : Bond pad spacing 114: Width 116: Distance 118: Total length 200: Circuit substrate 201: Substrate 202: Bonding layout 204: Bonding pad 206: dummy bonding 208: Bonding 210: Bonding 212: Wire 214: Wire 216: Connecting portion 218: extending portion 220: bonding pad spacing 222: width 224: distance 226: distance 228: wire spacing 230: bonding area 232: total length 300: liquid crystal display panel 302: backlight module 304: liquid crystal display module 306: Thin film transistor substrate 15
< S 1363895 308 :彩色濾光片基板 I :區域 330 :接合區 Π :區域<S 1363895 308: Color filter substrate I : Area 330 : Junction area Π : Area
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