TWI363500B - Decoding method and system for low-density parity check code - Google Patents

Decoding method and system for low-density parity check code Download PDF

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TWI363500B
TWI363500B TW097143816A TW97143816A TWI363500B TW I363500 B TWI363500 B TW I363500B TW 097143816 A TW097143816 A TW 097143816A TW 97143816 A TW97143816 A TW 97143816A TW I363500 B TWI363500 B TW I363500B
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parity check
block
odd
check matrix
decoding
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TW097143816A
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Chinese (zh)
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TW201019608A (en
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Yeong Luh Ueng
Chung Jay Yang
Zong Cheng Wu
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Nat Univ Tsing Hua
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1363500 31(43-12)及 18(61-43)。 要之A6|[k-1],A12[k-l]&A 讀取。Asi[k-ll,A12[k-1〗及 A 在階段0,用於線性區塊碼(:<0)解碼所需 «[k-ι]分別從 FIFO-O,FIFO-1 及 FIFO-2 中 明取。λ61Μ’λ12Μ及λα]]也分別在階段i儲存於奶㈤他⑼ 及 REG1 之 U0 中。在階热,i ^ ^ ^ ____“1363500 31 (43-12) and 18 (61-43). A6|[k-1], A12[k-l]&A is read. Asi[k-ll, A12[k-1] and A in phase 0, required for linear block code (:<0) decoding «[k-ι] from FIFO-O, FIFO-1 and FIFO respectively -2 Take it in the middle. λ61Μ'λ12Μ and λα]] are also stored in stage (i) in milk (f) (9) and U0 of REG1, respectively. In the order heat, i ^ ^ ^ ____"

因為在記憶區塊Mb°a t HFO-O,FIFO-1及FIFO-2的所有長 度大於5 ’在五級讀解碼過程中,這些FIFQs*是空的。因此, 在記憶區,MB:中沒有儲存器存取危障。現在考慮記憶區塊㈣, 其在儲存祕取時有危障。起初,在記憶區塊mb?巾之FiF〇_〇, FIF(M立及FffO-2的長度分別為42,52及2。nF〇 2的長度小於 5這思味著FIFO-2 字處於無值狀態。此外,在五解碼階段内, 我們必/頁更新|位元節點、之事後機率兩次。對於這個問題, 我們將在下文卜丨紹解決方案。目9A揭示了記憶區塊之結 構』。除了以下的不同’記憶區塊㈣之結構與記憶區塊吨相同。 在記憶區塊MB:及ΜΒ;。中,FIF⑽及FIF(M之輪入分別從卿〇 及REG1之輸出而得。然而,為了避免在管線解碼中發生f正〇 2 之無值現象,在記憶區塊MBl。巾,nFQ_2的輸人從观⑽而不是 职〇2之輸出而得。在記憶區塊mb〖及mb?,REG0,REG1及REG2 之輸入分職FIFai,FIFa2及FIF⑽娜。細,在記憶區 塊啊中另外具有提供資料至REG1之U3的輸入管道。具有這樣 的、、Ό構’我們可以將拙⑴的UQ,m及U2當作在五階段解碼時 用於FIFO 2之擴展緩衝器。基於圖9八所揭示之結構,在解碼圖 15Since all lengths of FIFO-1 and FIFO-2 are greater than 5' in the memory block Mb°a HFO-O, these FIFQs* are empty during the five-level read decoding process. Therefore, in the memory area, there is no memory access barrier in MB:. Now consider the memory block (4), which is dangerous when storing secrets. At first, in the memory block mb?FiFi〇_〇, FIF (M and FffO-2 are 42, 52 and 2. The length of nF〇2 is less than 5, which means that the FIFO-2 word is in the absence. In addition, in the five decoding stages, we must update the bit node and the probability of the bit node twice. For this problem, we will discuss the solution below. Figure 9A reveals the structure of the memory block. In addition to the following differences, the structure of the memory block (4) is the same as that of the memory block. In the memory block MB: and ΜΒ;., FIF (10) and FIF (the round of M is derived from the output of Qing and REG1 respectively) However, in order to avoid the valueless phenomenon of f-positive 2 in the pipeline decoding, in the memory block MB1, the input of nFQ_2 is obtained from the view (10) instead of the output of the job 2. In the memory block mb And mb?, REG0, REG1 and REG2 are divided into FIFai, FIFa2 and FIF(10) Na. Fine, in the memory block, there is an input pipeline that provides information to U3 of REG1. With this, we can UQ, m and U2 of 拙(1) are treated as extension buffers for FIFO 2 during five-stage decoding. The structure disclosed in Figure 9 is decoded in Figure 15

Claims (1)

1363500 101年Z月〖fg修正替換頁 七、申請專利範圍: 1、一種用於低密度奇偶檢查碼之解碼方法,其包含: 獲得一系列區塊碼之一系列奇偶檢查矩陣; 從該系列奇偶檢查矩陣獲得一恆等奇偶檢查矩陣; 將該恆等奇偶檢查矩陣分成一奇數恆等奇偶檢查矩陣及 一偶數恆等奇偶檢查矩陣,其中該奇數恆等奇偶檢查矩陣由該 恆等奇偶檢查矩陣之奇數列組成,該偶數恆等奇偶檢查矩陣由 該恆等奇偶檢查矩陣之偶數列組成;以及 依據該奇數恆等奇偶檢查矩陣及該偶數恆等奇偶檢查矩 陣而解碼該系列區塊碼。 一 2申請專職圍f 1摘叙解碼綠,其巾依據該奇數 惶專奇偶檢查_及_數財相檢查矩陣而解媽該系列 區塊碼之步驟包括: ,據該偶數怪等奇偶檢查矩陣解碼該些區塊碼以獲得一 提供該第一系列之額外值以使依據該奇 3 該些區塊碼時得以使用該第-系列 第等奇偶檢查矩陣解碼該些區塊碼以獲得一 數恆等奇爐查_解碼紗外值錢依據該偶 之額外值。 -塊碼時得以使㈣第二系列 3、 如申請專利範圍第2項所述之 等奇偶檢查雖及核料奇偶m ’其巾依據偶數恆 列區塊碼。 ~~矩陣而連續地解碼該系 4、 如申請專利朗第3項所述之解 檢查節點之複數個位元節點的 ^f法’進-步將包括- -第二指標次集,從而該第二指標 2一第-指標次集及 人集包括對應於該恆等奇偶 21 1363500 .... 101年么月if曰修正替換頁 行具有權重2之該些位元節點的— 才曰才示-人集匕括該些位元節點的另一部分。 μ 圍第4項所述之解媽方法,其中該系列區塊 碼之複數個編碼位元,其被該第二指標 二塊 =申等=输車及奇數怪等奇偶檢查矩:據該 -檢杳節第1項所述之解碼方法,進-步地將包括 及-第二指標次集,從成#沾-人集 檢査矩練等奇偶 指標次集包括該些位元節點㈣點的分,且該第一 1、等如第6項所述之解碼方法,射依據該奇數 查矩陣及該偶數值等奇偶檢查矩陣 區塊碼之步驟包括: ψ'71 等奇偶檢查矩陣解碼該些區塊碼 第一系列之值,賴供該第—㈣ =值奇偶:及查矩陣解碼該些區塊碼時得以使丄= 依據該奇數怪等奇偶檢查矩陣解碼該些區塊碼以獲得一 提供該第二系列之額外值以使依據該偶 數臣專奇赌查_解賴魏_時得喊⑽第 之額外值。 ’ 申=\圍第7顿狀,其付姻奇數 恆等奇偶檢查矩陣及該㈣料奇偶檢查 =一_之值触第二㈣之額外值轉碼該些 區塊碼上該些位元節點之—部分而執行,其被該第二 指標次集而指出。 22 1363500 101年i月 < 日修正替換頁 其中該些1¾¾ 9、如申請專利範圍第丨項所述之解碼方法 係使用管線方式以進行解碼。1363500 101 years Z 〖fg correction replacement page VII, the scope of application for patents: 1. A decoding method for low-density parity check code, comprising: obtaining a series of parity check matrix of a series of block codes; Checking the matrix to obtain an identity parity check matrix; dividing the identity parity check matrix into an odd parity check matrix and an even parity check matrix, wherein the odd parity check matrix is composed of the identity parity check matrix An odd-numbered column consisting of the even-numbered columns of the identical parity check matrix; and decoding the series of block codes according to the odd-numbered parity check matrix and the even-numbered parity check matrix. A 2 application full-time enclosure f 1 excerpt decoding green, the towel according to the odd number 惶 special parity check _ and _ number financial check matrix to solve the series of block code steps include: according to the even parity parity check matrix Decoding the block codes to obtain an additional value for providing the first series to enable decoding of the block codes using the first series of parity check matrices according to the odd 3 block codes to obtain a number Constant odd furnace check _ decoding yarn outside the value according to the additional value of the even. - The block code enables (4) the second series. 3. The parity check as described in item 2 of the patent application scope and the parity parity m' are based on the even-numbered constant block code. Decoding the system 4 in a ~~ matrix, as in the method of claiming a plurality of bit nodes of the de-checking node described in the third item of claim 3, the step-by-step will include - the second indicator sub-set, thereby The second indicator 2 - the first indicator set and the person set include corresponding to the identity parity 21 1363500 .... 101 years of the month if the correction of the replacement page row has the weight 2 of the bit nodes - only The display-person set includes another part of the bit nodes. μ The method of solving the mother described in item 4, wherein the plurality of coding bits of the series of block codes are the parity check heads of the second index = Shen et al = transport and odd odds: according to the - The decoding method described in item 1 of the inspection section further includes, in addition to - the second indicator sub-set, from the set of parity indicators such as the "dip-person set check", including the bit nodes (four) points And the decoding method according to the sixth aspect, wherein the decoding method according to the sixth aspect, the step of detecting the parity check matrix block code according to the odd matrix and the even value includes: decoding a parity check matrix such as ψ '71 The value of the first series of block codes is obtained by the first-(four)=value parity: and the matrix is decoded to decode the block codes, so that the block codes are decoded according to the odd parity check matrix to obtain a block code. The additional value of the second series is provided to make the extra value of the (10) according to the even number of gambling. '申=\ circumference 7th shape, the odd parity parity check matrix and the (four) material parity check = a value of the second (four) extra value transcode the bit nodes on the block code It is executed in part, which is indicated by the second indicator set. 22 1363500 101 i month < day correction replacement page wherein the decoding method described in the third paragraph of the patent application is pipelined for decoding. H)、於低密度奇偶檢查碼m統,其適用於解碼且 有-奇偶檢查矩陣之健度奇偶檢查碼,該奇紐查矩陣能夠 分成複數個區塊狀區塊行,且從奇偶檢查矩賴得—值 偶檢查矩陣’其能夠分成—奇數•轉奇查矩陣及一偶數惶 等奇偶檢查鱗,其t該奇紐等相檢查矩陣由該值等奇偶 檢查矩陣之奇數列而組成,且該偶數料奇偶檢查矩陣由該怪 等奇偶檢查矩陣之偶數列而組成,該解碼系統包括: 一第一記憶體組,其儲存對應 機率值; 於這些區塊行之複數個事後 一第一記憶體組’儲存從複數個檢查節點至複數個位元節 點之複數個檢查節點至位元節點信息;以及 一處理設備,其電性耦接至該第一記憶體組及該第二記憶 體組以依據該奇奇偶檢查矩陣及該偶等奇偶檢查 矩陣而解碼該低密度奇偶檢查碼之複數個區塊碼。 一 11、如申請專利範圍第10項所述之解碼系統,其中該處理設 備包括: —行至列模組,其電性耦接至該第一記憶體組以從該第一 記憶體組讀取至少一個該些事後機率值並將該讀取之事後機 率,值配置至一列基礎形式; 一檢查節點至位元節點資訊讀取模組,其電性搞接至該第 —3己憶體組以讀取該些檢查節點至位元節點信息; ^ 一檢查節點至位元節點資訊更新模組,其包括複數個檢查 節點至位元節點資訊更新單元,並電性耦接至該行至列模組及 該檢查節點至位元節點資訊讀取模組以接受以該列基礎形式 23 1363500 _ 101年>月fr日修正替換苜 彳域率健所讀取找些檢查^ 祕的該些檢絲點至位元節點f訊更新單元用 第1=輸^一個該些位元節點至該些檢查節點的複數個 矩陣‘ H’且此位元節點對應於該偶數恆等奇偶檢杳 矩ί之—仃,另—部份的該些檢查節點至位元節點資訊更新i 至該錄查節點的 恒等奇偶檢:且此另-個位元節點對應於該奇數 差異计算模組,其電性輕接 息更新模組,該差異計算模組包括至=== 點至位元節點信息更新模_輸出而計算出一新的 檢一即點至位4點資訊及—新的列基礎形式事後機率值; /至行模組n關接至該差異計算模缺該第-記 憶體組以將該新的列基礎形式事後機率值配置至一適;儲存 於該第一記憶體組之新的事後機率值;以及 -檢查節點錄元節雜息寫續組 異計算模組及該第二記憶體組以接受該新的檢杳== 節點資訊並將該新的檢查節點至位元節點資訊;乂= 記憶體組。 12、 如申請專利範圍第u項所述之解竭系統 憶體組包括: ^ 〇& 複數個第-記憶區塊,每個該些第一記憶區塊儲存對應於 一個該些區塊行之該些事後機率值;以及 複數個暫存器槽,每個該些暫存器槽包括至少一個暫存器 且用於儲存㈣絲-記㈣塊讀取之該些事後機率值。 13、 如中請專利範圍第利所述之解爾、統,其中該第一記 24H), in the low density parity check code m system, which is suitable for decoding and having a parity check code of a parity check matrix, the odd Newcha matrix can be divided into a plurality of block block rows, and from the parity check matrix The Dependent-Valued Check Matrix 'is capable of being divided into odd-odd-transitive odd-check matrices and even-numbered 惶 parity check scales, where the odd-phase check matrix is composed of odd-numbered columns of parity check matrices such as values, and The even parity check matrix is composed of even columns of the odd parity check matrix, and the decoding system includes: a first memory group storing corresponding probability values; and a plurality of after-the-first memories in the block rows The volume group 'stores a plurality of check nodes from the plurality of check nodes to the plurality of bit nodes to the bit node information; and a processing device electrically coupled to the first memory group and the second memory group And decoding a plurality of block codes of the low density parity check code according to the odd parity check matrix and the even parity check matrix. The decoding system of claim 10, wherein the processing device comprises: a row-to-column module electrically coupled to the first memory bank to read from the first memory group Taking at least one of the after-effect values and configuring the read probability, the value is configured into a basic form; a check node to the bit node information reading module, and electrically connecting to the third-order memory The group is configured to read the check nodes to the bit node information; ^ a check node to a bit node information update module, which includes a plurality of check nodes to the bit node information update unit, and is electrically coupled to the row to The column module and the check node to the bit node information reading module to accept the column basic form 23 1363500 _ 101 years > month fr day correction replacement area rate health read to find some check ^ secret The check points to the bit nodes f update unit use the first = one of the bit nodes to the plurality of matrices 'H' of the check nodes and the bit nodes correspond to the even parity check Moment ί - 仃, another part of the inspection The node-to-bit node information update i to the parity check of the record node: and the other bit node corresponds to the odd difference calculation module, and the electrical light contact update module, the difference calculation mode The group includes to the === point-to-bit node information update mode_output to calculate a new one, that is, the point-to-point 4 point information and the new column basis form after-effect probability value; Up to the difference calculation mode, the first-memory group is configured to configure the new column basis form after-effect rate value; a new after-effect probability value stored in the first memory group; and - checking the node recording element section The suffocating writes the contiguous group computing module and the second memory group to accept the new check == node information and the new check node to the bit node information; 乂 = memory group. 12. The depletion system as described in claim U, wherein the memory group includes: ^ 〇 & a plurality of first memory blocks, each of the first memory blocks corresponding to one of the block rows And the plurality of register slots, each of the register slots includes at least one register and is configured to store the after-effect values of the (four) silk-to-four (four) block read. 13. If the scope of the patent application is mentioned in the scope of the patent, the first record 24 憶體組包括: 複數個第一記憶區塊,每個該此一^ 一個該些區塊行之事後機率值髓塊儲存對應於 複數個暫存器檔,每個該些暫 且用於儲存從該些第—記塊讀m至^個暫存器 14、如申請專利範圍第13項所述之解事後機· 第一記憶區塊對應於一個該些暫存器^;系統’其中一個該些 記憶區塊讀取之該事後機率值被儲存一侧些第一 暫存器檔。 子主該相對應之一個該些 卜如申請專利範圍第1G項所述之 憶體组被配置為適合以管線方式解;’n第:記 式被分成—默數量之階段。’且此管線方 Μ、如申請專利範圍第15項所述之解 憶體組包括: 焉系統,其中該第一記 複數個第-記舰塊,每個該些第—記 —個該些區塊行之該些事後機率值;以及1、於 複數個暫存n檔,每個該些暫存器 之暫存器且祕儲存從該此第(匕㈣預疋數置 率值。 子錢區塊讀取之該些事後機 H料鄕_ 16項所述之解料統,射每齡此 ^-疏區塊齡成複數鑛存區域,該 - ==且二存於該終點儲存區域之該些=機: 妁數里小於該預定數量的時候, 卞阻 從該些儲存區域中之一先前儲存區域中讀取 =機該先前儲存區域中所儲存 二: 近該終點儲存區域中所儲存之該些事後機率值,且由 25 U0J!)00 * 101年么月,X日修正替換頁 存域令所讀取的該些事後機率值被儲存於 及該些暫存器射之-先前暫存器檔内;以及·.存_ 暫存11檔之輸出賴存在該些暫存諸t之-软 點暫存盗檔中的-個暫存器内,其中該終點暫存器二 存從該終點儲存區域讀取之該些事後機率值。β又並儲 18、如申請專利範圍第1G項所述之解碼系統, 一 f體組的配置使㈣解題_碼複油健Γ奇偶:己 查碼,該些絲度相射碼具衫_率及碼長。 =1:專利範圍第18項所述之解碼系統’其中該第-記 星- r記憶區塊’每個該些第一記憶區塊儲存對應於 ί $ "τ r之事後機率值’且每個該些第一記憶區塊被分 ί 每個該些低密度奇偶檢查碼之奇偶檢查矩陣 上一最大仃權重之一預定數量;以及 平 =個暫存器稽’每個該些暫存器檔包括至少一暫存写且 用於儲存從第-記舰塊讀取 :體圍?18項所述之解二=第-記 =:=式_塊碼之配置方式,且此管 二=專利範圍第20項所述之解碼系統,其中該第-記 複數個第一記憶區塊,每個 ▲ 僅-個該些區塊行之該些事後機=憶區塊儲存對應於 塊被分成該預定數量之儲存區:中憶區 重碼I:對應之該些奇偶檢查矩阵之同-行中 26 9 13635〇〇 . . ------- 101年2月K"曰修正替換頁 " 複數個暫存器檔,每個該些暫存器檔至少包括該預- 之暫存器且用於儲存從該些第一 §己憶區塊讀取之該些事後機 率值。 22、如申請專利範圍第21項所述之解碼系統,其中每個該些 第一記憶區塊被分成複數個儲存區域,該些儲存區域之一為二 終點儲存區域,且當儲存於餅,_存區域之該些事後機 的數量小於該預定數量的時候, 此重Ϊ該些儲存區域中之—歧儲存區域中讀取所健存之該 “ί機率值’該先前儲存區域中_存之該些事後機率值^ 點儲存區域中所儲存之該些事後機率值, 厂节俘器檔中之一先刖暫存器播内;以及 先⑴暫存器檔之輸出被儲存在該些暫存秀於tb ,存II獅的—㈣存其中該終點暫存 子從δ亥終點儲存區域讀取之該些事後機率值。。虽又並儲 27 1363500 四The memory group includes: a plurality of first memory blocks, each of the ones of the block lines of the probability value of the pulp storage corresponding to the plurality of register files, each of which is temporarily used for storing The first block reads m to ^ register 14, the solution as described in claim 13 of the patent scope. The first memory block corresponds to one of the registers; the system 'one of the The event probability values read by the memory blocks are stored on the first temporary register file. The sub-master corresponds to one of the groups of memory groups as described in claim 1G of the patent application, which is configured to be suitable for pipeline solution; the 'nth: record is divided into the stage of the number of silents. 'And this pipeline block, as described in claim 15 of the scope of the memory group includes: 焉 system, wherein the first plurality of first-story blocks, each of the first - note - these The block probability value of the event line; and 1, in a plurality of temporary storage n files, each of the registers of the scratchpad and the secret storage from the first (匕 (four) pre-number of values. The money block reads the after-sales machine H material _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The area=the machine: when the number of turns is less than the predetermined number, the resistance is read from one of the previous storage areas of the storage area=the machine is stored in the previous storage area: near the end storage area The stored probability values of the after-sales are stored by the U.S. - In the previous register file; and ·. _ The temporary output of the 11 files depends on the temporary storage of the t-soft-point temporary piracy The device, wherein the end point of the plurality of register memory afterwards two probability values read from the end of the storage region. β and storage 18, as claimed in the patent scope of the 1G item of the decoding system, a f body group configuration (4) problem solving _ code refueling parity parity: check code, the silky phase of the code with a shirt _ Rate and code length. =1: The decoding system described in claim 18, wherein the first-spot-r memory block stores each of the first memory blocks corresponding to the probability value of ί $ "τ r and Each of the first memory blocks is divided into a predetermined number of one of the maximum weights of each of the low-density parity check codes; and a flat = one register is used for each of the temporary storage blocks The program file includes at least one temporary write and is used for storing the configuration from the first-story block: the solution of the body circumference, the solution of the second item, the first-time ===-type block code, and the tube The decoding system of claim 20, wherein the first-complex number of first memory blocks, each of the ▲-only the block lines of the after-effects=remember block storage corresponding to the block is Divided into the predetermined number of storage areas: Zhongyi District Replica I: Corresponding to the parity check matrix of the same line - 26 9 13635 〇〇. . ------- 101 February K"曰Revision replacement page " a plurality of scratchpad files, each of the scratchpad files including at least the pre-register and for storing from the first § memory blocks Some of the post-machine values. 22. The decoding system of claim 21, wherein each of the first memory blocks is divided into a plurality of storage areas, one of the storage areas being a second end storage area, and when stored in the cake, When the number of the after-storage areas of the storage area is less than the predetermined number, the "copy rate value" stored in the storage area of the storage area is stored in the previous storage area. The after-the-fact probability values are stored in the storage area, and one of the factory-capture files is stored in the temporary register; and the output of the first (1) temporary storage file is stored in the The temporary show is at tb, and the deposit of the II lion - (4) is the probability value of the after-storage read from the end point storage area of the δH. Although it is stored 27 1363500 = . 101年z月(Γ曰修正替換頁 / · - C 、指定代表圖「 (一) 本案指定代表圖為:第(3 )圖。 (二) 本代表圖之元件符號簡單說明: 30 :解碼器 300 :事後機率記憶體模組 310 : R記憶體模組 320 :行至列模組 322 :檢查節點至位元節點資訊讀取模組 324 :, CVMU偶數層 326:CVMU奇數層 328:差異計算模組 330:列至行模組 332 :檢查節點至位元節點資訊寫入模組 五、本案若有化學式時,請揭示最能顯示發明特徵的化學式: 無= . 101 years z month (Γ曰Revised replacement page / · - C , designated representative figure " (1) The representative representative picture of this case is: (3) picture. (2) The symbol of the representative figure is simple: 30: Decoder 300: After-effect probability memory module 310: R memory module 320: row-to-column module 322: check node to bit node information reading module 324:, CVMU even layer 326: CVMU odd layer 328: Difference calculation module 330: column-to-row module 332: check node to bit node information writing module 5. If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention:
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