1363397 九、發明說明： * 【發明所屬之技術領域】 本發明有關一種微機電系統(microelectromechanical systems，MEMS)裝置與半導體裝置之整合結構及製造此種 MEMS裝置與半導體裝置之整合結構之方法。 【先前技術】 馨 MEMS裝置包括具有微機電的基板與微電子電路整合在 一起。此種裝置可形成例如微感應器(micr〇sens〇rs)或微驅動器 (microactuators)，其係基於例如電磁、電致伸縮 (electrostrictive)、熱電、壓電、壓阻(piez〇resistive)等效應來操 作。MEMS裝置可藉由微電子技術例如微影、氣相沉積、及蝕 刻專，於絕緣層或其他之基板上製得。近來，有使用與習知之 類比及數位CMOS (互補式金氧半）電路之同類型的製造步驟 # (例如材料層的沉積與材料層的選擇性移除)來製造MEMS。 採用例如CMOS製程的生產技術來量產舰_裝置，這 樣可以不用更新設備，材料也是CMOS製造時—般使用的材 料。但MEMS也有其特殊十生，因此於製造細⑽結構時可能 會出現-些問題’導致不容易與半導體製程互相整合。例如， 細MS有些藉，在製造時，f要使㈣「濕式_」之释放 製程’在「濕式姓刻」這個處理過程中，氧切犧牲層被例如 &氟酸钮刻劑溶解’由產生的空隙將不同元件分開，但此方法 1363397 極易同N·彳貝害到相鄰的CM〇s介電層。另—種方法是採用氣體 氫氟酸進彳了釋放製程。於習知方法巾，濕式蝴與蒸氣触刻釋 放’都會對CMOS的介電層產生橫向損壞。 因此’對於新穎的半導體裝置與MEMS裝置的整合結構與 其製造方法仍有其需要，以確保MEMS裝置之製造能與CMOS 製造方法相容。 【發明内容】 本發明之一目的是提供一種MEMS裝置與半導體裝置之 整合結構及其製法，如此，可避免半導體裝置在MEMS裝置製 造時被触刻劑侵餘。 依據本發明之MEMS裝置與半導體裝置之整合結構，包括 一基板；一介電層，形成於基板上；一 MEMS裝置，其形成於 基板或介電層中；—半導體裝置，其形成於基板或介電層中； 及一蝕刻停止裝置，其形成於基板上並位於MEMS裝置與半導 體裝置之間之介巾，㈣於MEMS裝置之釋放製程中保護 半導體裝置免於遭受触刻。 依據本發明之製造MEMS裝置與半導體裝置之整合結構 之方法，包括：提供一基板，基板具有一 MEMS區域一蝕刻 停止裝置區域、及一半導體裝置區域，MEMS區域與半導體裝 8 1363397 置區域之間隔著_停止裝置區域，半導體裝置區域之基板設 置有-金氧半電晶體，MEMS區域之基板設置有—第一微機電 元件；於半導體裝置區域之基板上進行一内連線製程，而形成 複數個第-介電層、至少一導電插塞及至少一導電層位於此等 第一介電層中；於敍刻停止裝置區域之基板上形成複數個第二 介電層及-姓刻停止裝置位於此等第二介電層中；於廳紙區 域之基板上形成複數個第三介電層及至少一第二微機電元件位 於此專第三介電廣中；及進行一敍刻製程以移除廳 此等第三介電層。 於依據本發明之MEMS裝置與半導體裝置之整人 中’因為包括-_停止裝置位於—細⑽裝置與—㈣體裝 ^之^，糾，在細MS裝置妓巾進魏切福刻之釋放 製知時，蝕刻停止裝置可做為一蝕 蝕半導妒奘 J爭壁’防止飯刻劑側向侵 +導體裝置。再者’此種蝕刻停止可 置(例如cmos)之製備相宏衣侑導體裝 備 彻内連線製㈣時製徉， 可不使用到半導體裝置以外的材料裟付 之，蝕列Θ 1* # @ ,, I耘、I造設備等；換言 〈蝕刻V止裝置、半導體裝置 一起相容而整合。 MEMS裝置二者之製造可 實施方式】 依據本發明之MEMS裝置與 1363397 ^於半導體裝置甲，在基板上方會進行—内連線製程 置设數層的介電層（或可將其整體視為— 、Μ建 層。為了製程上的便利，本發明之鞋刻停曰止裝塞、導電 線製程而與導電插塞或導電層—起用此内連 如金氧半導體電晶體，軌，可為PM〇s^m包括例 (N型金氧半）、或復〇弘 金乳+)、NM〇s1363397 IX. Description of the Invention: * Technical Field of the Invention The present invention relates to an integrated structure of a microelectromechanical systems (MEMS) device and a semiconductor device, and a method of fabricating the integrated structure of such a MEMS device and a semiconductor device. [Prior Art] A MEMS device includes a substrate having microelectromechanical integrated with a microelectronic circuit. Such devices may form, for example, micro-sensors or microactuators based on effects such as electromagnetic, electrostrictive, thermoelectric, piezoelectric, piezoresistive, etc. To operate. MEMS devices can be fabricated on insulating layers or other substrates by microelectronics such as lithography, vapor deposition, and etching. Recently, MEMS have been fabricated using the same type of fabrication steps as conventional analog and digital CMOS (complementary MOS) circuits (e.g., deposition of material layers and selective removal of material layers). The production technology of the CMOS process is used to mass-produce the ship_device, so that it is not necessary to update the equipment, and the material is also used in the manufacture of CMOS. However, MEMS also has its own special tenths, so there may be some problems when manufacturing fine (10) structures, which makes it difficult to integrate with semiconductor processes. For example, fine MS is somewhat borrowed. At the time of manufacture, f is required to make (4) "wet_" release process. In the process of "wet-type surname", the oxygen-cut sacrificial layer is dissolved by, for example, & Fluoric acid button engraving agent. 'The different elements are separated by the resulting gap, but this method 1363397 is extremely easy to damage the adjacent CM〇s dielectric layer. Another method is to use a gas hydrofluoric acid to release the release process. In the conventional method, the wet butterfly and the vapor touch release will cause lateral damage to the CMOS dielectric layer. Therefore, there is still a need for a novel semiconductor device and MEMS device integrated structure and method of manufacturing the same to ensure that the fabrication of the MEMS device is compatible with the CMOS fabrication method. SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated structure of a MEMS device and a semiconductor device and a method of fabricating the same, which can prevent the semiconductor device from being invaded by the etchant during the manufacture of the MEMS device. The integrated structure of the MEMS device and the semiconductor device according to the present invention includes a substrate; a dielectric layer formed on the substrate; a MEMS device formed in the substrate or the dielectric layer; and a semiconductor device formed on the substrate or And a etch stop device formed on the substrate and located between the MEMS device and the semiconductor device, and (4) protecting the semiconductor device from contact during the release process of the MEMS device. A method of fabricating an integrated structure of a MEMS device and a semiconductor device according to the present invention includes: providing a substrate having a MEMS region-etch stop device region, and a semiconductor device region, the MEMS region being spaced apart from the semiconductor device 8 1363397 region The _stop device region, the substrate of the semiconductor device region is provided with a MOS transistor, the substrate of the MEMS region is provided with a first MEMS element, and an interconnect process is performed on the substrate of the semiconductor device region to form a plurality of a first dielectric layer, at least one conductive plug and at least one conductive layer are located in the first dielectric layers; forming a plurality of second dielectric layers on the substrate of the region of the stop device and a stop device Located in the second dielectric layer; forming a plurality of third dielectric layers on the substrate of the office paper area and at least one second MEMS element is located in the third dielectric; and performing a lithography process Remove the third dielectric layer of the hall. In the whole person of the MEMS device and the semiconductor device according to the present invention, 'because the -_stop device is located in the -10 (10) device and - (4) body mount ^^, the fine MS device wipes into the Weichefu When known, the etch stop device can be used as an etched semi-conducting layer to prevent the rice engraving agent from invading the conductor device. Furthermore, the preparation of such an etch stop can be set (for example, cmos). The phase of the 宏 侑 conductor is equipped with the internal wiring system (4), and can be used without the use of materials other than the semiconductor device, 蚀 Θ 1* # @ @ , I耘, I manufacturing equipment, etc.; in other words, the etching V-stop device and the semiconductor device are compatible and integrated. Manufacture of both MEMS devices can be implemented according to the present invention. The MEMS device according to the present invention and the semiconductor device A, the dielectric layer is disposed on the substrate over the interconnecting process (or can be regarded as a whole) —— Μ 层 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 PM〇s^m includes examples (N-type gold oxide half), or Fuji Hongjin milk +), NM〇s
U讀贿止裝置⑽半導料置與Μ碗 二^MEMS裝置進行釋放製程時保護半導體裝置。 停止裝置可在半導體裝置之製程以外單 =到 裝置之製程中盥半導體穿f一妞制^ 次疋於+導體 導體裝置起製付，而以後者較佳。 =置可有多種形態，可為單—或是堆疊形式恤合起來的^ 或多道形式_卿壁立於半導體裝置與Mems裝置之間。 於單-形式而組合起來的韻刻障壁的情形，韻刻停止裝置 可包括複㈣的複數個柱狀耐㈣材料插塞或是—或多個牆狀 耐餘刻材料織設立於半導财置與mems裝置之「^數 排的複數個柱狀耐_材料插塞」之「複數排」，是指二排或多 於二排，每一排有複數個柱狀耐蝕刻材料插塞。 於堆叠而組合起來的钱刻障壁的情形，钮刻停止裝置可包 括至少-組下狀堆疊：複數㈣複數她狀耐_材料插塞 與-耐㈣材料層互相堆疊而形成於介電層中；或是，一或多 1363397 =狀耐Μ刻材料插塞與—耐_材料層互相堆叠而形成於介 ψ θ令上下久序並無特別限制，即，可為複數排的複數個柱 狀耐朗材_綠上層，材料層在下層；或是，耐 刻材料層在上層，而複數排的複數個柱狀_刻材料插塞在 s同理可為-或多個牆狀耐韻刻材料插塞在上層，而耐 d材料層在下層，或是，耐钱刻材料層在上層，而一或多個 蹁狀耐蝕刻材料插塞在下層。 對於複數排的複數個柱狀耐钱刻材料插塞而言，「複數排 是指二排或多於二排，每—排有複數個柱狀咖刻材料插塞。 ^數排的複數個柱狀耐㈣材料插塞的排列方式，較佳為相鄰 的兩排的鋪彼此交錯排列，以增進整體__劑的效果。 ^刻停止裝置可包括-組或多組如上述之結構。多組結構之間 ^下堆疊’以與釋放製程的MEMS區域有相當的高度或更 耐姓刻材料基本上是在MEMS裝置之釋放製程中 2材料’例如，當釋放製程是仙含有缝__液 石進仃濕式勤]或蒸氣㈣時，則選用耐___料做 11 丄 為耐餘刻材料。耐氫氟酸_材料包括，例如：金屬、多晶石夕， 仁不限於此。其巾’金屬可為例如於半導體裝置製程中常使 的鋁、銅、鎢等。 於本發明中，触刻停止裳置位於半導體裝置與峨細裝置 之間’進-步，侧停找置可環繞MEMS裝置，以對峨^ 裂置以外的區域做完整的防钱刻保護。 第1圖顯示依據本發明之MEMS裝置與半導體裝置之敕人 結構之一具體實施例之示意圖。如第i圖所示，MEMs裝= 半導體裝置之整合結構1G包括—基板12。基板12可為例如^ 導體基板。介電層2卜22 ' 23、24、25形成於基板12上。介 電層可為例如氧切層。—MEMS裝置14形成於基板丨2及此 等；I電層中。-半導體裝置16形成於基板12及此等介電層中。 蝕刻彳T止裝置18形成於基板12上並位於MEMS裝置14與 半導體裝置16之間之此等介電層中。於第1圖中，所示之 MEMS 14僅部分示意性的示出’包括有—多㈣層％， 氧化物層27位於多晶石夕層％與基板12之間，在介電層 25之表面具有—金屬層28。半導體裝置16包括-電晶體29、 導電層 31、32、33、34、35、及 36、導電插塞 40、41、42、 43 44、及45等’也有可能包括其他電晶體、導電層或導電插 t名虫刻+止褒置18包括複數個雜刻材料層5卜52、53、 54、55、及 56、》、> 止，， 次後數個牆狀耐蝕刻材料插塞6〇、61、62、63、 12 1363397 .64、及65。於此具體實施例中，牆狀而編,】材料插塞60、6卜 62 63、64、及65各於每-介電層中有三排的配置與耐鞋刻 材料層5卜52、53、. 55、及56互相堆疊。 • 钱刻停止襄置可設置成圍繞MEMS裝置，以確保保護效 果。第2圖進-步顯示钱刻停止裝置18圍繞mems裝置μ 之頂視示意圖’清楚顯雜刻停止裝置18之耐侧材料層允 •與複數個牆狀耐触刻材料插塞65圍繞著MEMS褒置Η。 第3圖則顯示蝕刻停止裝置圍繞MEMS裝置“之另一具 體實施例之頂視示意圖，其中钱刻停止裝置是由複數排的複數 個柱狀耐敍刻材料插塞66與耐钱刻材料層56所構成。可注意 到相鄰兩排陳狀耐侧材料插塞66是錯開排列。 依據本發明之MEMS裝置與半導體裝置之整合結構之製 矚造’主要是在MEMS裝置與半導體農置之間形成一餘刻停止裝 ，黑。餘刻停止裝置較佳於半導體裝置之製造步驟中同時進行， 例如利用半導體裝置的導電插塞與導電層製程(例如内連線製 程)製造侧停止裝置之牆狀或柱狀耐餘刻材料插塞與耐爛 材料層。因此’柱狀或牆狀雜刻材料插塞與—導電插塞可具 有相同材料’而耐飯刻材料層與導電層可具有相同材料。娜紙 農置亦可於半導體敦置之製造步驟(例如内連線製程)中 得。如此，三區域中同—高度的介電層是同時製造而合為一層。 13 1363397 . 第4至丨〇圖顯示一製造本發明之MEMS裝置與半導體裝 中形成二道溝渠(trench)。然後 以於介質孔與溝渠中填入金屬 置之整合結構之方法之一具體實施例。於此具體實施例中， MEMS裝置為一微型麥克風。請參照第4圖，首先，提供一基 •板12，基板12具有一 MEMS區域102、一蝕刻停止裝置區域 104及半導體裝置區域106。MEMS區域102與半導體裝置 區域106之間隔著蝕刻停止裝置區域1〇4。半導體裝置區域 • 之基板12設置有一電晶體29〇MEMS區域1〇2之基板12設置 有微機電元件38。接著，於基板I2上形成介電層20,或稱 為層間介電層(ILD)。介電層可包括例如氧⑽。平坦化之後， 進行-微影與触刻製程，於半導體裝置區域1〇6之介電層2〇 中形成介質孔(via)，並於敍刻停止裝置區域刚之介電層2〇 ，進行金屬沉積製程及平坦化U reading bribe device (10) semi-conducting material and bowling device 2 ^ MEMS device to protect the semiconductor device during the release process. The stop device can be used in the process of the semiconductor device alone. In the process of the device, the semiconductor device is manufactured by the semiconductor device, and the latter is preferred. = can be in a variety of forms, can be single - or stacked form of the ^ or multiple forms of _ _ _ standing between the semiconductor device and the Mems device. In the case of a monolithic combination of rhyme barriers, the rhyme stop device may comprise a plurality of (4) columnar resistant (four) material plugs or - or a plurality of wall-like residual materials woven in semi-conducting The "complex row" of the "multiple columnar resistance-material plugs" of the "memory row" of the mems device means two rows or more rows, and each row has a plurality of columnar etching resistant material plugs. In the case of stacking and combining the money barriers, the button stop device may comprise at least a group of underlying stacks: a plurality (four) of plural-like material-resistant material plugs and - (four) material layers stacked on each other to form in the dielectric layer Or, one or more 1363397 = etch-resistant material plugs and - _ material layers are stacked on each other to form a median θ. The upper and lower chronological order is not particularly limited, that is, a plurality of columns in a plurality of rows耐朗材_Green upper layer, the material layer is in the lower layer; or, the resistant material layer is in the upper layer, and the plurality of columnar _ etched material plugs in the plurality of rows may be - or a plurality of wall-like rhyme-like engravings The material plug is in the upper layer, and the d-resistant material layer is on the lower layer, or the resist-resistant material layer is on the upper layer, and one or more enamel-like etching resistant materials are plugged in the lower layer. For a plurality of columns of column-shaped erosive material plugs in a plurality of rows, "the plurality of rows refers to two rows or more than two rows, and each row has a plurality of columnar cacao material plugs. ^ A plurality of rows of rows The arrangement of the columnar resistant (four) material plugs is preferably such that the adjacent two rows of tiles are staggered with each other to enhance the effect of the overall agent. The indentation stop device may comprise - or more sets of structures as described above. The stacking of multiple sets of structures is equivalent to the height of the MEMS area of the release process or the resistance of the surrogate material is basically in the release process of the MEMS device. 2 For example, when the release process is a fairy with a seam __ When the liquid stone enters the wet type or the steam (4), the ___ material is used as the endurance material. The hydrofluoric acid resistant material includes, for example, metal, polycrystalline stone, and the kernel is not limited thereto. The metal of the towel can be, for example, aluminum, copper, tungsten or the like which is often used in the manufacturing process of a semiconductor device. In the present invention, the etch stop is located between the semiconductor device and the thin device, and the side stops. Surrounds the MEMS device to provide complete protection against damage outside the 峨^ Fig. 1 is a view showing a specific embodiment of a MEMS device and a semiconductor device according to the present invention. As shown in Fig. i, the integrated structure 1G of the MEMs package = semiconductor device includes a substrate 12. For example, a conductor substrate is formed on the substrate 12. The dielectric layer can be, for example, an oxygen-cut layer. The MEMS device 14 is formed on the substrate 及2 and the like; The semiconductor device 16 is formed in the substrate 12 and the dielectric layers. The etched T stop device 18 is formed on the substrate 12 and located in the dielectric layers between the MEMS device 14 and the semiconductor device 16. In the figure, the MEMS 14 shown is only partially schematically shown as including - many (four) layers %, and the oxide layer 27 is located between the polycrystalline layer % and the substrate 12, having a surface on the dielectric layer 25 - metal layer 28. Semiconductor device 16 includes - transistor 29, conductive layers 31, 32, 33, 34, 35, and 36, conductive plugs 40, 41, 42, 43 44, and 45, etc. 'may also include other The crystal, the conductive layer or the conductive plug t-insert + stop 18 includes a plurality of layers of molybdenum material 5 52, 53 , 54, 55, and 56, ",", after the next few wall-shaped etch-resistant material plugs 6〇, 61, 62, 63, 12 1363397.64, and 65. In this embodiment, Wall-shaped,] material plugs 60, 6 and 62 63, 64, and 65 each have three rows of per-dielectric layers and a layer of shoe-resistant material 5, 52, 53, 55, and 56. Stacking • The money stop device can be set to surround the MEMS device to ensure the protection effect. Figure 2 shows the top view of the memory stop device 18 around the mems device μ. The side material layer allows a plurality of wall-shaped etch-resistant material plugs 65 to surround the MEMS. Figure 3 is a top plan view showing another embodiment of the etch stop device surrounding the MEMS device, wherein the money stop device is composed of a plurality of columns of columnar resistant material plugs 66 and a layer of resistant material 56. It can be noted that the adjacent two rows of the aging-resistant material plugs 66 are staggered. The fabrication of the integrated structure of the MEMS device and the semiconductor device according to the present invention is mainly in the MEMS device and the semiconductor farm. Forming a momentary stop, black. The residual stop device is preferably performed simultaneously in the manufacturing steps of the semiconductor device, for example, by using a conductive plug of the semiconductor device and a conductive layer process (for example, an interconnect process) to fabricate the side stop device. a wall-like or column-shaped material-resistant material plug and a layer of resistant material. Therefore, the columnar or wall-shaped material plug and the conductive plug may have the same material, and the rice-resistant material layer and the conductive layer may have The same material can be obtained in the semiconductor manufacturing process (such as the interconnect process). Thus, the same-high dielectric layer in the three regions is simultaneously fabricated and combined into one layer. 13 1363397 Fig. 4 to Fig. 4 shows a specific embodiment of a method of manufacturing a two-channel trench in a MEMS device and a semiconductor package of the present invention, and then filling the dielectric hole and the trench with a metal integrated structure. In this embodiment, the MEMS device is a miniature microphone. Referring to Figure 4, first, a substrate 12 is provided. The substrate 12 has a MEMS region 102, an etch stop region 104, and a semiconductor device region 106. MEMS The region 102 is spaced apart from the semiconductor device region 106 by an etch stop device region 1-4. The substrate 12 of the semiconductor device region is provided with a transistor 29. The substrate 12 of the MEMS region 1200 is provided with a microelectromechanical device 38. Next, the substrate A dielectric layer 20, or an interlayer dielectric layer (ILD), is formed over I2. The dielectric layer may include, for example, oxygen (10). After planarization, a lithography and a lithography process is performed, and the semiconductor device region 1 A dielectric via is formed in the second layer of the electrical layer, and the dielectric layer 2 is immediately formed in the region of the stop device to perform a metal deposition process and planarization.
14 1^53397 接著，請參照第5圖，同上述之方式製得介電層23、24 及25 '導電插塞43、44及45、導電層34、35及36、牆狀耐 蝕刻材料插基63、64及65、耐蝕刻材料層54、55及56。並於 製造導電層35及耐蝕刻材料層55之同時，於MEMS區域1〇2 形成金屬層49 位於MEMS元件39之上方。然後，可進 步形成保護層(passivati〇n hyer) 72覆蓋半導體裝置區域 1〇6。保護層72可為例如利用TE〇s (四乙氧矽烷)製得的氧化 $層' PSG (射層及氮化韻之堆疊。紐形成光阻層 74覆蓋於半導體裝置區域⑽及㈣停止裝置區域刚，做為 之後蝕刻製程之遮蓋。 然後，如下述進行MEMS _ 1〇2之釋放製程。請參照 6圖’首先進行一異向性的深反應離子敍刻(deepreactive-ion eMimg ’ DRIE)之氧化矽乾蝕刻製程，以光阻層％為遮罩， 几件39之間的各介電層（氧切層)敍穿，形成開口 ％，露出 板12，而介電層24、金屬㈣及部分耐钱刻材料層μ亦可 此触刻中被_。再請參照第7圖，再進行—異向性的深反 離子钱刻之魏朗製程，以歧層74為料，可將開口 7 底部之基板12部分移除，此時之開口記為77，而光阻層％ 二盍=介電層(例如介電層24)部分恰可隨此程蝴 …邊，請參照第8 m等向性的祕 如 製程，敍刻赃MS區域102的各介電層，…、札姻 39，可做為微型麥克風的震動 ^ 上的το件 b見風的震動膜。當介電層為氧化石夕時，較名 丄允3397 使用含氫級_卿。雖域料向性祕财^，由於敍 刻停止裝置區域1G4的侧停止裝置提供良好__壁，、所 以半導體裝置區域1G6的半導體裝置及各介電層並 刻的橫向損壞。 丨蝕 接著，繼續完成MEMS裝置之製造。如第9圖所示，移除 柹阻層74’然後全面塗覆一彈性層^’以提供震動膜更好的彈 彈性層78可包括例如塑性橡膠(plastic rubber)、鐵弗隆 (ΓϋΓ)、帕瑞玲(Pyralene⑧’商品名，屬於多氣聯苯一族的化 ^八面胺㈣yamide)。然後於基板12之上表面(或稱正 層光阻層⑽，並覆蓋元件39,再於正面施加― ^ > θ 82 ’ W於後續之背後㈣製程中保護基板正面。缺 Μ::刻製程？ MEMS區域1〇2的基板12财， 来⑶卿）。接著，請參照第1G圖，將膠帶層82及 θ移除，即完成微型麥克風震動臈之製備。 金屬方1去中’各導電層、耐餘刻材料層、及mems元件或 ㈣。曰第可利用1 虫刻方法而形成，也可以利用鑲嵌製程以 電元件之雙鎮㈣Γ的以若干導電層、顧刻材料層、及微機 介電芦22或鑲嵌製程之結果簡要說明之。例如，在形成 妨料對之身後，於介電層22上形成—圖案化之_亭止層 22 # θ 、Ί案化之光阻層(未示出)做為遮罩， 16 1363397 妨介電㈣及㈣層22 _，形成供_ 耐餘刻材料插塞、耐_材料層、及元件39使用的開口 ^層、 沉積一金屬層(例如鋼層），填入開口中，再予以平扭“、、使， 製得如第u圖所示之導電插塞與導電層之雙鑲嵌結旦構匕89= 钕刻材料插基與耐_材料層之雙鑲嵌結構9q 構之元件39。 八百鑲肷結 • 上述為鑲叙結構之一例，本發明不限於此。即，亦可开4 例如牆狀耐侧材料插塞在下層，而耐餘刻材料層堆疊為上t 之雙鑲嵌結構。柱狀耐餘刻材料插塞與耐侧材 曰 構亦然。 隹蹩結 第12圖顯示依據本發明之另—具體實施例之截面示音 圖麵裝置料導體裝置之整合結構％其巾线刻停止 裝置僅藉由形成複數排的複數個柱狀耐㈣材料插塞仍而製 得。同理，於本發明中，钱刻停止裳置亦可僅藉由形成—或複 數排的牆狀耐蝕刻材料插塞而製得。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利 範圍所做之均等變化與修倚，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖顯不依據本發明之MEMS裳置與半導體裳置之整合 17 1363397 結構之一具體實施例之截面示意圖。 第2圖顯示依據*發明之MEMS裝置與半導體纟置之整人 結構之_停止裝置圍繞MEMS裝置之―具體實施例之頂^ 示意圖。 第3圖顯示依據本發明之MEMS農置與半導體裝置之整人 結構之敍刻停止裝置圍繞MEMS裝置 ^正口 視示意圖。 力具體實施例之頂 第4至10圖顯示依據本發明之製造Mem 裝置，整合結構之方法之—具體實關- 第11圖顯示依據本發明之製造MEMS衰置料導體裝置 之整合結構之製法中，利用鑲嵌製程製造導電層'導電插塞、 耐蝕刻材料層、牆狀耐蝕刻材料插塞及MEMS元件之具體實施 例之截面示意圖。 八 ^ 第12圖顯示依據本發明之MEMS裝置與半導體裝置之整 合結構之另—具體實施例之載面示意圖。 【主要元件符號說明】 1G、7〇 MEMS與半導體 12 基板 裝置之整合結構 μ mems裂置 16 半導體裝置 18 餘刻停止裝置 20 〜25 介電層 26 多晶矽層 2Ί 氧化物層 28 金屬層 29 電晶體 18 1363397 31 〜36 導電層 38 微機電元件 39 元件 40 〜45 導電插塞 49 金屬層 51 〜56 而才钱刻材料層 60 〜65 牆狀耐蝕刻材料插塞 66、68 柱狀耐蝕刻材料插塞 72 保護層 74 光阻層 76 開口 77 開口 78 彈性層 80 光阻層 82 膠帶層 84 空穴 86 触刻停止層 88 介電層14 1^53397 Next, referring to FIG. 5, the dielectric layers 23, 24 and 25' conductive plugs 43, 44 and 45, the conductive layers 34, 35 and 36, and the wall-shaped etching resistant material are formed in the same manner as described above. Bases 63, 64 and 65, etch resistant material layers 54, 55 and 56. At the same time as the conductive layer 35 and the etching resistant material layer 55 are formed, the metal layer 49 is formed over the MEMS element 39 in the MEMS region 1〇2. Then, a protective layer (passivati〇n hyer) 72 is formed to cover the semiconductor device region 1〇6. The protective layer 72 can be, for example, an oxidized layer of 'PSG' (a stack of shot layers and nitriding layers) made of TE〇s (tetraethoxy decane). The photoresist layer 74 is formed over the semiconductor device region (10) and (4) stop device. The area is just covered by the etching process. Then, the release process of MEMS _ 1〇2 is performed as follows. Please refer to Fig. 6 'Firstly perform an anisotropic deep-reactive ion characterization (deepreactive-ion eMimg ' DRIE) The dry etching process of the cerium oxide is performed with the photoresist layer as a mask, and the dielectric layers (oxygen cut layers) between the 39 pieces are pierced to form an opening % to expose the board 12, and the dielectric layer 24 and the metal (4) And some of the layer of money-resistant material can also be etched in the etch. _ Please refer to Figure 7, and then - the anisotropic deep anti-ion engraved Weilang process, with the layer 74 as the material, can The substrate 12 at the bottom of the opening 7 is partially removed, and the opening at this time is denoted as 77, and the photoresist layer % 盍 = dielectric layer (for example, the dielectric layer 24) portion can just follow the process, please refer to the eighth The m isotropic nature of the process, the various dielectric layers of the MS area 102, ..., Zao 39, can be used as a micro-microphone ^ On the το piece b see the vibration film of the wind. When the dielectric layer is oxidized stone eve, the name 丄 3 3397 uses the hydrogen-containing grade _ Qing. Although the domain material is visibly secretive ^, due to the narration stop device area 1G4 The side stop device provides good __wall, so the semiconductor device of the semiconductor device region 1G6 and the dielectric layers are laterally damaged. The etch is then completed, and the fabrication of the MEMS device is continued. As shown in Fig. 9, the removal is performed. The barrier layer 74' is then fully coated with an elastic layer to provide a vibrating membrane. The elastic layer 78 may include, for example, plastic rubber, iron swell, and Pyralene 8'. , which belongs to the polyglycol group, is yamide. It is then applied to the upper surface of the substrate 12 (or the positive photoresist layer (10) and covers the element 39, and then applied to the front side - ^ > θ 82 ' W In the back (4) process, the front side of the substrate is protected. The defect is: the engraving process? The substrate of the MEMS area 1〇2, 12 (3) Qing. Then, please refer to the 1G figure, remove the tape layer 82 and θ, That is to complete the preparation of the micro-microphone vibration 。. Metal side 1 goes to the 'each conductive layer Residual material layer, and MEMS element or (4). 曰 can be formed by a method of engraving, or can be made by using a damascene process with a plurality of conductive layers, a layer of material, and a dielectric. The result of the reed 22 or the damascene process is briefly described. For example, after the formation of the baffle pair, a patterned photoresist layer 22 # θ, a patterned photoresist layer is formed on the dielectric layer 22 (not shown) As a mask, 16 1363397 may be dielectric (4) and (4) layer 22 _, forming an opening for the _ material-resistant material plug, _ material layer, and element 39, depositing a metal layer (such as steel Layer), filled in the opening, and then flattened "," to make a double-inlaid junction structure of conductive plug and conductive layer as shown in Fig. u = engraved material interposer and resistant material The element 39 of the double damascene structure 9q of the layer. Eight hundred inlaid knots • The above is an example of a studded structure, and the present invention is not limited thereto. That is, it is also possible to open 4, for example, a wall-shaped side material plug in the lower layer, and the residual material layer is stacked in a double damascene structure of the upper t. The column-like residual material plug and the side-resistance structure are also the same. Figure 12 shows an integrated structure of a cross-sectional sounding device device conductor device according to another embodiment of the present invention. The towel line stop device only forms a plurality of columnar resistant (four) materials by forming a plurality of rows. The plug is still made. Similarly, in the present invention, the stagnation of the money can be made only by forming a - or a plurality of rows of wall-shaped etch-resistant material plugs. The above is only the preferred embodiment of the present invention, and all changes and modifications made by the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows an integration of a MEMS skirt and a semiconductor skirt according to the present invention. 17 1363397 A schematic cross-sectional view of one embodiment of a structure. Fig. 2 is a view showing a top view of a specific embodiment of a MEMS device according to the invention of the MEMS device and the semiconductor device. Fig. 3 is a schematic view showing the MEMS device according to the MEMS device and the semiconductor device according to the present invention. The fourth embodiment of the present invention shows a method for fabricating a Mem device according to the present invention, and a method for integrating the structure - a specific implementation - Figure 11 shows a method for manufacturing an integrated structure for manufacturing a MEMS dead conductor conductor device according to the present invention. A cross-sectional schematic view of a specific embodiment of a conductive layer 'conductive plug, an etch-resistant material layer, a wall-shaped etch-resistant material plug, and a MEMS device is fabricated using a damascene process. Figure 8 is a schematic view showing a carrier of another embodiment of the integrated structure of the MEMS device and the semiconductor device in accordance with the present invention. [Main component symbol description] 1G, 7〇 MEMS and semiconductor 12 substrate device integration structure μ mems cleavage 16 semiconductor device 18 residual stop device 20 ~ 25 dielectric layer 26 polysilicon layer 2 Ί oxide layer 28 metal layer 29 transistor 18 1363397 31 ~ 36 Conductive layer 38 MEMS component 39 Component 40 ~ 45 Conductive plug 49 Metal layer 51 ~ 56 and material layer 60 ~ 65 Wall-shaped etching resistant material plug 66, 68 Column-shaped etching resistant material insert Plug 72 protective layer 74 photoresist layer 76 opening 77 opening 78 elastic layer 80 photoresist layer 82 tape layer 84 hole 86 etch stop layer 88 dielectric layer
89 導電插塞與導電層之雙鑲嵌結構 90 耐蝕刻材料插塞與耐蝕刻材料層之雙鑲嵌結構 102 MEMS 區域 104 蝕刻停止裝置區域 106 半導體裝置區域 1989 Double damascene structure of conductive plug and conductive layer 90 Double damascene structure of etch resistant material plug and etch resistant material layer 102 MEMS area 104 Etch stop device area 106 Semiconductor device area 19