九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種紅外線熱影像陣列模組，其係特別有關於紅外線 熱影像陣列模組驗證架構與製造方法。 — 【先前技術】 隨著必須滿足各種熱像應用的特殊需求，在陣列感測模組材料的選 擇、最佳化元件結構設計與提升熱影像解析度及偵檢度，過去十多年來均 為開發高品質之紅外線熱影像陣列模組並盼望達到之目的。舉例來說：20呢 年曰本Masalkar等人（US 20020088943A1)，針對感測架構中多重量子井 製程架構的改進與簡化製程之步驟提出，可有效提升感測，元件的檢測效 率，在2004年，美國jeffrey b Bart〇n等人⑽ 2〇_〇61〇56a1) ’提出 鱗化銦基板下_新設計之近紅外光錄雜與提出針對模組製程改進方 法用於偵檢陣列架構上；2005年美國Michael G. Engelmann (US 2005_4麵1) #人針對大晝數練析度可絲與近紅彳紳列型影像 感測器模組架構提出改良性架構，同年Frederick E. K〇ch等人（us 200500171·1) ’ f次提出量子點紅外雜平鱗顺組結合⑽激號讀 取電路架構之熱影像應用。 總括說來’由於熱像模組開發需要各種不同專業領域技術人員，例如， -個完整紅外祕雜_微，包七.制元僻列蟲晶與設計需要物 理、光電材料、材·晶專長，陣列式光訊號讀取碰電路（腿c)單元 需要積體電路、触數位電子專長及細像校正電路需要邏輯電路與 影像電路设計專長’整體模組最佳整合與偵錯需要影像系統驗證專長人 員。之前，整合技術開發時，只在個別專業固有專長領域中進行局部性能 最佳化驗證’並緖λ-套具敝外、雜賴峨峰證絲與其結構製 作整合方法。 因此’本發明.針對上述問題而提出一種紅外線熱影像陣列模組驗證 架構與製造綠，不财《:讀職f彡像_椒4、異f接合鋪像之架 1360881 構與製作流程之缺點，又可應用在不同熱影像感測材料、異質接合與顯像 之架構與製作流程’並提相發各種錄_觀巾之偵錯效率，可解決 上述之問題。 【發明内容】 本發明之主要目的’在概供—歡雜祕鱗賴_證架構葬 裝造方法，其提升陣列感測模組性能及偵錯效率。 =明之另-目的，在於提供-種紅祕細轉賴組驗證架構孽 臬知·方法，其有效降低研發之成本。 本發料對紅外賴f彡辦聰城縣鑛製造紐，其包含一南 格ί組Γΐ設!^晶與辨紐碰，彡_行如參數校正；_ 導敎“ 7乙型感測元件製程與變溫光電量測驗證，實縣晶完治 變溫與變壓量測同抽導線或低雜訊號線導出，經過低這 後即進行—隹平暗電阻、響應頻譜、偵檢度校正，合格繼 陣列製程及#格後’繼續進行該焦平面 陣列製程，而製作符合設定之感測元件規格’進行焦平面 試區域進行^ 獅彳谢_，魏，選定測 讀咖=:====嫩㈣㈣列與訊號 晶與=輸驗證重^程知，不合格則返嘴模組規袼設計、蟲 驗證合3平辦列與訊號讀崎體電路貼合與磨薄製程 組進行光電==細输物^-測陣列模 :後::=返回焦乎_製程及峨均勻_= 翰出參數，以進行模組熱影像品質分析與測定；合格此驗 1360881 證後即進行-熱影像陣列模組離型，不合格則返回焦平面陣列與訊號讀出 積體電路貼合與磨薄製程驗證重新驗證。 合格後，繼續進行該熱影轉列模組_，制賴柱貼合方式與焦 平面感測陣列接合，每_單元_光電賴存至積分電容喊，使列與 行多工器依序經峨輸出端送至感測器緩衝板模組與料處理祕内進行 影像訊號處理，崎成影__模組_。如此，可提高陣规測模組 性能，縮短偵檢模組之驗證期程。 【實施方式】 兹為使貴審查委員對本發明之結構特徵及所達成之功效有更進一步 之瞭2與綱，雜雜佳之實麵及配合麵之綱，綱如後： 請參閱第-圖，其為本發明之紅外線熱影像陣列模組驗證架構之流程 圖如圖所*本發明包含一熱像模組規格設計、蟲晶與光學物性驗證1〇， 須先進行蟲贼制驗、巾、長紅外線吸收波段； :感職組紅外線穿透基板102選擇感測模組之品紐劣，即影響接收波 #又之、’外線穿透率，一底端局摻雜接觸層1〇4，紅外線其秦響半導體與導電 觸品f卜紅外線吸收層又稱主崎其週期數⑽，吸收紅外線 == 量t效率；，層或空乏層108,吸收紅外線之厚度與 豳傲影響里子效率與感測元件暗電_;—能障阻擋層110 ’影 質阻抗’以符合高注入光電流效率、感測元件暗電流值、操 —竭嶋_丨12，嫩_特性與光 20，格後’即進打—單乙型感測元件製程與變溫光電量測驗證 線導測試絕緣’而以金線經由同軸導線或低雜訊號 校正，入格祕’皿4 '皿與變壓量測其暗電流、暗電阻、響應頻譜、傭度 ㈣㈣輸狀蝴恤證30，不 ·、、顧組祕設計、|晶與鱗雛難1()賴祕；而合格 7 ⑼881 後，繼續断、平面__及q 1 測元件規格，進行焦平面陣列製程，、ϋ =符合設定之感 進行-焦平鱗顺峨糾賴，合格此驗證後即 返回人熱像軸蝴、蝴&====⑼，不合格則 驗證σ4Γ==^Γ、Γ面陣職號讀_電路貼合與磨薄製程 焦平面陣與訊輸積體電路進油貼合，以便使 早夕瓜職組進仃光電喊轉換；—訊號取樣 ==，==雜訊咖叫至—注入單元^ 组單元訊二益^ !；電容1020電荷訊號輸出至輸出端；一放大器模 置循序操取；-時序生成^„414與列416多工選擇器單元，感測單元位 時間，合格此驗70 420，由主時序426控卿取與訊號積分 不合_ (含光機系統）驗證5〇， 人Μ _ 沒程及"先電均勻度驗證30重新驗證。 制最合測試(含光機系 -低溫恤=2 刺雛。°°嶋雜；其卜 ，W管、外;積：:::= ==號_電路之_與：=: 處理㈣，娜’處理影綱訊號並輸出；一控制 χ. 個心7與衫像訊號輸出，並連結主控電腦，入槐屮私说 像處理系統==rrz===彻 8 1360881 請一併參閱第二圖（a)，其為本發明之架構圖。由圖·示可知，本發明 之熱像模組規格設計、蟲晶與光學物性驗證1〇，係依據所設計之參數後， 定義規格所需熱影像陣列模組中紅外線感測元件結構，其利用磊晶與高溫 擴散設備’以分子束蟲晶法（Molecular Beam Epitaxy , MBE )、金屬有機 氣相遙晶法（Metal Organic Chemical Vapor Deposition，M0CVD)或高IX. Description of the Invention: [Technical Field] The present invention relates to an infrared thermal image array module, which is particularly related to an infrared thermal image array module verification architecture and manufacturing method. — [Prior Art] With the special needs of various thermal imaging applications, the selection of array sensing module materials, the optimization of component structure design, and the improvement of thermal image resolution and detection have been performed for more than a decade. In order to develop high-quality infrared thermal image array modules and hope to achieve the goal. For example: 20 years of the year, Masalkar et al. (US 20020088943A1), proposed for the improvement of the multi-quantum well process architecture in the sensing architecture and the simplification of the process steps, can effectively improve the sensing efficiency of components, in 2004 , United States jeffrey b Bart〇n et al. (10) 2〇_〇61〇56a1) 'Under the squamized indium substrate _ new design of near-infrared optical recording and proposed for the module process improvement method for the detection array architecture; In 2005, Michael G. Engelmann (US 2005_4, 1) #人############################################################################################# Et al. (us 200500171·1) 'f times proposed quantum dot infrared squarish squamous group combination (10) thermal imaging application of the singularity reading circuit architecture. In summary, due to the development of thermal imaging modules, technicians in various professional fields are required, for example, a complete infrared secret _ micro, package seven. 元 僻 虫 虫 与 and design requires physical, optoelectronic materials, materials · crystal expertise Array type optical signal reading and touching circuit (leg c) unit requires integrated circuit, touch digit electronic expertise and fine image correction circuit. It requires logic circuit and image circuit design expertise. 'The overall module is optimally integrated and debug requires image system. Verify the expertise. Previously, when integrating technology development, local performance optimization was only carried out in the field of intrinsic expertise of individual professions, and the integration method of the structure and the structure was mixed. Therefore, the present invention provides an infrared thermal image array module verification architecture and manufacturing green for the above problems, and does not finance ": read the job 彡 _ pepper 4, different f joint shop frame 1360881 structure and production process shortcomings It can also be applied to different thermal image sensing materials, heterogeneous bonding and imaging architecture and production process, and to solve the above problems. SUMMARY OF THE INVENTION The main object of the present invention is to improve the performance of the array sensing module and the efficiency of debugging, in the provision of the method. = The other purpose - the purpose is to provide - the red key to the group verification framework 臬 know the method, which effectively reduces the cost of research and development. This issue is for the infrared ray f彡 聪 聪 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县 县Process and variable temperature photoelectric measurement verification, real county crystal treatment temperature change and pressure measurement measured with the same drawing wire or low noise signal line, after the low, then the 隹 flat resistance, response spectrum, detection degree correction, qualified After the array process and #格格' continue to proceed to the focal plane array process, and make the specifications of the sensing components in accordance with the settings, carry out the focal plane test area for ^ 彳 彳 _, Wei, selected test coffee =: ==== tender (4) (4) Column and signal crystal and = transmission verification ^^ know, if it is unqualified, the return module specification design, insect verification and 3 flat and signal reading Saki circuit and the thin process group for photoelectricity == fine Input ^-Measure array mode: After::=Return to the focus _Process and 峨 uniform _= John parameters for module thermal image quality analysis and measurement; qualified after the test 1360881 certificate - thermal image array mode Group release type, if it is unqualified, return to the focal plane array and the signal readout integrated circuit and the thinning process test Re-verification of the certificate. After passing the test, continue the thermal transfer module _, the splicing method is combined with the focal plane sensing array, each _ unit _ photoelectric ray to the integral capacitor shout, so that the column and row multiplex The device is sent to the sensor buffer board module and the material processing secret to perform image signal processing, and the image is processed by the __ module _. Thus, the performance of the array measurement module can be improved, and the detection mode can be shortened. The verification period of the group. [Embodiment] In order to enable the reviewing committee to further improve the structural features and the achieved effects of the present invention, the outlines of the complex and the mating surface are as follows: Please refer to the first drawing, which is a flow chart of the verification structure of the infrared thermal image array module of the present invention. The present invention includes a thermal image module specification design, insect crystal and optical property verification, and must first be wormed. Thief test, towel, long infrared absorption band; : Inductive group infrared penetrating substrate 102 selects the sensing module's product newcomer, that is, affects the receiving wave# again, 'external line penetration rate, a bottom end doping Contact layer 1〇4, infrared light Qinhua semiconductor and conductive contact Infrared absorption layer, also known as the main cycle of the mains (10), absorption of infrared == quantity t efficiency;, layer or depletion layer 108, the thickness of the absorption of infrared rays and arrogance affect the efficiency of the neutron and the sensing element dark electricity _; - energy barrier The barrier layer 110 'shadow impedance' to meet the high injection photocurrent efficiency, the sensing element dark current value, the operation 嶋 嶋 丨 , , , , , 特性 特性 特性 特性 特性 特性 特性 特性 特性 特性 特性 特性 特性 特性 特性 特性 特性 — — — — — — — — — — — The component process and the variable temperature photoelectric measurement verification line guide test insulation 'and the gold wire is calibrated via the coaxial wire or the low noise signal, and the dark cell, the dark resistance, the response spectrum, and the commission are measured. Degree (4) (4) Loss of the 30th, no, and the design of the team, | crystal and scales difficult to 1 () Lai secret; and after passing 7 (9) 881, continue to break, plane __ and q 1 measuring component specifications, carry out The focal plane array process, ϋ = conforms to the sense of setting - the focus is smooth and sloppy, and after passing this verification, it returns to the human thermal image, butterfly &====(9), and if it fails, it verifies σ4Γ== ^Γ,Γ面阵号号 reading_Circuit bonding and thinning process focal plane array and signal transmission integrated circuit oil fitting, It will make the early morning melon group into the photoelectric screaming conversion; - signal sampling ==, == noise coffee call to - injection unit ^ group unit two benefits ^!; capacitor 1020 charge signal output to the output; an amplifier mode Step-by-step operation; - Timing generation ^ 414 and column 416 multiplexer unit, sensing unit bit time, qualified for this test 70 420, master timing 426 control and signal integration is not _ (including optical system) Verification 5〇, Μ _ no way and " first power uniformity verification 30 re-verification. The most suitable test (including light machine system - low temperature shirt = 2 thorns. ° ° noisy; its Bu, W tube, outside; product::::= == _ circuit _ and: =: processing (four), Na 'process the shadow signal and output; a control χ. Heart 7 and shirt image signal output, and link to the main control computer, into the private image processing system == rrz=== 彻8 1360881 Please refer to the same Figure 2(a) is an architectural diagram of the present invention. It can be seen from the figure that the thermal image module specification design, the insect crystal and the optical property verification of the present invention are based on the designed parameters, and the specification is defined. Infrared sensing element structure in a thermal image array module, which utilizes epitaxial and high-temperature diffusion devices, Molecular Beam Epitaxy (MBE), Metal Organic Chemical Vapor Deposition (Metal Organic Chemical Vapor Deposition, M0CVD) or high
溫擴政爐（HTDO)為較佳元件結構製備方式。若將紅外光吸收層設計成 量子侷限架構’如：量子井（Quantum Well)、量子點（Quantum Dot)感 測架構操作，則偏向以分子束蟲晶法或金屬有機氣相遙晶法之方式蟲晶β 反之’若以基體型（Bulk Type) Ρ-Ν、Ρ-Ι-Ν型態為主之感測架構，常 以分子束遙晶法或金屬有機氡相蟲晶法Μ成長N與I層後，再利用高溫擴散爐 擴散出Ρ層。而使用基板可為四族如：石夕（Si)、三五族如：GaAs、InP， 其感測材料、週期架構與厚度分別為：Si/SizGel-z (z=0. 1~0. 5， 10~40nm/l〜l〇nm，10〜50 個週期）、AlxGal-xAs/GaAs (x=0.1 〜0.5， 10〜40nm/l〜lOnm ’ 10〜50 個週期）、AlxGa卜xAs/InyGa卜yAs/GaAs (χ=0· 1〜0. 5，y=0.1 〜0. 3 ’ 10〜40nm/l〜5nm/l〜10nm，10〜50個週期），而基 體型感測材料為InSb、MCT、InP，有I-本質層（厚度：〇〜5ym)之Ρ-I-N架 構’ P極是利用HTD0擴散方式形成，P極擴散材料可為ZnAs化合物、Zn、Cd， 深度:1〜3"m。 §以分子束蠢βθ法、金屬有機氣相蟲晶法或尚溫擴散爐蟲晶與擴散機 台成長所設計感測元件架構前，必須先進行蟲晶參數校正，如：材料沉積 率、週期架構完整性、結構結晶品質、極性與參雜濃度》上述為感測元件 •» 模組架構之磊晶架構設計流程、磊晶參數驗證與感測元件架構。之後，截 取同一片感測元件遙晶片一部分（約晶片總面積1/4〜1/5)，進行單乙型感 測元件製程、光電特性量測驗證20，主要確認實際磊晶完成感測元件架構 與所設計元件結構間的光電特性與品質差異。 在單乙型感測元件製程中，以光罩與實體元件製程線寬誤差〈10%，進 行變溫光電量測驗證時，在HH300K下操作溫度誤差率<15%，得到光譜型態 9 1360881 均勻度>80% ’並調制適當的蝕刻水溶劑（内含弱pjj值酸液：雙氧水：去離 子水=2〜5 : 1〜2:5〜20)，蝕刻深度為元件層架構上層至產生電子—電洞層 間之厚度（約1〜lOvm)’目的為避免側向漏電流，若為平面式（pianar_type) 定義元件區域製程’可用於高溫擴散P_極（擴散深度在〇 5~5Μιη)，再以 表面研磨方式（l~5/zm粒徑之氧化鋁：去離子水=1:2〜5)，研磨至 0. 25〜2μιη ’形成最適當之p-極區域，非元件區域為卜本質層可阻止側向溢 散（Lateral Spreading )電流，而將光電流侷限流經元件主架構層至接 觸電極區’以達到最大量子效率。 之後’可選擇以電漿化學氣相沉積法（Plasma Enhance Chemical Vapor Depositon’PECVD)(基板溫度介於300〜500°C)、光化學沉積法（piasmaThe temperature expansion furnace (HTDO) is a preferred component structure preparation method. If the infrared light absorbing layer is designed as a quantum confinement structure such as Quantum Well or Quantum Dot sensing architecture operation, the method is biased by molecular beam crystallization or metal organic vapor phase crystallization. Insect crystal β, in contrast, if the Bulk Type Ρ-Ν, Ρ-Ι-Ν type is the sensing structure, it is often grown by molecular beam telecrystallization or metal organic 氡 虫 晶After the I layer, the ruthenium layer is diffused by a high temperature diffusion furnace. The substrate can be used for four groups such as: Shi Xi (Si), three or five groups such as GaAs, InP, and the sensing material, periodic structure and thickness are: Si/SizGel-z (z=0. 1~0. 5, 10~40nm/l~l〇nm, 10~50 cycles), AlxGal-xAs/GaAs (x=0.1~0.5, 10~40nm/l~lOnm '10~50 cycles), AlxGab xAs/ InyGa yAs/GaAs (χ=0·1~0. 5, y=0.1 ～0. 3 '10~40nm/l~5nm/l~10nm, 10~50 cycles), while the base type sensing material is InSb, MCT, InP, I-IN architecture with I-essential layer (thickness: 〇~5ym) P pole is formed by HTD0 diffusion method, P pole diffusion material can be ZnAs compound, Zn, Cd, depth: 1~ 3"m. § Before the sensing element structure is designed by the molecular beam stupid βθ method, the metal organic gas phase crystal method or the growth of the furnace and the diffusion machine, the crystal crystal parameters must be corrected, such as: material deposition rate, period Architectural integrity, structural crystallization quality, polarity and doping concentration. The above is the sensing component •» The epitaxial architecture design flow of the module architecture, the epitaxial parameter verification and the sensing component architecture. After that, a part of the same sensing element remote chip (about 1/4~1/5 of the total wafer area) is intercepted, and a single-type sensing element process and photoelectric characteristic measurement verification 20 are performed, mainly confirming the actual epitaxial completion sensing element. The difference in optoelectronic characteristics and quality between the architecture and the component structure being designed. In the process of single-b type sensing element, the line width error of the mask and the physical component is <10%. When the variable-temperature photoelectric measurement is verified, the temperature error rate is <15% under HH300K, and the spectral pattern is obtained. Uniformity >80% 'and modulate the appropriate etching water solvent (containing weak pjj value acid: hydrogen peroxide: deionized water = 2~5: 1~2:5~20), the etching depth is the upper layer of the component layer structure to The thickness of the electron-hole layer (about 1~lOvm) is generated to avoid lateral leakage current. If the planar region (pianar_type) is defined, the component region process can be used for high temperature diffusion P_ pole (diffusion depth is 〇5~5Μιη) , and then by surface grinding (aluminum of l~5/zm particle size: deionized water = 1:2~5), grinding to 0. 25~2μιη 'to form the most appropriate p-pole region, non-element region The intrinsic layer prevents lateral flow of current, while limiting the photocurrent through the element's main architectural layer to the contact electrode region to achieve maximum quantum efficiency. After that, you can choose Plasma Enhance Chemical Vapor Depositon (PECVD) (substrate temperature between 300~500 °C), photochemical deposition (piasma)
Vapor Depositor! ’ PVD)(基板溫度介於80〜200°C)、離子濺鍍（一般使 用He、Ar離子鈍性氣體）、或加熱蒸鍍法成長氧化矽（Si〇x)或氮化矽 (SiNx) ’當作感測元件之表面披覆層H6，厚度介於5〇~3〇〇nm，再以化學 離子乾式法（Reactive Ion Etching，RIE)或濕蝕刻法（氟化氫：去離 子水，Buffer HF : DI water= 1〜5:20)定義出半導體接觸金屬區，而此類 感測元件上114與下1〇1〇電極區使用的接觸金屬材質，若為n型可為把（卩们 1 〜20nm/鉻（Cr) 1〜20nm/金鍺合金（Au/Ge) 50~300nm/金（Au) 50〜300nm , P型可為鈀（Pd) 1〜20nm/鉻（Cr)卜20nm/金鈹合金（Au/Be)或辞（Zn) 50~300nm/金（Au) 50〜300nm，可使用熱蒸鍍、電子搶加溫蒸鍍或離子錢艘 進行金屬電極製作。 快速退火（Rapid Thermal Annealing，RTA)製程是形成於較佳之半 導體與金屬間之歐姆接觸，加溫穩定溫度與時間分別介於35〇~5〇(rc， 15~60sec，加溫溫度斜率1〇〇〜2〇(Tc/sec。若為平台式（Mesa)定義感測元 件區域製程，除了利用光罩顯影定義蝕刻區，飯刻區域深度必須超過下端 咼摻雜極性區厚度之1/3〜1/2之間，其餘製程均以平面式相同。在針對量子 井感測元件架構製程，必須在平台式定義感測元件區域製程之後增加週期 性光柵結構，其結‘構為1维長條狀或2維方形或菱形型態，光柵間距及高度 1360881 < 介於1〜5//πι與10~500咖之間蝕刻方法與平台式感測定義區域製程方式相 同β以上為單乙型感測元件製程主要步郵，其目的是要利用此製程參數作 為之後焦平面陣列架構製作之參考參數。 . 完成單乙型感測元件架構後，以導熱膠貼在測試絕緣基座上（如：氧 化域台基座）’將金線上下訊號端5丨出，放人循環歧態氦低溫變溫真 空腔體中’再將端子pin訊號線經由饋通線（feedthr〇u绅）介面經由同轴 導線或低雜訊訊號線導出，經過低溫變溫與變壓量測其暗電流、暗電阻、 響應頻譜（如··以FTIR光譜分析儀··入射光源、進行傅立葉頻域轉換得到 吸收光譜分布；低雜訊電流放大器：進行電壓設定、訊號感測度與增益放 # 大）' 偵檢度校正（如：黑體輻射源··校正FTIR光源'強度；鎖相放大器： 同步調.變光電流轉制電壓訊號擷取），經過以上光電物理參數量測與驗證 後，右能符合所訂之感測元件規格，如：訊號雜訊比、光響應波段、響應 度、偵檢度、暗電流、暗微分電阻，同片感測磊晶片其餘3/4〜4/5晶片面積 • 則使用陣列型光罩。 • 之後，直接進行焦平面陣列製程，以每單位偵檢單元均勻度線寬誤差 <10% ;光譜響應中總光電流均勻度>75%，而製作流程使用原單乙型參數為 主進行陣列製作，最後加上元件測試區進行暗電流均勻度測試13，若為利 用低能隙感測材料所製作之感測陣列，如銻化銦、汞鎘銻，必須在感測陣 ® 列表面以電漿、紫外光輔助汽相沉積、或加熱真空沉積等方式成長如：氧 化石夕或氮化矽等鈍化膜（passivation layer)(厚度介於50〜300nm之間）， 或以旋轉塗佈方式披覆聚合物層（厚度介於0.5〜3/zm之間）於陣列層上， 主要目的是防止表面受外界水氣或污染物滲透，造成表面雜質能階增加形 成側向暗電流，而影響感測品質。 請一併參閱第二圖（b)，其為本發明之架構圖。由圖示可知，隨之， 上、下金屬電極端上成長銦柱118 (高度介於3〜12μιη，底部面積小於金屬 電極區），利用壓應力與平板加溫方式（溫度介於90〜2〇〇。〇），達到銦柱 近熔點瞬間時，與訊號讀出積體電路進行銦貼合（Indium bonding)，接 11 136.0881 η咖浦现 製程（如：Pdyffler聚合物質），而完成完整焦平面陣列與 訊號讀出積體電路架構4财，-組表示_畫數内的焦平面 妹 轉換，其架構為每個畫素單元對應一組可為緩衝、直接注入、 電容轉阻放大式注人娜訊·分單元。因此，希魏增加_焦平 列感測元件架構與訊號讀出積體電路模組間支财，並適度釋放卿 成之切應力累積之目的。 ^ =積體電路單-架構單^訊_碰電路主要魏為光電訊號擁取 閘極調變 在灌膠製程時，先將感測元件陣列與訊號讀出積體電路结入之焦平面 陣列模組間不需填膠部分以光阻保護’再置入聚合* (polymer)° “膠液 中，待氣泡不再從感測元件陣列與訊號讀出積體電路晶片交界處即可，夾 出後至入培養品中至防朝箱中陰乾，至少放置8〜12小時後再以有機溶液 如’丙_二氣曱烧，去除原固著於焦平面陣列模組晶片上之保護光阻與 殘存，劑。最後，請-併參閱第三圖，類似如單乙型感測晶片，先以導熱 膠固著於細或84腳晶#基座上。基座上的打線接腳連結方式對應於焦平 面陣列與訊號讀㈣體電㈣械哪換輸ώ訊額、電源訊號72、時脈 暨同步驅_人輸出1顧觀、_溫度檢_額與職二極體訊號 76 〇 參閱第四圖，其為本發明之方塊圖。由圖示可知，完成後，再進行置 入低溫真空致冷腔中502 ’先進行時序驅動程序51〇 ’目的是供給焦平面陣 列模組正常工作狀態，使輸出訊號維持正常工作模式，此時利用數位示波 器截取感測器緩衝板模組（Sensor Buffer Board) 524内的影像類比輸出 端，以確認其要求輸出訊號規格。之前，測試室溫下之焦平面陣列與訊號 5賣出積體電路接合阻值訊號畫面，目的初步了解接合狀況，再將溫度設定 於待驗證紅外線熱影像陣列模組之適當溫度操作範圍，此操作溫度介於絕 對凱氏溫賴.〖之間。當溫度在此妓溫度狱約至少15分鐘後，進行 調整外加模組操作偏壓512，而轉換至跨接在感測元件之偏壓絕對值5〇8介 於10mV至4V間；配合調整訊號讀出積體電路内積分時間使其介於1〇ysec至 12 1360881 32msec之間；訊號轉阻放大暨補償5〇4與緩衝增益5〇6功能端賴後級放大與 補偏電路而定，當以上重要調制參數均調為使得影像感測模組觀測單調中 段溫區背景下，原始影像訊號在顯示螢幕為灰階層次。 . 同時，以示波器繼續監測影像輸出端訊號，使其顯示出對溫度變化有 較大之動態值，此顯像處理系統電路板pr〇cessing办对挪）526 中，也設汁具有訊號類比/數位轉換5i4、訊號資料處理儲存與介面控制 516、可程式型時序内建518、可程式電源供應電路52〇，而主時序也可經由 VME bus傳輸鏈由電腦供給’整個控制指令與影像訊號輸出架構也可由怒232 介面，連、结主控電腦中控概理器522之Bit I/F介面卡作為指令（c〇nmand) •與1/0功能。然後再裝置紅外線光學鏡頭至感測模組前焦距處（F#介於 1.5〜3· 5) ’熱練整合職（含域祕）驗㈣進行湖參數微調，最 後進行低溫與咼溫區段兩點影像訊號線性補償，以校正其勳態影像均勻度。 請參网第五圖，其為本發明之立體圖。如圖所示，然而，影像調校程 ; 序完成後，便確認完成紅外線熱影像陣列模組製作中，焦面感測陣列之焦 平面陣列與訊號讀出積體電路模組是由感測模㈣面接光區_接收紅=卜 '線光訊號802 ’而訊號讀出積體電路讀取電路晶片808是以訊號讀出積體電 路上光電流輸入端806，藉由銦柱貼合方式與焦面感測陣列之焦平面陣列接 合’每陣列單兀内的光電流儲存至積分電容腦訊號藉由列⑽與行多工器 φ犯依序經訊號輸出端8M送至感測器緩衝板模組524與顯像處理系統電路 模組526内進行影像訊號處理等程序；低溫操作之焦平面陣列環境制冷器控 制溫度介於40〜150Κ±0· 5K，封農内部真空壓力介_E_5|2切汀之間， 經兩點均勻度影像品質補償後其影像晝面均句度>98%，FpA模組偵檢單元操 作率>95%，最後便完成一組熱影像模組離型。 ·’ 综上所述，本發明之紅外線熱影像陣列模組驗證架構與製造方法，其 包含有熱賴減格設與鱗雛，減進秘晶參數校正； 其在感敝段则短、巾、長紅外核蚊段；合雖，進行單乙型感測 元件製程與變溫光電量測驗證，以蟲晶完成感測元件以低溫變溫與變壓量 13 行=雷&驗，’g卩進行焦平面陣顺程及其光電均勻度驗證，進 驗證重目熱賴、贱格設計、蠢g與光學物性 愈磨簿㈣二。後’賴進行該辭面陣贿聽讀出㈣電路貼合 =z===r咖麵嫩舰合轉換 ^陣m程及其越均勻度驗證重新驗證。 與磨薄製程驗执重新陣列與訊號讀出積體電路貼合 合格後，繼續進行該熱影像陣列模組雛型，俜 ====_+’娜瓣獅離型。 專利法所規定之專利3=進f及可供產業利用者，應符合我國 早日賜准專利，^為禱無疑，菱依法提出發明專利申請，祈釣局 准以上所述者’僅為本㈣之—較佳實施躺已，並非 =實施之範圍，舉凡依本發明申請專利範圍所述之形狀、構造、特徵^ 神所為之均專變化與修飾，均應包括於本發明之申請專利範圍内。精 【圖式簡單說明】 第-圖為本發明之紅外線熱影像陣列模組之流程圖； 第二圖（a)為本發明之紅外線熱影像陣舰組之架構圖； 第二圖（b)為本發明之紅外線熱影像陣列模組之架構圖； 第三圖為本發明之紅外線熱職陣舰組之平面圖； 第四圖為本發明之紅外線熱影像_模組之方塊圖；及 第五圖為本㈣之紅祕鱗轉舰組之立體圖。 【主要元件符號言兒明】 10 熱像模組規格設計、磊晶與光學物性驗證 單乙型感測元件製程與變溫光電量測驗證 焦平面陣列製程及其光電均勻度驗證 焦平面陣列與訊號讀出積體電路貼合與磨薄製程驗證 影像整合測試（含光機系統）驗證 熱影像陣列模組雛型完成 模組紅外線穿透基板 底端高摻雜接觸層 紅外線吸收層 本質層 能障阻擋層 頂端高雜質摻雜接觸層 上電極區 感測元件表面絕緣彼覆層 銦柱 下電極區 輸出致能P-MOSFET電晶體 輸出與復置切換P-MOSFET電晶體 調整感測元件偏壓P-MOSFE：T電晶體 復置致能N-MOSFET電晶體 積分電容 選擇致能端點 偏壓注入端點 復置端點 負端端點 訊號輸出端 注入單元 15 1360881 414 行多工器 416 列多工器 418 行取樣保持與放大電路單元 420 時序生成單元 422 時序生成控制單元 424 線時序 426 主時序 428 行選擇埠 2110 行復置埠h 2111 列選擇埠 2112 列復置埠 2113 A通道輸出端 2114 B通道輸出端 70 通道輸出端點 72 偏壓與電源端點 74 時序端點 76 晶片溫度感測二極體輸出端點 78 測試感測輸出模組端點 502 低溫真空致冷腔 524, 感測器缓秦板模組 504 訊號轉阻放大與補償 506 緩衝增益功能 508 影像晶片模組時序與偏壓驅動模組 510 時序生成模組 512 偏壓建立模組 526 影像處理電路模組 514 類比數位轉換電路Vapor Depositor! 'PVD) (substrate temperature between 80 and 200 ° C), ion sputtering (usually using He, Ar ion blunt gas), or heating evaporation to grow yttrium oxide (Si〇x) or tantalum nitride (SiNx) 'As the surface coating layer H6 of the sensing element, the thickness is between 5〇~3〇〇nm, and then by Reactive Ion Etching (RIE) or wet etching (hydrogen fluoride: deionized water) , Buffer HF : DI water= 1~5:20) defines the semiconductor contact metal region, and the contact metal material used for the 114 and the lower 1〇1 electrode region on the sensing element is n-type. 11~20nm/chromium (Cr) 1~20nm/gold-iridium alloy (Au/Ge) 50~300nm/gold (Au) 50~300nm, P-type can be palladium (Pd) 1~20nm/chromium (Cr) Bu 20nm / gold bismuth alloy (Au / Be) or gram (Zn) 50 ~ 300nm / gold (Au) 50 ~ 300nm, can be used for thermal electrode plating, electronic rush heating vapor deposition or ion money for metal electrode production. The Rapid Thermal Annealing (RTA) process is an ohmic contact formed between a preferred semiconductor and a metal. The temperature and time of the heating are between 35 〇 and 5 〇 (rc, 15 to 60 sec, plus The temperature slope is 1〇〇~2〇(Tc/sec. If the sensing element area process is defined for the platform type (Mesa), in addition to using the mask development to define the etched area, the depth of the rice-cut area must exceed the thickness of the lower-end erbium-doped polarity area. Between 1/3 and 1/2, the rest of the process is the same in planar mode. In the process of quantum well sensing component architecture, the periodic grating structure must be added after the platform-based definition of the sensing component region process. 1D long strip or 2D square or diamond shape, grating spacing and height 1360881 < Between 1~5//πι and 10~500 coffee etching method and platform type sensing defined area processing method is the same β or more The main step of the single-B type sensing component process is to use this process parameter as a reference parameter for the subsequent focal plane array architecture. After completing the single-B type sensing component architecture, the thermal insulating adhesive is applied to the test insulating base. On the seat (such as: oxidized field platform base) 'pull out the gold signal line 5, put the loop 氦 氦 low temperature temperature vacuum chamber' and then the terminal pin signal line through the feed line (feedthr〇u绅) interface via coaxial The wire or the low noise signal line is derived, and the dark current, the dark resistance, and the response spectrum are measured by the low temperature and the variable voltage measurement (for example, the FTIR spectrum analyzer is used to input the light source, and the Fourier frequency domain conversion is performed to obtain the absorption spectrum distribution; Low noise current amplifier: voltage setting, signal sensing and gain release #大)' Detection degree correction (such as: blackbody radiation source · correction FTIR light source 'intensity; lock-in amplifier: synchronous adjustment. variable photocurrent conversion voltage After the above photoelectric optoelectronic parameters are measured and verified, the right can meet the specifications of the sensing components, such as: signal noise ratio, optical response band, responsivity, detection degree, dark current, dark differential Resistor, same chip sensing the remaining 3/4~4/5 wafer area of the epitaxial wafer • Use an array type reticle. • After that, the focal plane array process is directly performed, and the line width error of each unit of the detection unit is <10%; the total photocurrent uniformity in the spectral response is > 75%, and the production process uses the original single-type parameter as the main method. Array fabrication, and finally the component test area for dark current uniformity test 13. If a sensing array made of low energy gap sensing materials, such as indium telluride or mercury cadmium telluride, must be on the surface of the sensing array Plasma, UV-assisted vapor deposition, or vacuum deposition, such as: passivation layer (between 50 and 300 nm) such as oxidized stone or tantalum nitride, or spin coating The coating polymer layer (thickness between 0.5~3/zm) is on the array layer. The main purpose is to prevent the surface from being infiltrated by external moisture or contaminants, causing the surface impurity level to increase to form a lateral dark current. Sensing quality. Please refer to the second figure (b), which is an architectural diagram of the present invention. As can be seen from the figure, the indium pillars 118 are grown on the upper and lower metal electrode ends (the height is between 3 and 12 μm, and the bottom area is smaller than the metal electrode region), and the compressive stress and the flat plate heating method are used (the temperature is between 90 and 2). 〇〇.〇), when the indium column is near the melting point, the indium bonding is performed with the signal reading integrated circuit, and the process is completed by 11 136.0881 η, such as Pdyffler polymer, and the complete coke is completed. Planar array and signal readout integrated circuit architecture 4, - group represents the focal plane transform in the number of pictures, the structure is a set of each pixel unit can be buffered, directly injected, capacitive transimpedance amplification Person Naxun·sub-unit. Therefore, Xiwei increased the _ focus level sensing component structure and the signal reading integrated circuit module to support the money, and moderately released the purpose of the cutting stress accumulation. ^ = Integral circuit single-architecture single signal_combine circuit main Wei Wei photoelectric signal capture gate modulation In the glue filling process, firstly connect the sensing element array and the signal reading integrated circuit into the focal plane array The glue between the modules is not required to be protected by photoresist. 'Re-polymerization* (polymer) ° "In the glue, the bubbles are no longer read from the sensing element array and the signal reading integrated circuit chip junction. After the product is released into the culture medium and dried in the anti-proof box, it is placed for at least 8 to 12 hours, and then the organic solution, such as 'C-dioxide, is used to remove the protective photoresist that is fixed on the focal plane array module wafer. Finally, please - and refer to the third figure, similar to a single-type sensing wafer, first fixed with a thermal paste on the fine or 84-foot crystal # base. Corresponding to the focal plane array and signal reading (four) body electric (four) mechanical which exchanges the amount of signal, power signal 72, clock and synchronous drive _ human output 1 Gu Guan, _ temperature check _ fore and occupational diode signal 76 〇 The fourth figure is a block diagram of the present invention. It can be seen from the figure that after completion, the low temperature vacuum is placed. The purpose of the 502 'first timing driver 51〇' in the cold cavity is to supply the normal operation state of the focal plane array module, so that the output signal maintains the normal working mode. At this time, the sensor buffer board module is intercepted by the digital oscilloscope (Sensor Buffer Board) The image analog output terminal in 524 is used to confirm the required output signal specification. Before testing the focal plane array at room temperature and the signal 5 to sell the integrated circuit to block the resistance signal screen, the purpose is to understand the bonding condition and then the temperature. Set to the appropriate temperature operating range of the infrared thermal image array module to be verified, the operating temperature is between the absolute Kelvin temperature. Between. When the temperature is at this temperature, the prison is at least 15 minutes, adjust and add module operation. The bias voltage is 512, and the absolute value of the bias voltage connected to the sensing element is between 5mV and 4V; the integration time of the integrated circuit is read by the adjustment signal to be between 1〇ysec and 12 1360881 32msec. Between the signal transimpedance amplification and compensation 5〇4 and the buffer gain 5〇6 function depends on the post-amplification and complementing circuit, when the above important modulation parameters are adjusted to make the shadow In the background of the sensing module to observe the monotonic mid-range temperature zone, the original image signal is displayed as gray level in the display screen. At the same time, the oscilloscope continues to monitor the image output signal to show a large dynamic value for temperature changes. The development processing system circuit board pr〇cessing do not move 526, also has juice analog/digital conversion 5i4, signal data processing storage and interface control 516, programmable timing built-in 518, programmable power supply circuit 52〇, and the main timing can also be supplied by the computer via the VME bus transmission chain. The whole control command and video signal output architecture can also be interfaced by the anger interface. The Bit I/F interface card of the main control computer 522 is connected. As a command (c〇nmand) • with 1/0 function. Then install the infrared optical lens to the front focal length of the sensing module (F# between 1.5~3· 5) 'The hot integration integrated (including the domain secret) test (four) to fine-tune the lake parameters, and finally carry out the low temperature and temperature section The point image signal is linearly compensated to correct its uniform image uniformity. Please refer to the fifth figure, which is a perspective view of the present invention. As shown in the figure, however, after the sequence is completed, it is confirmed that the infrared thermal image array module is completed, and the focal plane array and the signal readout integrated circuit module of the focal plane sensing array are sensed. The mode (four) surface is connected to the light zone _ receiving red = 卜 'line optical signal 802' and the signal reading integrated circuit reading circuit chip 808 is used to read the photocurrent input terminal 806 on the integrated circuit by means of indium column bonding Engaged with the focal plane array of the focal plane sensing array. The photocurrent stored in each array is stored to the integrating capacitor. The brain signal is sent to the sensor buffer by the column (10) and the line multiplexer φ. The module module 524 and the image processing system circuit module 526 perform video signal processing and the like; the low temperature operation of the focal plane array environment refrigerator controls the temperature between 40 and 150 Κ ± 0 · 5K, and the internal vacuum pressure of the farmer _E_5 Between 2 dicing, after two-point uniformity image quality compensation, the image has a uniform face degree > 98%, FpA module detection unit operation rate > 95%, and finally completes a set of thermal imaging modules Release type. · In summary, the infrared thermal image array module verification architecture and manufacturing method of the present invention comprise a thermal reduction frame and a scale, and the reduction of the crystal parameters are corrected; Long-infrared nuclear mosquito section; although, the single-b-type sensing component process and variable-temperature photoelectric measurement verification are performed, and the sensing element is completed by the insect crystal at a low temperature and a variable pressure 13 rows = Ray & inspection, 'g卩The focal plane array and its photoelectric uniformity verification are carried out, and the verification is focused on the heat, the design, the stupid g and the optical property (4). After the 'Lai' the face of the face of the bribery read and read (four) circuit fit =z ===r coffee face tender ship conversion ^ array m process and its more uniformity verification re-verification. After the re-arrangement and the signal reading integrated circuit are matched with the thinning process, the thermal image array module prototype is continued, 俜 ====_+’. The patents stipulated by the Patent Law 3 = enter and f for industrial use, should be in line with China's early grant of patents, ^ for the pray, no doubt, Ling filed an invention patent application according to law, the praying bureau is more than the above mentioned 'only for this (four) The present invention is not limited to the scope of implementation, and all variations and modifications of the shapes, structures, and features described in the scope of the present invention should be included in the scope of the present invention. . [Simplified illustration of the drawing] The first figure is a flow chart of the infrared thermal image array module of the present invention; the second figure (a) is the structural diagram of the infrared thermal image array ship of the present invention; the second figure (b) The architecture diagram of the infrared thermal image array module of the present invention; the third diagram is a plan view of the infrared hot-ship array of the present invention; the fourth diagram is a block diagram of the infrared thermal image_module of the present invention; and the fifth The figure is a perspective view of the red secret scales of the (4). [Main components symbolic] 10 Thermal imaging module specification design, epitaxial and optical property verification Single-B type sensing component process and variable temperature photoelectric measurement verification Focal plane array process and its photoelectric uniformity verification focal plane array and signal Read integrated circuit bonding and thinning process verification image integration test (including optical system) verification thermal image array module prototype complete module infrared penetration substrate bottom high doping contact layer infrared absorption layer intrinsic layer energy barrier Barrier layer top high impurity doped contact layer upper electrode region sensing element surface insulation layer indium column lower electrode region output enable P-MOSFET transistor output and reset switching P-MOSFET transistor adjustment sensing element bias P -MOSFE: T transistor reset enable N-MOSFET transistor integral capacitor selection enable end bias injection endpoint reset terminal negative terminal signal output terminal injection unit 15 1360881 414 row multiplexer 416 column Worker 418 Row Sample Hold and Amplify Circuit Unit 420 Timing Generation Unit 422 Timing Generation Control Unit 424 Line Timing 426 Main Timing 428 Row Selection 埠 2110 Row Reset 埠h 2111 Column Selection 埠 2112 Column Reset 埠 2113 A Channel Output 2114 B Channel Output 70 Channel Output Endpoint 72 Bias and Power End 74 Timing End 76 Wafer Temperature Sensing Diode Output Endpoint 78 Test Sense Measurement output module end point 502 low temperature vacuum cooling chamber 524, sensor slow Qin plate module 504 signal resistance amplification and compensation 506 buffer gain function 508 image chip module timing and bias drive module 510 timing generation module 512 bias setting module 526 image processing circuit module 514 analog digital conversion circuit
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輸出影像資料訊號處理與控制電路 可程式時脈生成電路 可程式電源供應電路 控制處理器 紅外光訊號射入 感測模組背面接光區 訊號讀出積體電路上之光電流輸入端 訊號讀出積體電路之讀取電路晶片 列多工器 行多工器 訊號輸出端 17Output image data processing and control circuit programmable clock generation circuit programmable power supply circuit control processor infrared light signal injection sensing module back light receiving area signal reading integrated circuit on the optical current input signal reading Integrated circuit read circuit chip array multiplexer row multiplexer signal output terminal 17