1360870 . 九、發明說明： . 【發明所屬之技術領域】 本發明是有關一種晶片承載基板及其製造方法，特別是 一種具有通道之晶片承載基板及其製造方法。 【先前技術】 習知之晶片承載基板1 ’例如印刷電路板（Printed Circuit Board，PCB)，其主要結構如圖1所示，其是在基板u之上、 鲁 下表面以一黏著層12黏著一導電層13，並於導電層13上触 刻出預定之電路圖案。若有電路設計考量的需求，可形成貫 通基板11上、下表面的通孔14(through hole)，再以一導電 元件15(conductive component)使上、下表面之導電層13電 性連接。最後，以一阻銲層16(solder mask)覆蓋於基板Π之 上、下表面並曝露出部分導電層13或導電元件15以定義出 銲點17卜172。 以圖1所示舉例說明，依據上述結構，晶片2即可設置 於基板11之上表面，而以銲球21或其它方式（例如打線）使 ® 晶片2與晶片承載基板1之銲點171電性連接。晶片承載基 • 板1之銲點I72則可與外部電性連接或與其它晶片電性連接。 習知晶片承載基板1之通孔14皆近似垂直於基板n之 表面，且其作用主要在於使上、下表面之導電層13電性連 接。習知晶片承載基板1之通孔14鮮少作為傳遞電性以外物 理量之通道，例如傳遞聲音或液態或氣體檢體等。若以習知 ' 之通孔14作為上述物理量之傳遞通道，則通道之兩端開孔必 •須設置在晶片於晶片承載基板丨之投影區域内，否則必須另 以其它手段將上述物理量導引至晶片，如此不僅限制了設計 5 彈性，亦增加複雜度。此外，如何維持通道的寬度一致亦是 一大難題。 綜上所述，如何於晶片承載基板中設置橫向的通道，並 維持相對一致的通道寬度便是目前極需努力的目標。 【發明内容】 針對上述問題，本發明目的之一是提供一種具有通道之 晶片承載基板及其製造方法，其是於基板中設置阻隔物，使 在移除基板之部分區域時可形成橫向的通道，且維持預定的 通道寬度。 為了達到上述目的，本發明一實施例之具有通道之晶片 承載基板包含一基板、一阻隔物、一第一積層、一第一阻焊層 以及一第二積層。基板具有一第一表面以及一第二表面；阻隔 物則嵌設於基板中。第一積層設置於第一表面，且其具有導 電性並形成一第一電路。第一阻銲層覆蓋第一電路並曝露第一 電路之部分表面，以定義出一第一銲點。第二積層則設置於第二 表面。其中，阻隔物、第一積層以及第二積層所包圍之基板被移除以 定義出一通道。 為了達到上述目的，本發明另一實施例之具有通道之晶 片承載基板之製造方法，其步驟包含提供一基板，其具有一 第一表面以及一第二表面；嵌設一阻隔物於基板以形成一預 定圖案；分別形成一第一積層以及一第二積層於第一表面以 及第二表面，其中第一積層具有導電性；移除部分第一積層 以形成一第一電路；覆蓋一第一阻銲層於第一電路，並曝露 出第一電路之部分表面，以定義出一第一銲點；以及移除阻 隔物、第一積層以及第二積層所包圍之基板以形成一通道。 1360870 以下藉由具體實施例配合所附的圖式詳加說明，當更容 易瞭解本發明之目的、技術内容、特點及其所達成之功效。 【實施方式】 請參照® 2a至圖2h，說明本發明之一較佳實施例之具有通道 之晶片承載基板之製造方法。首先，提供一基板31，其具有 一第一表面311以及一第二表面312。基板31之材質可為金 屬材料或高分子聚合物。於此實施例中，基板31之材質以金 屬材料來作說明。接著，如圖2e所示’依據一預定圖案於基 板31中嵌設阻隔物32。預定圖案是用以定義出通道預定二 置316。依設計需求，預定圖案亦可定義出電性連接區3ΐ5， 其用以使後續形成於基板31第一表面311以及第二表面312 之電路可以彼此電性連接。 請參照圖2b至圖2e ’舉例說明於基板3】中丧設阻隔物32 的方法。如圖2b所示’依據前述之預定圖案，先於基板31 之第一表面311形成第一凹槽313。第一凹槽313之深度未 達第二表面312,亦即第一凹槽313之深度小於基板3ι :厚 度。如圖2c所示，於第一凹槽313令填入阻隔物仏接著， 相對於第-凹槽313形成-第二凹槽314，如圖2d所示亦 即於第二表面312形成第二凹槽314。第二凹槽314之深度 達到先剛在第-表面311所填人之阻隔物32，亦即第二凹样 314之深度大於等於基板31厚度與第一凹槽313深度之^ ，。最後’再於第二凹槽314中填人阻隔物32即形 2e所示結構。 Μ 請參照圖2f’接續說明本發明之具有通道之晶片承載基 ^之製造方法。丧設阻隔物32後，即分別在基板31之第一 表面311以及第二表面312形成第一積層33以及第二靜 7 :包Ϊ此:來，阻隔物32與第-積層33以及第二積層34 以及番^板31即為—封閉區域，例如通道預定位置316 層，連接區315。於此實施例令，第一積層33是由導電 33i ^黏著層332所組成，其中黏著層332用以使導電層 使導/於第—表面3U。此外’黏著層332具有絕緣性質， 功電層Ml與金屬材質之基板31彼此絕緣，因此黏著層 成所:視為—絕緣層。導電層311則可經由後續製程處理形 钱續上述說明，依設計的需求，第二積層34亦可具有 電性’亦即第二積層34是由導電層341與黏著層342所組 、’其主要作用如第一積層33所述，在此不再贅述。然而， 需注意者，第二積層34亦可不具備導電性質，而僅作為與 —積層33包夾基板31之用。 ^ 請參照圖2g，利用習知形成電路之方法分別於導電層331、34ι 形成所需之第一電路以及第二電路。第一電路以及第二電路上可再分 別以第一阻銲層351以及第二阻銲層352加以覆蓋，使部分電路曝^ 出來以定義出第一銲點361以及第二銲點362，舉例而言，第一銲點 361用以與晶片電性連接，而第二銲點362則與外部電性連接，或是 與其它晶片電性連接。 請再參照圖2g，習知技術中，大多是以通孔的方式，以一導電 元件15將基板第一表面與第二表面之電路電性連接(如圖}所示)。於 此實施例令，導電層331則是以導電元件15與基板31之電性連接區 315電性連接，電性連接區315再以另一導電元件15與導電層341 電性連接，如此，第一表面311之導電層331與第二表面312之導電 層341即可彼此電性連接。 請參照圖2h’最後，以適當方法移除通道預定位置316之基 板材料’即可形成通道37。舉例而言’可以藥劑選擇性地溶解基 1360870 板材料，而對於阻隔物32卻不會有溶解制，或是溶 微。如圖2h所示，本發明之晶片承载基板3之通道^目其 橫向的性質，糾與基板31之表面近乎平行，如此可〜1 片承載基板3之設計彈性。1360870. TECHNOLOGICAL FIELD OF THE INVENTION The present invention relates to a wafer carrier substrate and a method of fabricating the same, and more particularly to a wafer carrier substrate having a channel and a method of fabricating the same. [Prior Art] A conventional wafer carrier substrate 1 ', such as a printed circuit board (PCB), whose main structure is as shown in FIG. 1 , is a bonding layer 12 on the lower surface of the substrate u. The conductive layer 13 is formed on the conductive layer 13 to form a predetermined circuit pattern. If there is a need for circuit design considerations, a through hole 14 is formed through the upper and lower surfaces of the substrate 11, and the conductive layer 13 of the upper and lower surfaces is electrically connected by a conductive component 15. Finally, a solder mask 16 is applied over the upper and lower surfaces of the substrate and a portion of the conductive layer 13 or conductive member 15 is exposed to define solder pads 17 172. As illustrated in FIG. 1, according to the above structure, the wafer 2 can be disposed on the upper surface of the substrate 11, and the solder joints 171 of the wafer 2 and the wafer carrier substrate 1 are electrically connected by solder balls 21 or other means (for example, wire bonding). Sexual connection. Wafer Carriers The solder joints I72 of the board 1 can be electrically connected to the outside or electrically connected to other wafers. The through holes 14 of the conventional wafer carrier substrate 1 are approximately perpendicular to the surface of the substrate n, and mainly function to electrically connect the conductive layers 13 of the upper and lower surfaces. It is known that the through hole 14 of the wafer carrier substrate 1 is rarely used as a passage for transferring physical quantities other than electrical properties, such as transmitting sound or liquid or gas samples. If the conventional through hole 14 is used as the transmission channel of the physical quantity, the opening at both ends of the channel must be disposed in the projection area of the wafer on the wafer carrier substrate, otherwise the physical quantity must be guided by other means. To the wafer, this not only limits the flexibility of the design 5, but also increases the complexity. In addition, how to maintain the uniform width of the channel is also a big problem. In summary, how to provide a lateral channel in the wafer carrier substrate and maintain a relatively uniform channel width is currently an urgent task. SUMMARY OF THE INVENTION In view of the above problems, one of the objects of the present invention is to provide a wafer carrier substrate having a channel and a manufacturing method thereof, wherein a barrier is disposed in the substrate to form a lateral channel when a portion of the substrate is removed. And maintain a predetermined channel width. In order to achieve the above object, a wafer carrier substrate having a channel according to an embodiment of the invention comprises a substrate, a barrier, a first laminate, a first solder resist layer and a second laminate. The substrate has a first surface and a second surface; the barrier is embedded in the substrate. The first laminate is disposed on the first surface and is electrically conductive and forms a first circuit. The first solder mask covers the first circuit and exposes a portion of the surface of the first circuit to define a first solder joint. The second laminate is disposed on the second surface. Wherein, the substrate surrounded by the barrier, the first laminate and the second laminate is removed to define a channel. In order to achieve the above object, a method for manufacturing a wafer carrier substrate having a channel according to another embodiment of the present invention includes the steps of providing a substrate having a first surface and a second surface; and forming a barrier on the substrate to form a predetermined pattern; respectively forming a first buildup layer and a second buildup layer on the first surface and the second surface, wherein the first buildup layer is electrically conductive; removing a portion of the first buildup layer to form a first circuit; covering a first resistance Soldering the layer to the first circuit and exposing a portion of the surface of the first circuit to define a first solder joint; and removing the spacer, the first buildup layer, and the substrate surrounded by the second buildup to form a via. BRIEF DESCRIPTION OF THE DRAWINGS The objects, technical features, features, and effects achieved by the present invention will become more apparent from the detailed description of the appended claims. [Embodiment] Referring to Figures 2a to 2h, a method of manufacturing a wafer carrier substrate having a channel according to a preferred embodiment of the present invention will be described. First, a substrate 31 having a first surface 311 and a second surface 312 is provided. The material of the substrate 31 may be a metal material or a high molecular polymer. In this embodiment, the material of the substrate 31 is described by a metal material. Next, as shown in Fig. 2e, a barrier 32 is embedded in the substrate 31 in accordance with a predetermined pattern. The predetermined pattern is used to define a predetermined channel 316. The predetermined pattern may also define an electrical connection region ΐ5 for electrically connecting the circuits formed on the first surface 311 and the second surface 312 of the substrate 31 to each other. Referring to Figures 2b to 2e', a method of damaging the barrier 32 in the substrate 3 will be exemplified. The first recess 313 is formed prior to the first surface 311 of the substrate 31 in accordance with the predetermined pattern as shown in Fig. 2b. The depth of the first groove 313 is less than the second surface 312, that is, the depth of the first groove 313 is smaller than the thickness of the substrate 3ι:. As shown in FIG. 2c, the first recess 313 is filled with the barrier, and then the second recess 314 is formed with respect to the first recess 313, as shown in FIG. 2d, that is, the second surface 312 is formed second. Groove 314. The depth of the second recess 314 reaches the barrier 32 which is first filled in the first surface 311, that is, the depth of the second recess 314 is greater than or equal to the thickness of the substrate 31 and the depth of the first recess 313. Finally, the second recess 314 is filled with the barrier 32, that is, the structure shown in the shape 2e. Μ Referring to Fig. 2f', the manufacturing method of the wafer carrier having the channel of the present invention will be described. After the barrier 32 is disposed, the first layer 33 and the second surface 312 are respectively formed on the first surface 311 and the second surface 312 of the substrate 31: the barrier 32 and the first layer 33 and the second layer The laminate 34 and the panel 31 are closed areas, such as a predetermined location 316 of the channel, and a connection zone 315. In this embodiment, the first build-up layer 33 is composed of a conductive layer 33i, wherein the adhesive layer 332 is used to cause the conductive layer to be guided to the first surface 3U. Further, the adhesive layer 332 has an insulating property, and the dielectric layer M1 and the metal substrate 31 are insulated from each other, so that the adhesive layer is formed as an insulating layer. The conductive layer 311 can be processed through subsequent processing. According to the design requirements, the second build-up layer 34 can also have electrical characteristics, that is, the second build-up layer 34 is composed of the conductive layer 341 and the adhesive layer 342. The main function is as described in the first laminate 33, and will not be described herein. However, it should be noted that the second build-up layer 34 may also have no conductive properties, and may only be used as a laminate 31 for sandwiching the substrate 31. Referring to FIG. 2g, a desired first circuit and a second circuit are formed on the conductive layers 331, 341, respectively, by a conventional method of forming a circuit. The first circuit and the second circuit are respectively covered by the first solder resist layer 351 and the second solder resist layer 352, so that part of the circuit is exposed to define the first solder joint 361 and the second solder joint 362. The first solder joint 361 is electrically connected to the wafer, and the second solder joint 362 is electrically connected to the external or electrically connected to other wafers. Referring to FIG. 2g again, in the prior art, the first surface of the substrate and the circuit of the second surface are electrically connected by a conductive element 15 in a through-hole manner (as shown in FIG. In this embodiment, the conductive layer 331 is electrically connected to the electrical connection region 315 of the substrate 31, and the electrical connection region 315 is electrically connected to the conductive layer 341 by another conductive component 15. The conductive layer 331 of the first surface 311 and the conductive layer 341 of the second surface 312 can be electrically connected to each other. Referring to Figure 2h', finally, the channel 37 is formed by removing the substrate material ' at the predetermined position 316 of the channel by a suitable method. For example, the agent can selectively dissolve the base 1360870 sheet material without dissolving or dissolving the barrier 32. As shown in Fig. 2h, the planarity of the channel of the wafer carrier substrate 3 of the present invention is corrected to be nearly parallel to the surface of the substrate 31, so that the design flexibility of the carrier substrate 3 can be made.
需注意者，前述嵌設阻隔物32之方法僅為舉例戈 本發明所屬技術領域之具有通常知識者亦可以其它方式力 實現。例如，將基板31黏著於一固定表面，再依預定以 除部分基板材料而貫通第一表面311以及第二表面了移 著填入阻隔物32，最後將基板31與固定表面分離即形成如 圖2e所示之結構。另可依預定圖案移除部分基板材料而貫通 第一表面311以及第二表面312，接著在黏著第—積層33、 第二積層34時，以黏著層332、342填入凹槽而形成阻隔物 32 ° 請參照圖3，說明本發明另一較佳實施例之具有通道之 晶片承載基板4。相較於圖2h所示之晶片承載基板3，其差 別在於晶片承載基板4之通道37’之開口設置於基板Μ之门 一表面。It should be noted that the foregoing method of embedding the barrier 32 is merely exemplary and can be implemented in other ways as well as those of ordinary skill in the art. For example, the substrate 31 is adhered to a fixed surface, and the first surface 311 and the second surface are separated by a predetermined portion to be filled with the barrier 32, and finally the substrate 31 is separated from the fixed surface to form a figure. The structure shown in 2e. Alternatively, a portion of the substrate material may be removed in a predetermined pattern to penetrate the first surface 311 and the second surface 312. Then, when the first laminate 33 and the second laminate 34 are adhered, the adhesive layer 332, 342 is filled into the recess to form a barrier. 32 ° Please refer to FIG. 3, which illustrates a wafer carrier substrate 4 having a channel according to another preferred embodiment of the present invention. In contrast to the wafer carrier substrate 3 shown in Fig. 2h, the difference is that the opening of the channel 37' of the wafer carrier substrate 4 is disposed on the surface of the gate of the substrate.
請參照圖4 ’說明本發明又一較佳實施例之具有通道之晶 片承載基板5。晶片承載基板5之基板材料為高分子聚合物， 因此，晶片承載基板5較不適合如晶片承載基板3利用電性 連接區315將基板31之第一電路與第二電路電性連接。為解 決此問題，可利用阻隔物32定義出通孔的預定位置，而在後 續製程中移除通孔預定位置的基板材料而形成通孔14。接著 再以導電元件15穿過通孔14而將第一電路與第二電路電性 連接。 需注意者’為了方便說明’前述實施例中第一積層33以及第二 積層34僅佈設單層電路。然而，本發明所屬技術領域中具有通常知 9 織者亦可採用多層結構的設計。如圖5所示，依據設計需求，晶 片承载基板6之第一積層33’可為多層結構，第一電路即可 由多層電路層疊而成。同理，第二積層亦可為多層結構，而 第二電路亦可由多層電路層疊而成。此外，具有通常知識者亦 可於第一銲點361作一金屬表面處理，使第一銲點表面形成 金屬層3 8，以改善第一銲點3 61之表面性質或增加導電性 等。同理，第二銲點362亦可作類似的金屬表面處理。 另需注意者’本發明之晶片承載基板亦可包含多層基 板，且可於每一層基板中以阻隔物定義出通道預定位置，最 後再形成通道。依設計需求，每一層基板中之通道可以相通 或不相通，如此可大大增加晶片承載基板的設計彈性。 、綜合上述，本發明之具有通道之晶片承載基板及其製造方 法’，利膝隔触設於基板中，以定義出通道預定位置。在移除通 道預定位置之基板材料後，即形雜隔難第__積 ”的橫向通道。由於可形成橫向之通道錄板中，/此增積力^ 曰曰片承載基板的設計彈性^外，由於阻隔物的阻擋，因此 可較為準確地移除通道預定位置之基板材料，故通道可維持 寬度’㈣箱物與第—赫贼第二積層所定義出 、上所述之實施例僅是為說明本發明之技術思想及 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之六 =實施，當不能以之限定本發明之專利範圍，即大凡； 發月所揭不之精珅所作之均等變化或修倚，仍應涵蓋 發明之專利範圍内。 在本 1360870 【圖式簡單說明】 圖1為一示意圖，顯示一習知之晶片承載基板。 圖2a至2h為一示意圖，顯示本發明一較佳實施例之具有通道之 晶片承載基板之製造方法。 圖3為一示意圖，顯示本發明另一較佳實施例之具有通道之晶片 承載基板。 圖4為一示意圖，顯示本發明又一較佳實施例之具有通道之晶片 承載基板。 圖5為一示意圖，顯示本發明再一較佳實施例之具有通道之晶片 承載基板。 【主要元件符號說明】 1 習知之晶片承載基板 11 基板 12 黏著層 13 導電層 14 通孔 15 導電元件 16 阻銲層 171 、 172 銲點 2 晶片 21 鲜球 3 本發明之晶片承載基板 11 1360870Referring to Fig. 4', a wafer carrier substrate 5 having a channel according to still another preferred embodiment of the present invention will be described. The substrate material of the wafer carrier substrate 5 is a high molecular polymer. Therefore, the wafer carrier substrate 5 is less suitable for electrically connecting the first circuit of the substrate 31 and the second circuit by the electrical connection region 315 as the wafer carrier substrate 3. To solve this problem, the predetermined position of the through hole may be defined by the barrier 32, and the through hole 14 may be formed by removing the substrate material at a predetermined position of the through hole in the subsequent process. Then, the first circuit and the second circuit are electrically connected by the conductive member 15 passing through the through hole 14. It is to be noted that the first laminate 33 and the second laminate 34 in the foregoing embodiment are provided with only a single layer circuit. However, it is also common in the art to which the present invention pertains to design a multilayer structure. As shown in Fig. 5, the first laminate 33' of the wafer carrier substrate 6 may have a multi-layer structure according to design requirements, and the first circuit may be laminated by a plurality of layers. Similarly, the second laminate may also be a multi-layer structure, and the second circuit may also be formed by laminating a plurality of layers. In addition, a person having ordinary knowledge can also perform a metal surface treatment on the first pad 361 to form a metal layer 38 on the surface of the first pad to improve the surface properties of the first pad 3 61 or to increase conductivity and the like. Similarly, the second solder joint 362 can also be treated with a similar metal surface. It is to be noted that the wafer carrier substrate of the present invention may further comprise a plurality of substrates, and a predetermined position of the channel may be defined by a barrier in each of the substrates, and finally a channel may be formed. According to the design requirements, the channels in each layer of the substrate can be connected or not, which can greatly increase the design flexibility of the wafer carrier substrate. In summary, the above-described wafer carrier substrate having a channel and a method of manufacturing the same are provided in the substrate to define a predetermined position of the channel. After the substrate material at the predetermined position of the channel is removed, the lateral channel of the __ product is difficult to form. Since the lateral channel can be formed in the recording plate, the increase of the force ^ the design elasticity of the carrier substrate is ^ In addition, due to the blocking of the barrier, the substrate material at the predetermined position of the channel can be removed more accurately, so that the channel can maintain the width of the (4) box and the second layer of the first squid defined by the embodiment described above. The purpose of the present invention is to explain the technical idea and the point of the present invention, and the purpose of the present invention is to enable the person skilled in the art to understand the invention of the present invention. Equivalent changes or modifications made by Jingjing should still cover the scope of the invention patent. In this 1360870 [Simplified illustration of the drawings] Fig. 1 is a schematic view showing a conventional wafer carrier substrate. Figs. 2a to 2h are schematic views. A method of fabricating a wafer carrier substrate having a channel in accordance with a preferred embodiment of the present invention is shown in Figure 3. Figure 3 is a schematic view of a wafer carrier substrate having a channel in accordance with another preferred embodiment of the present invention. 1 is a schematic view showing a wafer carrier substrate having a channel according to still another preferred embodiment of the present invention. FIG. 5 is a schematic view showing a wafer carrier substrate having a channel according to still another preferred embodiment of the present invention. Conventional wafer carrier substrate 11 substrate 12 adhesive layer 13 conductive layer 14 through hole 15 conductive member 16 solder resist layer 171, 172 solder joint 2 wafer 21 fresh ball 3 wafer carrier substrate 11 of the present invention 1360870
31 基板 311 第一表面 312 第二表面 313 第一凹槽 314 第二凹槽 315 電性連接區 316 通道預定位置 32 阻隔物 33、33， 第一積層 331 導電層 332 黏著層 34 第二積層 341 導電層 342 黏著層 351 第一阻銲層 352 第二阻銲層 361 第一銲點 362 第二銲點 37 、 37， 通道 38 金屬層 4 本發明之晶片承載基板 5 本發明之晶片承載基板 6 本發明之晶片承載基板 1231 substrate 311 first surface 312 second surface 313 first groove 314 second groove 315 electrical connection region 316 channel predetermined position 32 barrier 33, 33, first laminate 331 conductive layer 332 adhesive layer 34 second laminate 341 Conductive layer 342 Adhesive layer 351 First solder resist layer 352 Second solder resist layer 361 First solder joint 362 Second solder joint 37, 37, via 38 Metal layer 4 Wafer carrying substrate 5 of the present invention Wafer carrying substrate 6 of the present invention The wafer carrier substrate 12 of the present invention