1360332 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種用於超寬頻系統時間同步偵測電路之 類匹配濾波器。 【先前技術】 參考習知技術，如中華民國發明專利第i2568〇8號「封 包憤測」、中華民國發明專利第U88543號「封包偵測系 統、封包偵測裝置及處理接收封包的方法」及中華民國發 明專利公告第512609號「用於數位接收器之傳輸模式偵測 器」，其所使用的方法為利用匹配濾波器的架構，將接收 到的訊號與已知的訊號去計算相關性，計算相關性的作法 是以乘法計算。在實現上，乘法電路較加法電路複雜，雖 可得到精確時間同步點，但整體架構又過於複雜，且會比 用加法實現所禽硬體成本高。 超寬頻系統（ultra wideband system, UWB)是一種以封包 交換為系統架構之無線通訊系統，超寬頻封包偵測同步序 列（Packet Sync Sequence)，例如其具有128筆資料，依其 極性將這128筆資料分組，每8筆資料為一組，共可分成16 組，其中以每8筆資料為一組的資料具有{+、_、__、 、+、+、-、+}或{-、+、+、+、—、—、+、 一 }的特性，依照這個極性，我們可以將這丨6組看成為帶 有{+、+、+、+、_、_、+、+、_、_、+、 —、十、—、十、+ }符號的{+、一、一、—、+、+、 —、+ }，利用此特性，我們可將原本需要長度128的匹配 125064.doc -6- U60332 應波器’轉換成兩個長度分別為8與16的匹配遽波器。 參考圖1，其顯示習知超寬頻系統之時間同步偵測電路 之電路不意i。習知超寬頻系統之時間同步偵測電路1〇包 括第-匹配渡波器11 ' -第二匹配渡波器12及一比較器 其中該第一匹配濾波器11包括一第一暫存器111、一 第—碼暫存器112、複數個乘法器113、114、115及一第一 加法器116。該第二匹配濾波器12包括一第二暫存器丨21、 一第二碼暫存器122、複數個乘法器123、124、125及一第 二加法器126。 該第一匹配濾波器11及該第二匹配濾波器12用以將接收 進來的資料與預先已知而儲存在第一碼暫存器U2及第二 碼暫存器122的封包同步序列以複數個乘法器作相乘，再 將相乘所得到的數值以第一加法器n6及第二加法器126相 加，將第二加法器126相加後得到的值利用該比較器13比 較是否超過一門檻值（threshold)，若超過門檻值則表示封 包已偵測到》 在超寬頻的系統中剛好可以利用封包同步序列的極性特 性來簡化匹配濾波器的運算，於是將封包同步序列依其極 性所對應的位置預先給予+、一的符號後再相加來與門檻 值做比較。因其功效等同匹配濾波器，但在實現上是以加 法電路取代乘法電路，因為類似匹配濾波器的作用，故以 類匹配濾波器稱之。 參考圖2，其顯示習知類匹配濾波器之電路示意圖。習 知類匹配濾波器20包括八個暫存器21至28、四個第一層加 125064.doc 器37。其運算是36及一個第三層加法 、算疋先將在暫存器21至 器3】至34各別兩兩相加 之值以第一層加法 k 相加得到的值為第二層加法哭 35、36的輸入值，再 層加法器 層加法器37將總值計算出來=加，最後再透過第三 速傳輪… ⑷來。因為超寬轉WB)是屬於高 ·則母—個時脈週期必須計算共三層的加法 正固運算過程的最大延遲路徑發生在這三層加法器 上面，而無法達到所要求的速度。 因此，有必要提供一 統時間同步偵測電路之 【發明内容】 種創新且具進步性的用於超寬頻系 類匹配濾波器，以解決上述問題。 發月k供種用於超寬頻系統時間同步偵測電路之類 =配遽波器’包括：複數個暫存器、複數個第—層磨縮 器至夕一第一層壓縮器及一加法器。複數個暫存器用以 儲存超寬頻封包同步序列。複數個第一層壓縮器用以壓縮 該等暫存器内儲存之超寬頻封包同步序列，以產生第一層 進位及第一層和。第二層壓縮器用以壓縮第一層進位及第 層和’以產生第二層進位及第二層和。加法器用以加總 第二層進位及第二層和。 本發明之類匹配濾波器利用壓縮器去改善習知大量使用 的加法器之缺點，且壓縮器的複雜度遠比加法器簡單，在 相同的速度要求下可以較小的面積來實現，而在相同面積 大小下’則可以較短的時間來完成電路運算。 【實施方式】 125064.doc 1360332 參考圖3，其顯示本發明用於超寬㈣統時間同步摘測 ;t路第一實施例之類匹配遽波器之電路示意圖。本發明用 •於超寬頻系統時間同步偵測電路第一實施例之類匹配遽波 請包括：複數個暫存㈣純、複數個第—層壓縮器 5卜52、至少一第二層壓縮器53及—加法器⑷在本實施 例中，類匹配滤波器40包括八個暫存器似料用以儲存超 寬頻封包同步序列。 > 複數個第-層壓縮器51'52用以壓縮該等暫存器内儲存 之超寬頻封包同步序列，以產生第一層進位及第一層和。 在本實施例中，第一層壓縮器包括一第一壓縮器5ι及一第 一壓縮器52，用以分別壓縮四個暫存器内儲存之超寬頻封 包同步序列，以產生二個第一層進位及二個第一層和。例 如，該第一壓縮器51用以壓縮四個暫存器41至44内儲存之 超寬頻封包同步序列，並產生第一進位“及第一和si ;該 .第二壓縮器52用以壓縮四個暫存器45至48内儲存之超寬頻 封包同步序列，並產生第二進位c2及第二和S2。第一層進 位及第一層和包括第一進位cl、第一和si、第二進位d及 第一-和s2。 參考圖5,其顯示本發明壓縮器之電路示意圖。以第一 壓縮器51為例說明，該第一壓縮器51包括複數個全加器 511、512、513、514，用以計算得上述第一層進位及第一 層和。並且以4個長度為5位元（bit)的暫存器為例，透過壓 縮比為4: 2的第一壓縮器51去壓縮每一組的第n位元， η=0、1、2、3、4，在經過兩層的全加器（fa)5 11、5 12或 125064.doc •9- 1360332 513、5 14後就可以得到第η位元的和及其進位，所以每一 • 組壓縮器來看，其最大延遲路徑發生在兩層全加器上。 ‘ 再參考圆3，第一進位cl、第一和si、第二進位。及第 二和s2輸入至第二層壓縮器53,第二層壓縮器53用以壓縮 上述第一層進位及第一層和，以產生第二層進位c3及第二 層和S3。在本實施例中，僅有一個第二層壓縮器53，其係 為一第三壓缩器53。該第三壓縮器53包括複數個全加器， • 其電路與圖5之第一壓縮器51類似，在此不加敘述。因 此’第三壓縮器53最大延遲路徑亦發生在兩層全加器上。 該加法器54用以加總第二層進位c3及第二層和s3。參考 圖6，其顯示本發明加法器之電路示意圖。該加法器“係 為一連波進位加法器’包括複數個全加器541、542、 543、544、545，該等全加器串聯連接，用以計算第二層 進位及第二層和β由圖6可以看出該加法器54最大延遲路 徑發生在進位傳遞上，須要經過5層全加器的延遲才可以 獲得相加後的結果。 參考圖4 ’其顯不本發明用於超寬頻系統時間同步偵測 電路第二實施例之類匹配濾波器之電路示意圖。本發明第 一實施例之類匹配濾波器6〇與第一實施例之類匹配濾波器 - 5〇不同之處在於，本發明第二實施例之類匹配濾波器6〇另 包括複數個D型正反器61、62，設置於第二層壓縮器53與 該加法器54之間，用以管線化處理，可縮短整個電路的最 大延遲路徑。在本實施例中，類匹配滤波器6〇包括一第一 D型正反器61及一第二D型正反器以。 125064.doc 1360332 比較習知圖2之電路架構及圖3之電路架構，若習知類匹 配;慮波器2 0内之加法3 1至3 7係使用漣波進位加法器，則 習知類匹配慮波器20需使用39個（5x4 + 6x2 + 7)全加器；本 發明之類匹配濾波器40係利用壓縮器，本發明之類匹配滤 波器40需使用39個（5x2x2 + 6x2 + 7)全加器。但在最大延遲 路位上’ S知類匹配據波器2 0必須經過5 + 6 + 7 = 18個全加器 的延遲才可以得到相加後的最終結果；然而，本發明之類 匹配;慮波器40則只需要2+2 + 7=11個全加器的延遲就可以得 到相加後的最終結果’速度上約縮短了 38%的延遲時間。 因此’在相同面積大小上（39個全加器），本發明之類匹配 遽波器40可以較短的時間完成運算。 若於圖2之習知類匹配濾波器2〇中每層加法器間再加入D 型正反器，透過管線化來縮短整個電路的最大延遲路徑， 則此時最大延遲路徑發生在最終加法器上，約需7個全加 器但在面積大小上需使用39個全加器以及4個長度為讣^的 暫存器和2個長度為7 bit的暫存器。參考圖4,其最大延遲 路徑發生在加法器54上，約需7個全加器，但是使用的面 積為39個全加器以及2個長度為6bit的暫存器。由此可以看 出來在相同速度要求上，本發明圖4之電路架構可以較少 的面積，達到相同的速度要求。 惟上述實施例僅為說明本發明之原理及其功效，而非限 制本發明。因&，習於此技術之人士對上述實施例進行修 改及變化仍；ί：脫本發明之精神^本發明之權利範圍應如後 述之申請專利範圍所列》 125064.doc -11 - 1360332 【圖式簡單說明】 圖1係顯示習知超寬頻系統之時間同步領測電路之電路 示意圖； 圖2係顯示習知類匹配濾波器之電路示意圖； 圖3係顯示本發明用於超寬頻系統時間同步偵測電路第 一實施例之類匹配濾波器之電路示意圖； 圖4係顯示本發明用於超寬頻系統時間同步偵測電路第 二實施例之類匹配濾波器之電路示意圖； 圖5係顯示本發明壓縮器之電路示意圖；及 圖6係顯示本發明加法器之電路示意圖。 【主要元件符號說明】 10 習知時間同步偵測電路 11 第一匹配濾波器 12 第二匹配濾波器 13 比較器 20 習知類匹配濾波器 21 至 28 暫存器 31 至 34 第一層加法器 35、36 第二層加法器 37 第三層加法器 40 本發明第一實施例類匹配濾波器 41 至 48 暫存器 51 第一壓縮器 52 第二壓縮器 125064.doc 13603321360332 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a matched filter for a time synchronization detection circuit of an ultra-wideband system. [Prior Art] Refer to the prior art, such as the Republic of China invention patent No. i2568〇8 “Package Indignation”, the Republic of China Invention Patent No. U88543 “Packet Detection System, Packet Detection Device and Method of Handling Receiving Packets” and The Republic of China Invention Patent Bulletin No. 512609 "Transmission Mode Detector for Digital Receiver" uses a matched filter architecture to calculate the correlation between a received signal and a known signal. The method of calculating the correlation is calculated by multiplication. In terms of implementation, the multiplication circuit is more complicated than the addition circuit. Although the precise time synchronization point can be obtained, the overall architecture is too complicated, and the cost of the bird hardware is higher than that by the addition method. Ultra wideband system (UWB) is a wireless communication system with packet switching as the system architecture. The ultra-wideband packet detection synchronization sequence (Packet Sync Sequence), for example, has 128 data, according to its polarity, these 128 pens Data grouping, each group of 8 data is divided into 16 groups, of which the data of each group of 8 data has {+, _, __, , +, +, -, +} or {-, + According to this polarity, we can see these 6 groups as {+, +, +, +, _, _, +, +, _, {+, one, one, —, +, +, —, + } of the _, +, —, ten, —, ten, and + } symbols. With this feature, we can match the length of 128064.doc. -6- U60332 The filter is 'converted into two matching choppers with lengths of 8 and 16 respectively. Referring to Figure 1, the circuit of the time synchronization detecting circuit of the conventional ultra-wideband system is shown to be unintentional. The time synchronization detecting circuit 1 of the conventional ultra-wideband system includes a first-matching ferrier 11' - a second matching ferristor 12 and a comparator, wherein the first matched filter 11 includes a first register 111, a first The code register 112, the plurality of multipliers 113, 114, 115 and a first adder 116. The second matched filter 12 includes a second register 丨21, a second code register 122, a plurality of multipliers 123, 124, 125 and a second adder 126. The first matched filter 11 and the second matched filter 12 are configured to compare the received data with a packet synchronization sequence that is known in advance and stored in the first code register U2 and the second code register 122. The multipliers are multiplied, and the multiplied values are added by the first adder n6 and the second adder 126, and the values obtained by adding the second adders 126 are compared by the comparator 13 for comparison. A threshold, if the threshold is exceeded, the packet has been detected. In the ultra-wideband system, the polarity of the packet synchronization sequence can be used to simplify the operation of the matched filter, so the packet synchronization sequence depends on its polarity. The corresponding position is given a +, one sign in advance and then added to compare with the threshold value. Because the function is equivalent to the matched filter, but the implementation is to replace the multiplying circuit with a adding circuit. Because it is similar to the function of the matched filter, it is called a matched filter. Referring to Figure 2, there is shown a circuit diagram of a conventional class matched filter. The conventional class matched filter 20 includes eight registers 21 to 28, four first layers plus 125064.doc 37. The operation is 36 and a third layer addition, and the value obtained by adding the values of the first two additions k in the registers 21 to 3 to 34 is added to the second layer. The input values of 35, 36 are crying, and the adder layer adder 37 calculates the total value = plus, and finally passes through the third speed transfer wheel (4). Since the ultra-wide turn WB) is high, the mother-cycle cycle must calculate a total of three layers of addition. The maximum delay path of the positive-solid operation process occurs on the three-layer adder, and the required speed cannot be achieved. Therefore, it is necessary to provide a time-synchronous detection circuit. [Inventive content] An innovative and progressive use of an ultra-wideband-class matched filter to solve the above problem. The month of the month is used for the ultra-wideband system time synchronization detection circuit, etc. = the configuration of the chopper includes: a plurality of registers, a plurality of first-layer refractors, a first-layer compressor, and an addition Device. A plurality of registers are used to store the ultra-wideband packet synchronization sequence. A plurality of first layer compressors are used to compress the ultra-wideband packet synchronization sequence stored in the registers to generate a first layer carry and a first layer sum. A second layer of compressor is used to compress the first layer of carry and the first layer &' to produce a second layer carry and a second layer sum. The adder is used to add the second level carry and the second layer sum. The matched filter of the present invention utilizes a compressor to improve the disadvantages of the conventionally used adder, and the complexity of the compressor is much simpler than that of the adder, and can be realized with a small area under the same speed requirement. Under the same area size, it can take a short time to complete the circuit operation. [Embodiment] 125064.doc 1360332 Referring to FIG. 3, there is shown a circuit diagram of the present invention for ultra-wide (four) system time synchronization sampling; t-channel first embodiment matching chopper. The matching pulse for the first embodiment of the ultra-wideband system time synchronization detecting circuit includes: a plurality of temporary storage (four) pure, a plurality of first-layer compressors 5 52, at least a second layer compressor 53 and - Adder (4) In this embodiment, the class-matching filter 40 includes eight registers to store the ultra-wideband packet synchronization sequence. > A plurality of layer-layer compressors 51'52 are used to compress the ultra-wideband packet synchronization sequences stored in the registers to generate a first layer carry and a first layer sum. In this embodiment, the first layer compressor includes a first compressor 5ι and a first compressor 52 for respectively compressing the ultra-wideband packet synchronization sequences stored in the four registers to generate two first Layer carry and two first layers and. For example, the first compressor 51 is configured to compress the ultra-wideband packet synchronization sequence stored in the four registers 41 to 44, and generate a first carry "and a first sum si; the second compressor 52 is used to compress The ultra-wideband packet synchronization sequence stored in the four registers 45 to 48, and generates a second carry c2 and a second sum S2. The first layer carry and the first layer and include the first carry cl, the first and si, the first Binary d and first-and s2. Referring to Figure 5, there is shown a circuit diagram of the compressor of the present invention. The first compressor 51 is illustrated as an example, the first compressor 51 includes a plurality of full adders 511, 512, 513 and 514, which are used to calculate the first layer carry and the first layer sum, and take four temporary registers with a length of 5 bits as an example, and pass the first compressor with a compression ratio of 4:2. 51 decompresses the nth bit of each group, η = 0, 1, 2, 3, 4, after passing through two layers of full adders (fa) 5 11, 5 12 or 125064.doc • 9 - 1360332 513, After 5 14 , the sum of the nth bit and its carry can be obtained, so for each group of compressors, the maximum delay path occurs on the two-layer full adder. a circle 3, a first carry cl, a first sum si, a second carry, and a second sum s2 input to the second layer compressor 53, the second layer compressor 53 for compressing the first layer carry and the first layer and To generate the second layer carry c3 and the second layer and S3. In this embodiment, there is only one second layer compressor 53, which is a third compressor 53. The third compressor 53 includes a plurality of The full adder, • its circuit is similar to the first compressor 51 of Fig. 5, and will not be described here. Therefore, the 'third compressor 53 maximum delay path also occurs on the two-layer full adder. The adder 54 is used for Adding a second layer carry c3 and a second layer and s3. Referring to Figure 6, there is shown a circuit diagram of the adder of the present invention. The adder "is a continuous carry adder" includes a plurality of full adders 541, 542, 543, 544, 545, the full adders are connected in series for calculating the second layer carry and the second layer and β. As can be seen from Fig. 6, the maximum delay path of the adder 54 occurs on the carry transfer, which requires 5 layers. The delay of the full adder can be obtained after the addition. Referring to Fig. 4', a circuit diagram of a matched filter such as the second embodiment of the ultra-wideband system time synchronization detecting circuit is shown. The matched filter 6A of the first embodiment of the present invention is different from the matched filter of the first embodiment in that the matched filter 6 of the second embodiment of the present invention further includes a plurality of D-types. The flip-flops 61, 62 are disposed between the second layer compressor 53 and the adder 54 for pipeline processing, which can shorten the maximum delay path of the entire circuit. In this embodiment, the class-matching filter 6A includes a first D-type flip-flop 61 and a second D-type flip-flop. 125064.doc 1360332 Compare the circuit architecture of the conventional FIG. 2 with the circuit architecture of FIG. 3, if the conventional class matches; the addition of the filter 20 0 to the 3 3 to 37 uses the chopping carryer, the conventional class The matching filter 20 requires 39 (5x4 + 6x2 + 7) full adders; the matched filter 40 of the present invention utilizes a compressor, and the matched filter 40 of the present invention requires 39 (5x2x2 + 6x2 + 7) Full adder. However, on the maximum delay path, the S-class matching filter 20 must pass the delay of 5 + 6 + 7 = 18 full adders to obtain the final result after the addition; however, the matching of the present invention; The filter 40 only requires a delay of 2+2 + 7 = 11 full adders to obtain the final result of the addition, which is about 38% shorter in delay. Therefore, the matching chopper 40 of the present invention can perform the operation in a shorter time on the same area size (39 full adders). If a D-type flip-flop is added between each adder in the conventional matched filter 2 of FIG. 2, the maximum delay path of the entire circuit is shortened by pipeline, and then the maximum delay path occurs at the final adder. In the above, about 7 full adders are needed, but 39 full adders and 4 scratchpads of length 讣^ and 2 scratchpads of 7 bits length are used in the area size. Referring to Figure 4, the maximum delay path occurs on adder 54, which requires about seven full adders, but uses an area of 39 full adders and two 6-bit registers. It can be seen that the circuit architecture of Figure 4 of the present invention can achieve the same speed requirement in terms of the same speed requirement. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments are made by those skilled in the art; ί: the spirit of the present invention. The scope of the present invention should be as set forth in the scope of the patent application hereinafter. 125064.doc -11 - 1360332 BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a time synchronization pilot circuit of a conventional ultra-wideband system; FIG. 2 is a circuit diagram showing a conventional class matched filter; FIG. 3 is a diagram showing the time synchronization of the ultra-wideband system according to the present invention. FIG. 4 is a circuit diagram showing a matched filter of a second embodiment of the ultra-wideband system time synchronization detecting circuit of the present invention; FIG. 5 is a circuit diagram showing the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 is a circuit diagram showing an adder of the present invention. [Main component symbol description] 10 conventional time synchronization detecting circuit 11 first matched filter 12 second matched filter 13 comparator 20 conventional class matched filter 21 to 28 registers 31 to 34 first layer adder 35, 36 second layer adder 37 third layer adder 40 First embodiment of the present invention matched filter 41 to 48 register 51 first compressor 52 second compressor 125064.doc 1360332
53 第二壓縮器 54 加法器 60 本發明第二實施例之類 61 第一D型正反器 62 第二D型正反器 111 第一暫存器 112 第一碼暫存器 113、 114、115 乘法器 116 第一加法器 121 第二暫存器 122 第二碼暫存器 123、 124 ' 125 乘法器 126 第二加法器 541至545 漣波進位加法器53 second compressor 54 adder 60 second embodiment of the invention 61 first D-type flip-flop 62 second D-type flip-flop 111 first register 112 first code register 113, 114, 115 multiplier 116 first adder 121 second register 122 second code register 123, 124 '125 multiplier 126 second adder 541 to 545 chopping carry adder
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