13575311357531
嚴重。同樣地，第二祕驅動H 20產生的第二閘極訊號的波形— 開始為—個方波的形狀，但因為線路負載的關係，使得第二閉極 訊號的波形隨著線路距離漸漸產生形變(如第丨圖中的第二間極線 21下方所示的波形），由於越接近第二閘極訊號線21末端的負載 會越大，因此第二閘極訊號波形失真的情形越嚴重。 、 上述波形失真的現象將導致相同的充電電位下，第一閘極線 11與第—閘極線η上末端的晝素電位較前端的晝素電位為高， 造成相鄰的兩健素具有不_亮度，此現象在第—閘極線叫 第二閛極線21末端位置的晝素特別明顯。 、 、、因此’如何能提供-種亮度均勻的閘極驅動式液晶顯示器， 成為研究人員待解決的問題之一。 【發明内容】 馨於以上的問題，本發明提供__制極驅動式液晶顯示哭， 薄膜電晶體之寄生電容值的方式，以補償間極訊號:形 造成的畫素電位差異，藉以提驗晶顯示器_示品質。 本發騎揭露之閘極购式液晶顯示器包含有：第一間極驅 ;:閘= 訊號;複數條第-閉極線，傳輸第 數條苐二閘極二動器’產生第二_動訊㈣ 極规動訊號；源極驅U產—===用以傳輸第二間 交又於隸笛產生一源極鷄虎；複數條資料線， 域，各資料線=極線與各個第二閘極線而定義出複數個畫素區 極分別盥複數体=傳輸源極驅動訊號’·複數個薄膜電晶體，其間 、硬數條第一間極線或複數條第二開極線電性連接；以及 31左側的相電晶體40，以控制薄膜電晶體4G的導通時間。 複數條第—閘極線11係與第-閘極驅動器10電性連接，用 、傳輸第㈤極驅動器1G產生的第—閘極驅動訊號至 左侧的薄膜電晶體4〇。 ' 第-閘極驅動器2G係用以產生第二閘極驅動訊號至資料線 31右側的'麵電晶體40，以控制薄膜電晶體40的導通時間。 複數條第二閣極'線21係與第二閘極驅動器20電性連接，第 -閘極線21並與第—閘極線u交錯配置，用以傳輸第二間 動訊號至資料線31右側的薄膜電晶體4〇。 〃 源極驅動态30係用以產生源極驅動訊號至薄膜電晶體4〇。 複數條資料線31係與源極驅動器30電性連接，而資料線31 交叉於各個第—_線11與轉第二閘極線21而定義出複數個 晝素區域’各個複數條資料線31用以傳輸源極驅動訊號。 複數個薄膜電晶體40之各閘極係依據薄膜電晶體40的位置 分別與複數條第—閘極線11或複數條第二閘極線21電性連接。 每個薄膜電晶體4〇係設置於每一條第一閘極線丨丨或每—條第 一間極線21與資料線31之交叉處。每兩相鄰的賴電晶體4〇之 源極係共同電性連接至同—條㈣線31上。 *複數個補償電容5G係形成於第—閘極㈣或第二閘極線^ 與薄膜電晶體4G之汲極之導線的重叠區域，用以補償各個畫素區 j間的電位差異。各個晝素區域之㈣合加她⑽幽電壓正比於補 知電合5G之電容值，且補償電容如的電容值正比於重疊區域的 面積，換。之’重疊區域的面積越大，卿償電容5㈣電容值越 1357531 第7圖為本發明晝素結構之剖面示意圖。如第7圖所示，晝 素結構600包含有基板200、閘極線43a、資料線31及薄膜電晶 體40。 閘極線43a係設置於基板200上並朝第一方向(例如，X轴方 向)延伸，用以傳輸閘極訊號。 資料線31係設置於基板2〇〇上，用以傳輸源極訊號，資料綠 31與閘極線43共同定義出一晝素區域。serious. Similarly, the waveform of the second gate signal generated by the second secret drive H 20 starts to be a square wave shape, but because of the line load relationship, the waveform of the second closed-pole signal gradually deforms with the line distance. (As shown in the waveform below the second polarity line 21 in the second diagram), the closer the load to the end of the second gate signal line 21 is, the more severe the distortion of the second gate signal waveform is. The phenomenon of waveform distortion described above will result in the same charge potential, the pixel potential of the upper end of the first gate line 11 and the first gate line η is higher than the terminal element potential of the front end, resulting in adjacent two health elements having Not 亮度 brightness, this phenomenon is particularly noticeable in the position where the first gate line is called the end of the second drain line 21. Therefore, how to provide a kind of gate-driven liquid crystal display with uniform brightness has become one of the problems to be solved by researchers. SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides a method of __electrode-driven liquid crystal display crying, the parasitic capacitance value of a thin film transistor, to compensate for the difference in pixel potential caused by the interpole signal: Crystal display _ shows quality. The gate-purchased liquid crystal display disclosed in the present disclosure includes: a first pole drive; a gate = a signal; a plurality of first-closed lines, and a transmission of the first two gates and two actuators to generate a second movement (4) Extremely motivated signal; source drive U--=== to transmit the second cross and to generate a source of chicken and tiger in the flute; multiple data lines, domains, data lines = polar lines and various The two gate lines define a plurality of pixel regions, respectively, a complex number body = a transmission source driving signal '· a plurality of thin film transistors, a first plurality of thin lines or a plurality of second open lines The phase connection; and the phase transistor 40 on the left side of 31 to control the on-time of the thin film transistor 4G. The plurality of first gate lines 11 are electrically connected to the first gate driver 10, and the first gate driving signals generated by the (5th) driver 1G are transmitted to the thin film transistors 4 on the left side. The first gate driver 2G is used to generate a second gate drive signal to the 'surface transistor 40' on the right side of the data line 31 to control the on-time of the thin film transistor 40. The plurality of second poles' line 21 are electrically connected to the second gate driver 20, and the first gate line 21 is alternately arranged with the first gate line u for transmitting the second motion signal to the data line 31. The thin film transistor on the right side is 4 turns. 〃 Source drive state 30 is used to generate the source drive signal to the thin film transistor 4〇. The plurality of data lines 31 are electrically connected to the source driver 30, and the data lines 31 intersect with the respective first-th line 11 and the second second gate line 21 to define a plurality of pixel regions 'each plurality of data lines 31 Used to transmit source drive signals. The gates of the plurality of thin film transistors 40 are electrically connected to the plurality of first gate lines 11 or the plurality of second gate lines 21 according to the positions of the thin film transistors 40, respectively. Each of the thin film transistors 4 is disposed at the intersection of each of the first gate lines or each of the first line lines 21 and the data lines 31. The source lines of each of the two adjacent Lai transistors are electrically connected to the same line (four) line 31. * A plurality of compensation capacitors 5G are formed in an overlapping region of the first gate (four) or the second gate line and the drain of the thin film transistor 4G to compensate for the potential difference between the respective pixel regions j. The (4) plus voltage of each of the elementary regions is proportional to the capacitance value of the complementary 5G, and the capacitance of the compensation capacitor is proportional to the area of the overlap region. The larger the area of the overlap region, the higher the capacitance of the capacitor (5) is. 1357531. Fig. 7 is a schematic cross-sectional view showing the structure of the pixel of the present invention. As shown in Fig. 7, the pixel structure 600 includes a substrate 200, a gate line 43a, a data line 31, and a thin film transistor 40. The gate line 43a is disposed on the substrate 200 and extends in a first direction (e.g., in the X-axis direction) for transmitting a gate signal. The data line 31 is disposed on the substrate 2 to transmit the source signal, and the data green 31 and the gate line 43 together define a halogen region.
薄膜電晶體40係設置於基板2〇〇上，其具有源極41、汲拯 42、閘極線43a、絕緣層80與半導體層9〇。絕緣層8〇係覆蓋於 閘極線43a上，半導體層9〇則設置於絕緣層8〇上。源極41電性 連接至資料線31。閘極線43a具有向第二方向(例如，γ軸方向） 延伸的突出部43b。 突出部43b與導線61a重疊的區域_一個平行板電容致 應，從㈣彡賴償電容5〇，且補償電容％的電容值正比於重叠 ，域的面積；換言之，重疊區域的面積越大，則補償電容5〇的^ 綜上所述，本發明所揭露的閘極驅動式液晶顯示器及晝素結 構係於各閘極線上根據訊號傳輸的距離形成具有败面_金: 層’使金屬層與晝素的導線構成—平行板電容效應，以補償 的兩個畫素關極訊號波形失真所產生的電位差異，進 以限定本 U兩個晝素亮度差異朗__，並提驗晶_器的顯矛目 雖然本發明已以較佳實施例揭露如上，然其並非用 13-57531 31 資料線 40 薄膜電晶體 41 源極 42 汲極 43 閘極 43a 閘極線 43b 突出部The thin film transistor 40 is provided on the substrate 2, and has a source 41, a buffer 42, a gate line 43a, an insulating layer 80, and a semiconductor layer 9A. The insulating layer 8 is covered on the gate line 43a, and the semiconductor layer 9 is placed on the insulating layer 8''. The source 41 is electrically connected to the data line 31. The gate line 43a has a protruding portion 43b that extends in the second direction (for example, the γ-axis direction). The area where the protruding portion 43b overlaps with the wire 61a is a parallel plate capacitance response, and the capacitance value of the compensation capacitance % is proportional to the overlap, the area of the domain; in other words, the larger the area of the overlap region, Then, the gate-driving liquid crystal display and the pixel structure disclosed in the present invention are formed on each gate line according to the distance of the signal transmission to form a failure surface _ gold: layer 'make metal layer With the wire composition of the halogen - parallel plate capacitance effect, to compensate for the potential difference caused by the distortion of the two pixel-off signal waveforms, to limit the brightness difference between the two elements of the U __, and to check the crystal _ Although the present invention has been disclosed in the preferred embodiment as above, it does not use 13-57531 31 data line 40 thin film transistor 41 source 42 drain 43 gate 43a gate line 43b protrusion
50 補償電容 51 第一補償電容 52 第二補償電容 60 晝素區域 61 晝素電極 61a 導線 61b 導線 70 金屬圖案區50 compensation capacitor 51 first compensation capacitor 52 second compensation capacitor 60 halogen region 61 halogen electrode 61a wire 61b wire 70 metal pattern area
71 第一金屬圖案區 72 第二金屬圖案區 80 絕緣層 90 半導體層 100 閘極驅動器 110 閘極線 200 基板 300 晝素陣列 1357531 400 500 液晶顯不 晝素陣列 晝素結構 60071 First metal pattern area 72 Second metal pattern area 80 Insulation layer 90 Semiconductor layer 100 Gate driver 110 Gate line 200 Substrate 300 Alizarin array 1357531 400 500 Liquid crystal display Cell array Alizarin structure 600