TWI357290B - Structure with embedded circuit and process thereo - Google Patents

Description

1357290 0611012 27083twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board process, and in particular to a process for a circuit board structure. [Prior Art] See: The circuit board technology has developed a buried circuit board (there is a Γwithembedded circuit with a buried line structure). In detail, the trace of the buried line from the dielectric surface is buried in the dielectric layer, and the non-extension process is shown in FIG. 1g. According to a conventional embedded circuit structure, the system does not. ^ Schematic diagram of the section. Please refer to FIG. 1A first. The conventional embedding includes the following steps. First, a substrate layer 110 is provided, and a carrier layer m and a carrier plate 112 are provided, wherein the carrier plate m is replaced by a barrier layer 1 and then the copper metal layer u4 is roughened to form a copper metal layer of the rough wheel surface S1. i 14. Thereafter, m is in which the photoresist layer 116 is entirely overlaid on the copper metal layer m. The photoresist layer 116 (four) is firmly attached = see FIG. 1 and FIG. 1C. Next, the photoresist layer 116 is exposed to a partial photoresist pattern layer 116, 'the photoresist pattern layer 116, the rough surface R1, and the photoresist pattern. 116' has an upper surface 1357290 0611012 27083twf, doc/p ll6a and a lower surface ll6b'. The upper surface H6a' is opposed to the lower surface 116b', and the lower surface 116b' is in contact with the copper metal layer 114. Since the photoresist pattern layer 116' is formed by exposure and development, the area of the upper surface U6a will be larger than that of the lower surface 116b. Referring to Figure 1E, the copper metal layer 114 is electrically keyed to form a copper circuit layer 12, wherein the copper circuit layer 12 has a plurality of beans.

The barrier layer 116 is exposed to expose a portion of the thickness. Referring to item 1F, the carrier plate 112 is then pressed onto a prepreg 130. Referring to FIG. 1F and FIG. 1G, the embedded wiring structure 100 in which the copper metal layer m and the carrier board ιΐ2 ^ are removed is completed. However, when the photoresist layer A β is ic), although the surface of the rough sugar is 8 = shadow (see Figure 1 and the metal layer 114, the photoresist layer 116 is firmly attached to the layer).

It is easy to control, and (4) the process parameters that cause the development of the stage are not unclean, thereby reducing the embedded performance and reducing the yield of the rough surface S1 flying circuit structure 100 by / month. SUMMARY OF THE INVENTION The present invention provides a yield of a buried 4-type line structure. The process of the work, the 'road structure, to improve the buriedness. The present invention provides a yield of a buried line structure. , and the structure of the road, the process of which can improve the internal burial - the present invention proposes a process for embedding the ten-machine, '' road structure, including the following steps 1357290 0611012 27083 twf.doc/p. First, a carrier substrate is provided. Next, a film layer covering the carrier substrate is formed. Thereafter, a laser beam is used to pattern the film layer to form a mask layer that partially exposes the carrier substrate. Next, a wiring layer is formed on the surface exposed by the mask layer. After the circuit layer is formed, the mask layer is removed. Next, an insulating layer is formed on the carrier substrate, wherein the wiring layer is buried in the insulating layer. Next, the carrier substrate is removed to expose a first table of the circuit layer

a face, wherein a second surface of the circuit layer is opposite the first surface, and an area of the first surface is smaller than an area of the second surface. In an embodiment of the present invention, the wiring layer has a side surface connected between the first surface and the second surface, and the insulating layer covers the second surface and the side surface.

In one embodiment of the invention, the first surface is tapered. In one embodiment of the invention, the carrier substrate is laminated to an insulating layer. In a layer of an embodiment of the invention. In one embodiment of the invention, a photoresist layer is disposed on the carrier substrate. The film layer is exposed in an embodiment of the invention. The method for forming the insulating layer from the second surface toward the above-mentioned circuit layer comprises the method that the insulating layer is a film or a resin. The method for forming the germanium layer comprises coating the patterned film layer, and further comprising: The carrier substrate includes a carrier layer and a conductive layer disposed on the carrier layer, and when the film layer covers each film layer, the mask layer is partially exposed to the conductive layer a field. 7 1357290 0611012 27083twf.d〇c/p The method for forming the circuit layer includes the method package of (4) mm addition and removal (4) and the present invention - the buried circuit structure, which comprises an insulation line, which is buried in the insulation layer, and the circuit layer has: The second surface opposite to the first surface and one connected to the flute-:: and S-side surface. The insulating layer covers the second surface and: the second table == is not covered by the insulating layer. The area of the first surface is irradiated by a small layer, and the first surface of the first surface and the insulating layer of the insulating layer can be buried in the mask layer of the laser t under the condition that the carrier substrate is not roughened. Line structure. Compared with the prior art, the present invention can eliminate the need for development, and the invention can make the surface of the board relatively clean, thereby improving the yield of the buried circuit structure. In order to make the above features and advantages of the present invention more comprehensible, the following description of the preferred embodiment and the accompanying drawings will be described in detail below. [Embodiment] FIG. 2A to FIG. 2G are schematic cross-sectional views showing a process of a buried circuit structure according to an embodiment of the present invention. Referring to Figure 2a, the process of the buried circuit structure of the present embodiment includes the following steps. First, a carrier substrate 210 is provided. In this embodiment, the carrier substrate 21A may include a !35729〇 0611012 27083 twf.doc/p-carrier 212 and a conductive layer 214, wherein the conductive layer 214 is disposed on the carrier 212. The material of the carrier substrate 210 and the conductive layer 214 may be metal. For example, the conductive layer 214 may be made of copper metal, and the carrier substrate 21 may be a plate. It must be noted that the carrier substrate 21A of the present invention includes various embodiments, and the carrier substrate 21A shown in Fig. 2A is only one of many embodiments. Therefore, it is emphasized herein that the carrier substrate and its carrier 212 and conductive layer 214 disclosed in Figures 2A-2G are for illustrative purposes only and are not limiting of the invention. Referring to FIG. 2B, a film layer 22 is formed which covers the carrier substrate 210, wherein the film layer 220 covers the conductive layer 214. The film layer 22 can be photosensitive. For example, the film layer 22G can be a photoresist layer, and the film layer can be formed by coating a photoresist layer on the carrier substrate (10). After the film layer 220 is formed, the film layer 22 () may be exposed to

The physical properties and chemical properties of the layer 220, thereby increasing the strength of the film layer 22q attached to the carrier substrate 210. Please refer to FIG. 2B and FIG. 2C, after the film is exposed, 20 L ” The ruthenium layer 220 is formed to form a mask layer 〇, partially exposing the surface of the carrier substrate 210 to perform a Lebes application. The above-mentioned laser beam may directly face the film layer 220 220 220 ^ the mask layer 220, having an upper surface 222a' and an opposite upper surface 1357290 0611012 27083twf.doc/p 230 may be from the second surface 23〇b as shown in Fig. 2D. The shape is tapered toward the first surface 230a, as shown in Fig. 2D and the figure, in forming the circuit layer After no, the mask layer 220 is removed. Since the mask layer 22' can be caused by the mask layer 22°, the method can be to use a stripping liquid; the entire layer is: the mask layer 220. The cover layer 22 is, and then the side of the circuit layer, the surface 230c and the surface of the carrier substrate 21 are exposed.

Referring to FIG. 2F' to subsequently form an insulating layer on the carrier substrate 210, wherein the wiring layer 230 is buried in the insulating layer 24A. In the present embodiment, the insulating layer 240 may be a film or a resin layer, and the insulating layer 24 may be formed by laminating the carrier substrate 21 to the insulating layer 24A. Since the film and the resin layer have fluidity, after the press-bonding substrate 21 is placed on the insulating layer 240, a plurality of gaps G existing between the wiring layers 230 may be filled by the insulating layer 240, that is, the insulating layer 240 is covered. The first surface 230b of the wiring layer 23〇 and the side surface 2.30c.

Referring to FIG. 2F and FIG. 2G, the carrier substrate 21A is removed to expose the first surface 230a of the wiring layer 230 and the surface 240a of the insulating layer 240. Since the material of the conductive layer 214 and the carrier 212 of the carrier substrate 210 can be metal, the method of removing the carrier substrate 210 may be to etch the carrier 212 and the conductive layer 214, wherein the etching may be wet etching. —. . . . -. After removing the carrier substrate 210, a buried wiring structure 200 including the wiring layer 230 and the insulating layer 240 has been substantially completed. In the 1357290 0611012 27083 twf.doc/p buried wiring structure 200, the insulating layer 24 covers the second surface 230b and the side surface 230c of the wiring layer 230, and the first surface 230a of the wiring layer 230 is not covered by the insulating layer 240. . In view of the above, since the area of the first surface 23〇a of the circuit layer 230 is smaller than the area of the second surface 230b, the traces 232 of the circuit layer 230 have a larger spacing from each other than in the prior art. p, and this can improve the electrical quality of the buried circuit structure. In addition, in the present embodiment, the wiring layer 230 may be tapered from the second surface 230b toward the first surface 230a, as shown in FIG. 2G, and the first surface 230a of the wiring layer 230 may substantially face the surface of the insulating layer 240. 240a is cut. It should be noted that the buried circuit structure 200 shown in FIG. 2G may be a single side circuit board, or the buried circuit structure 200 may be a double side circuit board. Or one of the circuit structures of the multi-layer circuit board, which is, for example, a surface line structure or an inner layer line structure. Therefore, the process of the buried wiring structure of the present invention can be applied to the process of a single layer circuit board, a double layer circuit board or a multilayer wiring board. In summary, the buried wiring structure of the present invention includes a wiring layer having a first surface not covered by the insulating layer and a second surface opposite to the first surface. Since the area of the first surface is smaller than the area of the second surface, the buried wiring structure of the present invention has a large spacing between the plurality of traces of the wiring layer as compared with the prior art. Thus, the present invention can improve the electrical quality of the buried wiring structure. Secondly, the present invention can be used to make a buried line gentleman's gift in the case where the carrier substrate is not thickly chained, and the field beam is used to carry the h_l. For example, + 士 = l and through the mask layer #进彳f (4) invention may not need to be above the above-mentioned technology, the invention can make the soil relatively clean, thereby improving the yield of the buried line structure. The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the application is determined by the definition of the attached occupation. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1G are schematic cross-sectional views showing a process of a buried circuit structure according to a conventional process. 2A to 2G are schematic cross-sectional views showing the process of the buried circuit structure according to an embodiment of the invention. [Description of main component symbols] 100, 200: buried wiring structure 110. Substrate 112: carrier plates 114, 114': steel metal layer 116: photoresist layer ^ 116': photoresist pattern layers 116a', 222a': Upper surface 13 1357290 0611012 27083twf.doc/p 116b, 222b': lower surface 120: copper wiring layer 122, 232: trace 130: film S1: raw sugar surface 210: carrier substrate 210a, 240a: surface 212: carrier plate® 214: conductive layer 220: film layer 220': mask layer 230: wiring layer 230a: first surface 230b: second surface 230c: side surface 240: insulating layer φ G gap P: pitch

Claims (1)

1357290 100-9-13 X. Application for Patent Park: L A light-weight structure provides a carrier substrate; 轾 includes: forming a film layer covering the carrier substrate; carrier = material - partial exposure of the carrier Less than the contact; the surface of the surface of the base substrate is formed - the wiring layer is exposed; the layer is exposed (4) the surface of the rail plate is formed after the circuit layer is formed, the mask layer is removed. On the substrate, the circuit layer is buried in the carrier substrate to expose the second layer of the circuit layer, and the surface of the second surface is smaller than the surface of the second surface. area. The method of the first embodiment of the invention, wherein the circuit layer has a side surface connected between the first surface and the structure J, The insulating layer covers the second surface of the fish 哕 一 一 一 Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ Λ 耘 耘 耘 耘 耘 耘 耘 耘 耘 耘 其中 耘 其中 其中 其中4. The internal type of wire loss as described in claim 1 is as follows: The method of forming the insulating layer includes pressing the carrier: Ξ 5. As in claim 1 The buried garment process is in which the insulating layer is a film or resin layer. ,,,,,, and oral S. 15 1357290 6. The buried wire process of claim 1, wherein the method of forming the film layer comprises applying a photoresist layer to the germanium substrate. The internal buried circuit structure process as described in the scope of the patent application, before the patterning of the film layer, further includes exposing the film layer. 8. The process of the buried circuit according to claim 1, wherein the carrier substrate comprises a carrier and a conductive layer disposed on the conductive layer, the film covering the conductive layer when the pattern The mask layer of the film layer partially exposes the conductive layer. The method of the process layer of the buried circuit structure described in the eighth aspect of the process includes the electroconductive layer. The process, in which the layer of the embedded buried circuit structure is described. The method of wearing the substrate includes the carrier and the conductive 5 16