TWI357017B - Systems and methods for synchronous code retrieval - Google Patents
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1357017 九、發明說明: 【發明所屬之技術領域】 本發明係關於用於能夠處理需求分頁瑪之碼遞送管理的 .系統’其獨立於一主機系統處理器與作業系統並且 '· 時。 …、 【先前技術】 記憶體管理系統在電腦工程之技術中為人熟知,其作為 構件用於藉由動態交換RAM之子區域與其他更大(但更慢) • 儲存記憶體來增強快速隨機存取記憶體(RAM)之效能,了吏 得該快速RAM始終可用於程式執行。藉由一記憶體管理單 " 元(MMU)來控制此類系統。 在先前技術中,一典型記憶體管理系統包括一主機處理 器(具有一内部或外部MMU)、非揮發性記憶體(nvm,其 係較大但較慢的記憶體)及R A M (其通常係用於碼執行的較 快較小的揮發性記憶體(VM))。 該MMU通常將該RAM中的區域映射至該nvm。該主機 •系統處理器以以下方式載入碼: ⑷在應用程式請求之後,當—應用程式有意嘗試載入並</ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; ..., [Prior Art] The memory management system is well known in the art of computer engineering as a component for enhancing fast random access by dynamically swapping sub-regions of RAM with other larger (but slower) storage memories. Taking the performance of the memory (RAM), the fast RAM is always available for program execution. Such a system is controlled by a memory management list "MMU. In the prior art, a typical memory management system includes a host processor (with an internal or external MMU), non-volatile memory (nvm, which is a larger but slower memory), and RAM (which is usually Faster and smaller volatile memory (VM) for code execution). The MMU typically maps the regions in the RAM to the nvm. The host • The system processor loads the code in the following way: (4) After the application requests, when the application intentionally tries to load and
運行恰巧儲存於該NVM中的另一應用程式(例如MSRun another application (such as MS) that happens to be stored in the NVM
Wind〇WsTM中的動態連結程式庫(或DLL))時; : (b)在尋頁錯失之後,當一無意"尋頁錯失"情況發生時,該 ·· MMU負責從該NVM載入該資料,並使用以下操作序列 來完成此項操作·· (1)碼快取:在可能時,該MMU將該現用碼保存於一 123608.doc 1357017 快取記憶體中,從而消除該主機系統處理器從一外 部資源(例如DRAM (dynamic RAM ;動態 RAM)/RAM或任一外部儲存裝置)讀取該碼的需 要,比減低交易之數目(從而減低功率消耗)並改良 - 處理器效能與輸出; ·· (11)將虛擬位址映射至實體位址,使用虛擬至實體轉換 表致能軟體程式實施需求分頁機制(如以下所說 明)’並通常藉由各種作業系統(例如Windows • Mobile、Symbian及 Linux)使用; (in)需求分頁機制係數個實施方案(藉由該MMU致能)之 一者,其使該虛擬記憶體空間等於或大於該實體記 憶體空間; (A) 當啟動一需求分頁機制並且該主機系統處理器 嘗試從該虛擬記憶體空間讀取内容(例如在碼執 行期間或藉由碼使用之資料)時,該MMU計算 請求的虛擬頁並在該内部快取記憶體中尋找該 •頁; (B) 若該頁不在該快取記憶體中,則該mmu在該虛 擬至實體表尋找在該碼或資料所位於的ram中 的實體位址; . (C)若該碼或資料未係映射至一 RAM實體位址(並因 : 此不能係擷取)’則一尋頁錯失發生;以及 (D)回應該尋頁錯失,該MMU將一異常中斷調用至 該主機系統處理n ’其係預期由該nvm提供該 123608.doc 1357017 遺漏頁 上述先前技術之 於複數個管理系統 變得難以處理。Wind〇WsTM dynamic link library (or DLL)); (b) After a page miss, when an unintentional "page missed" occurs, the MMU is responsible for loading from the NVM This data, and use the following sequence of operations to complete this operation · (1) code cache: When possible, the MMU saves the active code in a 123608.doc 1357017 cache memory, thereby eliminating the host system The need for the processor to read the code from an external resource (such as DRAM (dynamic RAM)/RAM or any external storage device) is less than reducing the number of transactions (thus reducing power consumption) and improving - processor performance and Output; (11) Map virtual addresses to physical addresses, use the virtual to entity conversion table to enable the software program to implement the demand paging mechanism (as explained below)' and usually through various operating systems (eg Windows • Mobile) (Symbian and Linux) use; (in) one of the requirements of the paging mechanism coefficient implementation (by the MMU enablement) that makes the virtual memory space equal to or greater than the physical memory space; (A) when booting One When the paging mechanism is sought and the host system processor attempts to read content from the virtual memory space (eg, during code execution or by code usage), the MMU computes the requested virtual page and is in the internal cache memory Looking for the page; (B) if the page is not in the cache memory, the mmu searches for the physical address in the ram where the code or data is located in the virtual to entity table; (C) if The code or data is not mapped to a RAM physical address (and because: this can not be retrieved) 'then a page miss occurs; and (D) should be page missed, the MMU will call an abnormal interrupt to the The host system processes n 'the system is expected to be provided by the nvm. The 123608.doc 1357017 missing page The above prior art to multiple management systems becomes difficult to handle.
方法的主要問題係該程序的複雜性。由 、驅動器及所涉及的協定所致此一程序 在先則技術中,Microsoft Windows CE(4.2或更高版本)支援雷虔八答 後而求刀頁。為支援該需求分頁機 制,開發者需要為該作業系統提供專用整合。在開發期 間’開發者需要安裝—檔案系統驅動器與一塊裝置驅動 器’並以-獨特方式(即不類似於不儲存碼用於需求分頁 的儲存記憶體所要求的杯—敕人、Α μ ^ 水的任整合)來格式化該儲存記憶 體。 需要一記憶體管理系#,# tfc ·χ+· i 理糸統其中該主機系統處理器從一位 4 δ月求^料並總是從該位晉择媒 ^ 4位置擭付該資料(直接或間接地)。 然而’該主機系統處理器要求同步地並在—極短的回應時 間(例如通常係4至5個時脈循環)内獲得該資料。因為某些 該等系統組件(例如該NVM)不能同步工作及/或不能在要求 的回應時間内提供咨粗 門扠供貝枓,故此一解決方式難以提供。此一 情形連同該主機车餘處搜^ /JU ^ 辦糸、,充處理器在一刼作期間不能外部中斷的 事實起係先月,』技術之麻煩方法似乎係唯一可能的解決方 式的原因。 需要提供„己憶體管理系統,其能夠同步地用於一主機 系統處理器對碼的需求,從而無論該碼係儲存於何處(即 該快取記憶體中、該RAM中或該NVM中)皆提供該碼。 【發明内容】 本發明之目的係提供用於能夠處理需求分頁碼之碼遞送 123608.doc 1357017 :理的系,统,其獨立於一主機系統處理器與作業且 無潛時。 為清楚起見’為本文之使用而特別定墓 幵⑺疋義以下數個術語。 本文中使用術語"程式計數器,,與"Pc”决 M。。 采表不一主機系統處 器中之一内部暫存器,其包括要藉由.The main problem with the method is the complexity of the program. This program is caused by the drive, the protocol involved, and the prior art, Microsoft Windows CE (4.2 or higher) supports the Thunder eight answer and then seeks the page. To support this demand paging mechanism, developers need to provide dedicated integration for this operating system. During development, 'developers need to install — file system drives and a device driver' and in a unique way (ie not similar to the cups required for storage memory that does not store code for demanding paging - 敕 Α, Α μ ^ water Any integration) to format the storage memory. Need a memory management system #,# tfc ·χ+· i 其中 其中 该 该 该 该 该 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机Directly or indirectly). However, the host system processor requires that the data be obtained synchronously and within a very short response time (e.g., typically 4 to 5 clock cycles). This solution is difficult to provide because some of these system components (e.g., the NVM) cannot operate synchronously and/or cannot provide a coarse-grained door for the required response time. In this case, together with the search for the rest of the host vehicle, the fact that the charging processor cannot be externally interrupted during the operation is the first month, and the technical troublesome method seems to be the only possible solution. There is a need to provide a memory management system that can be used synchronously with a host system processor for code requirements, regardless of where the code is stored (ie, in the cache, in the RAM, or in the NVM) The present invention provides the code. SUMMARY OF THE INVENTION The object of the present invention is to provide a code delivery 123608.doc 1357017 system capable of processing a demand page code, which is independent of a host system processor and job and has no latent For the sake of clarity, 'there are specific tombs for the use of this article. (7) The following terms are used. The term "program counter is used in this article, and "Pc" is used. . The internal memory of one of the host system devices is not included in the table.
稽田该主機系統處理器 執行的當前命令之…當該處理器完成命令執行時,藉 由該主機系統處理器來自動遞増該ρ 』以精由該主機系The current command executed by Ji Tian's host system processor... When the processor completes the command execution, the host system processor automatically recurs the ρ to optimize the host system.
統處理器使用特殊"分支"或"跳躍"命令來將該職定為任 一位址。 本文中使用術語"軟體中斷”盥"SWI"决志_ ^ I 一 a W1术表不一處理器命 令,其將該PC自動設定為一"重置向量"位址。在跳躍至該 重置向量位址之後,該主機系統處理器旋即開始執行位於 該位址的碼。本文中使用術語,,軟體中斷處置器,,來表示位 於該重置向量位址的碼並且其在軟體中斷執行之後旋即藉 由該主機系統處理器來執行。The processor uses a special "branch" or "jump" command to make the job a single address. In this article, the term "software interrupt" 盥 "SWI" decision_^ I a a W1 table is not a processor command, which automatically sets the PC to a "reset vector" address. After the reset vector address, the host system processor immediately begins executing the code at the address. The term, software interrupt handler, is used herein to denote the code at the reset vector address and it is After the software interrupt is executed, it is executed by the host system processor.
本文中使用術語”處理器快取記憶體"來表示一計算系統 中的记憶體之一部分,其具有最快的效能及通常一有限容 積。本文中使用術語"頁”來表示一給定系統中用於記憶體 管理的資料之最小單元(通常係2至4千位元組)。本文中使 用術語"片斷”來表示具有相同類型之使用(例如VM與NVM 中的載入或儲存方法)的一連續頁集。 本文中使用術語••碼"來表示可以藉由一處理器來執行的 一處理器命令集。本文中使用術語”駐存碼"來表示一旦載 入VM便保持駐存於該vm中的碼並且其在請求之後不需要 123608.doc 1357017 旋即從該NVM載入。駐存碼夕也/ 于%之執行不涉及潛時。 本文中使用術語"CPU月;# & 原子無作M來表示一 CPU(centralThe term "processor cache memory" is used herein to mean a portion of a memory in a computing system that has the fastest performance and typically a finite volume. The term "page" is used herein to mean a given The smallest unit (usually 2 to 4 kilobytes) of data used for memory management in a given system. The term "fragment" is used in this article to mean a contiguous set of pages of the same type of use (such as VM and NVM in the load or store method). The term "•code" is used in this article to mean that it can be handled by one. A processor command set to be executed by the device. The term "resident code" is used herein to mean that the code that resides in the vm is retained once the VM is loaded and that it does not need 123608.doc 1357017 immediately after the request. NVM loading. The resident code is also / the execution of % does not involve latent time. This article uses the term "CPU month; # & atom does not make M to represent a CPU (central
Proc — y中央處理單元)操作,其不能藉由任何事Proc — y central processing unit) operation, which cannot be done by anything
件來中斷(例如硬體或軟體中斷)並因而若開始則總會係完 成。本文中使用術語"碼冑送飼服器”與"CDS"來表示一硬 體控制器,其係藉由一主記_ p @ 1 匕隐體匯流排連接至一主機系統 處理器。該CDS係藉由一李铋 符田糸統6己憶體匯流排連接至該主系 統記憶體或嵌入主系統記憶體内邻 脰門。在該請求達到該主系 統記憶體之前,對該主系統記恃體 六说& +,μ ^ u粒之每一存取請求皆通過 該CDS。在本發明中,該CDS負責回應對—給定命令碼之 一 CPU請求來遞送以下命令碼 者.(a)來自主系統記憶 體之-命令碼,或(b)不同於該請求的命令碼之一則。 本文中使用術語,,碼段表"來表示保持於該主機系統處理 器令之一表,#中每一碼段皆係藉由一起始位址或段號與 該命令碼之長度來表示。 在本發明之一較佳具體實施例中,教導—記憶體管理系 統’其滿足對命令碼之同步CPU請求,從而由各種來源(某 些來源係非同步的)提供該碼。 在本發明之另-較佳具體實施例中,教導—記憶體管理 機構,其提供對任何碼讀取請求皆具有一同步回應的主機 系統處理器,無論該請求的碼在VM中是否可用。透過該 CDS來選路至倾之每一存取請求。在接收來自該主機系 統處理器之碼讀取請求之後’該CDS旋即將該等請求轉遞 至該主VM,接收來自該主VM之請求的資料並將該資料從 123608.doc • 10· 1357017 該VM遞送至該主機系統處理器。該主機系統處理器要求 要在數個時脈脈衝(通常係〇11八]^中的3至5個脈衝)内遞送 碼(即資料讀取請求)。若該碼已位於中,則此時框通常The device is interrupted (for example, hardware or software interrupt) and thus will always be completed if it is started. The term "code feed device" and "CDS" are used herein to refer to a hardware controller that is coupled to a host system processor by a master _p@1 匕 hidden bus. The CDS is connected to the main system memory or embedded in the main system memory by a Li Wei Futian system 6 memory bus. Before the request reaches the main system memory, the CDS Each access request of the system record & +, μ ^ u is passed through the CDS. In the present invention, the CDS is responsible for responding to the request - one of the command code CPU requests to deliver the following command code (a) the command code from the main system memory, or (b) one of the command codes different from the request. The term, the code segment table is used herein to mean that the processor is maintained in the host system. In a table, each code segment in # is represented by a start address or segment number and the length of the command code. In a preferred embodiment of the present invention, the teaching-memory management system 'satisfies Synchronous CPU requests for command codes, thus by various sources (some sources The code is provided in a non-synchronized manner. In another preferred embodiment of the present invention, a teaching-memory management mechanism is provided that provides a host system processor having a synchronous response to any code read request, regardless of the request Whether the code is available in the VM. The CDS is used to route to each access request. After receiving the code read request from the host system processor, the CDS will forward the request to the host. The VM receives the data from the request of the primary VM and delivers the data from the 123608.doc • 10· 1357017 the VM to the host system processor. The host system processor requires a number of clock pulses (usually 11 to 8) (3 to 5 pulses) within the delivery code (ie data read request). If the code is already in the middle, then the box is usually
係足夠的。然而,若該碼未係駐存於VM中並必須從NVM 載入則此時框對於該CDS自NVM擷取該碼係不足的。 在本發明之—較佳具體實施例巾,在請求的碼不能藉由 該CDS從VM按時遞送之情況下(由於該碼可儲存於或 八他k速儲存裝置),該〇1)8藉由向該主機系統處理器提供 :WI形式《替換碼"來避免潛時之情形。該主機系統處理 器續取並執行該SWI而非實際的碼。在執行該㈣之後, 該主機系統處理器旋即在―咖原子操作中停用硬體中 斷,儲存所㈣等CPU暫存n與狀態並跳躍至-重置向量 位址。 *該重置向量包括引起該主機系統處理器在一有限迴路(" 等待、路)t執仃程式碼的碼。當該主機系統處理器完成 °亥重置向里程式時,該主機系統處理器恢復該CPU暫存器 狀釔,致能該等硬體中斷並跳回至啟動該SWI之位址(全 部在一 CPU原子操作之時間内執行)。 ,若在該主機系統處理器在執行該重置向量程式時該CDS s理將該實際請求的碼從NVM載入至倾,則該C⑽ 再人提供SWI ’使得該主機系統處理器將如上所述再次 匕躍至該重置向量等待迴路程式^重複此等程序直至該 完成該請求的碼自NVM之祿取。當該CDS已完成該 際清未的碼之榻取時,該CDS等待下一次該主機系統處 123608.doc • 11 · (d) 該CDS識別引起該SWI之位址並計算要相應載入的 虛擬記憶體段號; (e) 該CDS接著將該計算的虛擬記憶體段號之資料從 NVM載入至該系、統主記憶體;以及 (f) 一旦將該資料栽入該系統主記憶體,該CDS便更新 該虛擬至實體表(即更新該"新載入號"之主記憶體實 體位址並將先前的頁標記為"遺漏·,)。 因此,依據本發明,第一次提供一電腦可讀取儲存媒 體’其具有執行於該電腦可讀取儲存媒體上的電腦可讀取 1¾ € Μ讀取碼包括:⑷程式碼,其用於回應來自一 機系、’先之主機系統處理器的對一命令碼之一 cpu請求 來遞送不同於該命令碼之一 SWI。 較佳的係,該SWI可操作以引起該主機系統處理器來再 次清求該命令碼。 較佳的係,該命令碼駐留於一 NVM中。 較佳的係,自一遠端來源擷取該命令碼。 較佳的係,將該程式碼嵌入該主機系統之一主v 件。 更佳的係,該電腦可讀取碼進一步包括:(1?)程式碼, 其用於在將該讀取請求之—虛擬位址轉換成—實體位址之 ,立即將每—讀取請求導向該主組件,不管該命令碼 是否係一存在碼段或一遺漏碼段之一部分。 τ’" 較佳的係,該電腦可讀取碼進一步包括:(b)程式碼, 其用於基於該命令碼之可用性在提供該命令碼與提供該 123608.doc 1357017 SW7之間進行選擇。 較佳的係,該電腦可讀取碼進一步包括·⑻程式媽, 用於辨別駐存碼;以及⑷程式碼,其用於避免在接收對 i駐存碼 < 存取請纟之後旋g卩針冑該駐存碼綠查 組件》 較佳的係,該電腦可讀取碼進一步包括:⑻程式碼, 二於依冑㈣命令碼表來區分—命令碼讀取請求與一 資料讀取請求,其中該命令碼讀取請求與該資㈣取請求 不同。 較佳的係’該電腦可讀取碼進—步包括:(b)程式碼, 其用於識別—請求的碼資料段是否在該主機系統之—主 VM組件中可用。 較佳的係’該電腦可讀取碼進一步包括:⑻程式碼, 其在該命令碼係一遺漏碼段之一部分時使用綱機器碼來 回應該主機系統處理器而不引起潛時。 較佳的係’該電腦可讀取碼進一步包括:(b)程式碼, 其用於提供對該CPU請求之一同步回應。 較佳的係、’該電腦可讀取碼進一步包括:⑻程式碼, 其用於將虛擬位址轉換成實體位址並用於將該等位址儲存 於一轉換表中;以及(c)程式碼,其用於命令碼管理。子 最佳的係,用於命令碼管理之程式碼可操作以依據藉由 該主機系統處理器傳送之一更新命令來更新該轉換表。 從以下詳細說明及範例將明白此等及其他具體實施例。 【實施方式】 123608.doc -15- 1357017 本發明係關於"能夠處理需求分頁碼之碼遞送管理的 系統,其獨立於一主機系統處理器與作業系統並且無潛 時。參考隨附說明與圖式可更佳地瞭解依據本發明的用於 月b夠處理需求分頁的碼遞送管理之原理及操作。It is enough. However, if the code is not resident in the VM and must be loaded from the NVM, then the box is insufficient for the CDS to retrieve the code from the NVM. In the preferred embodiment of the present invention, in the case where the requested code cannot be delivered from the VM on time by the CDS (since the code can be stored in the octave k-speed storage device), the 〇1)8 By avoiding the latent situation by providing the host system processor with the WI form "Replacement Code". The host system processor continues to fetch and execute the SWI instead of the actual code. After performing the (4), the host system processor immediately disables the hardware interrupt in the "cafe atom operation", stores the CPU (4), etc., and temporarily jumps to the state and jumps to the -reset vector address. * The reset vector includes a code that causes the host system processor to execute the code in a finite loop ("wait, road). When the host system processor completes the resetting to the mile mode, the host system processor restores the CPU register state, enabling the hardware interrupts and jumping back to the address of the SWI (all in the Executed within a CPU atomic operation time). If the CDS is loading the actual requested code from the NVM to the dump when the host system processor executes the reset vector program, the C(10) provides the SWI again so that the host system processor will Again, the reset vector wait loop program is repeated until the code that completes the request is taken from the NVM. When the CDS has completed the cancellation of the code, the CDS waits for the next time the host system is at 123608.doc • 11 (d) The CDS identifies the address of the SWI and calculates the corresponding load. a virtual memory segment number; (e) the CDS then loads the calculated virtual memory segment number data from the NVM to the system and the main memory; and (f) once the material is loaded into the system main memory Body, the CDS updates the virtual to entity table (ie, updates the "newload number" main memory entity address and marks the previous page as "missing·,). Therefore, in accordance with the present invention, for the first time, a computer readable storage medium is provided which has a computer readable reading on the computer readable storage medium. The reading code includes: (4) a code for Responding to one of the command codes from one machine, the first host system processor, a cpu request to deliver one of the SWIs different from the command code. Preferably, the SWI is operable to cause the host system processor to again request the command code. Preferably, the command code resides in an NVM. Preferably, the command code is retrieved from a remote source. Preferably, the code is embedded in one of the host system's main v pieces. More preferably, the computer readable code further comprises: (1?) code for converting the virtual address to the physical address of the read request, and immediately reading each read request Oriented to the main component, regardless of whether the command code is part of a code segment or a missing code segment. τ'" Preferably, the computer readable code further comprises: (b) a code for selecting between providing the command code and providing the 123608.doc 1357017 SW7 based on the availability of the command code. . Preferably, the computer readable code further comprises: (8) a program mother for identifying the resident code; and (4) a code for avoiding receiving the pair of resident code < accessing the user Preferably, the computer readable code further comprises: (8) a code, and a second (4) command code table to distinguish - a command code read request and a data read The request, wherein the command code read request is different from the request (4) fetch request. Preferably, the computer readable code step comprises: (b) a code for identifying whether the requested code data segment is available in the primary VM component of the host system. Preferably, the computer readable code further comprises: (8) a code that uses the machine code to respond to the host system processor without causing latency when the command code is missing a portion of the code segment. Preferably, the computer readable code further comprises: (b) a code for providing a synchronous response to one of the CPU requests. Preferably, the computer readable code further comprises: (8) a code for converting the virtual address into a physical address and storing the address in a conversion table; and (c) a program Code, which is used for command code management. The sub-optimal system, the code for command code management, is operable to update the conversion table in accordance with an update command transmitted by the host system processor. These and other specific embodiments will be apparent from the following detailed description and examples. [Embodiment] 123608.doc -15- 1357017 The present invention relates to a system capable of handling code delivery management of demand page numbers, which is independent of a host system processor and operating system and has no latency. The principles and operation of the code delivery management for the monthly processing of demand paging according to the present invention can be better understood with reference to the accompanying description and drawings.
現參考圖式,圖1顯示依據本發明之較佳具體實施例的 擷取程序之簡化流程圖。在接收來自該主機系統處理器的 讀取或寫入資科之-請求(步驟20)之後,該CDS針對以下 問題來檢查該請求(步驟22):Referring now to the drawings, Figure 1 shows a simplified flow diagram of a capture program in accordance with a preferred embodiment of the present invention. After receiving a request for reading or writing from the host system processor (step 20), the CDS checks the request for the following problem (step 22):
(1)該請求是否係一讀取請求? ⑺該資料是否屬於包括於該等"碼段"區域之一者中的一片 斷? (3)該片斷是否未位於心中(即,•資料遺漏")? 若步驟22中所有三個問題 门艰之答案皆係疋’則該CDS使用 該S WI來回應該主機备 Λ ^主機系統處理器(步驟24)。若步驟22中的 β等問題之-或多㈣題的答案係否’則該⑽將該存取(1) Is the request a read request? (7) Is the material a break in one of the "codes" areas? (3) Is the fragment not in the mind (ie, • Missing data ")? If all three of the problem answers in step 22 are answered, then the CDS uses the S WI to back up the host system processor (step 24). If the answer to the question such as β or the answer to the question (4) in step 22 is no, then (10) the access is
請求轉遞至該Μ統記憶體(步驟26)。關於步驟22中的前 兩個問題,應注意本發明Φ 赞月主要係關於磧取請求及碼,而非 資料。 具有將該PC值改變成一转 ^ 特疋位址值(例如,該重置向量 位址)之一處理器命令的 的填枓碼之一範例係碼:swi 0x1(具 有輸入參數1之一軟微tb齡、, 中斷)。在此範例中該處理器命令传 一 SWI。該軟體中斷處 尔 慝置器知道如何依據該輸入參數來處 理該SWI。當該主機备从走 冬处 系統處理器執行該SWI時,停 其他中斷’將所有暫存 用所有The request is forwarded to the memory (step 26). Regarding the first two questions in step 22, it should be noted that the present invention Φ is mainly about the retrieval request and the code, not the information. An example code of a fill code having one of the processor commands that changes the PC value to a value of the address (eg, the reset vector address): swi 0x1 (with one of the input parameters 1 soft) Micro tb age, interrupt). In this example the processor commands a SWI. The software interrupt handler knows how to process the SWI based on the input parameters. When the host is ready to perform the SWI from the winter system, the other interrupts are stopped.
子器自動儲存至一特定位置並將該PC 123608.doc -16- 1357017The sub-device is automatically stored to a specific location and the PC 123608.doc -16- 1357017
值改變成該重置向量。藉由調用該SWI來改變該PC,該PC 將所有暫存器儲存於一堆疊中並自動跳躍至該重置向量位 址。 以下顯示重置向量碼(即該軟體中斷處置器)之 其位於該重置向量位址並在停用所有其他中斷之後在接收 一 SWI之後旋即加以執行。 ⑴ push r4 ; (2) wait in loop 〇f 1000 ; (3) mov r4,#l〇〇〇 ; (4) LI subs r4, r4, #1 ; (5) nop ;(等待) (6) bne %B1 ; (5) end of loop; (6) (推送暫存器) (初始化r4(計數器)至looo) (標籤1 :遞減r4) (若r4#0,則跳躍至li) P〇P r4 : (彈出暫存器) (8) (9) (目前lr值係SWI+4(藉由SWI執行)) subs lr, lr, #4 ;(將lr值設定為該s WI位址) ret ; (跳回SWI位址) (致能中斷) 等系統處理器跳躍至該重置向量碼時,已停用該 後範圍"二已/存該主機系統處理器之暫存器(包括該"最 )暫存益,其在執行該重置向量碼完成之後旋 即具有針對該主機系統處理器之"跳回,·位址卜 該重置向量碼指示該主機系 環,而人人 叽蜒理器來迴路1000個循 而執仃一 nop命令(即"無操 Γ 7 )田該主機系統處 123608.doc 1357017The value changes to the reset vector. The PC is changed by invoking the SWI, which stores all the scratchpads in a stack and automatically jumps to the reset vector address. The following shows that the reset vector code (i.e., the software interrupt handler) is located at the reset vector address and is executed immediately after receiving a SWI after deactivating all other interrupts. (1) push r4 ; (2) wait in loop 〇f 1000 ; (3) mov r4, #l〇〇〇; (4) LI subs r4, r4, #1 ; (5) nop ; (wait) (6) bne %B1 ; (5) end of loop; (6) (push register) (initial r4 (counter) to looo) (label 1: decrement r4) (if r4#0, jump to li) P〇P r4 : (Eject register) (8) (9) (The current lr value is SWI+4 (executed by SWI)) subs lr, lr, #4; (set lr value to the s WI address) ret ; (jump back to the SWI address) (Enable interrupt) When the system processor jumps to the reset vector code, the post range is deactivated and the register of the host system processor is saved (including the " The most temporary storage benefit, which immediately has a "jumpback" for the host system processor after the completion of the reset vector code, and the reset vector code indicates the host system ring, and everyone is 叽The processor loops through 1000 loops and executes a nop command (ie, "no operation 7). The host system is at 123608.doc 1357017
理器完成執行該迴路時,將該LR暫存器設定為從其呼叫該 swi的位址。在該主機系統處理器係一 ARM處理器之情況 下’該ARM處理器在SWI執行之後旋即將該"SWI位址+4·, 保存於該LR暫存器中。為計算該SWI位址,該主機系統處 理器從該LR暫存器中之值減去四。當該主機系統處理器執 订該返回命令時’重新致能中斷恢復該等暫存器,該主 機系統處理器返回該SWI位址(全部在—epu原+ = 間内執行)。When the processor finishes executing the loop, the LR register is set to the address from which the swi is called. In the case where the host system processor is an ARM processor, the ARM processor saves the "SWI address +4· in the LR register after the SWI is executed. To calculate the SWI address, the host system processor subtracts four from the value in the LR register. When the host system processor executes the return command, the re-enable interrupt resumes the registers, and the host system processor returns the SWI address (all executed in the -epu original +=).
但應 儘s已針對有限數目的具體實施例來說明本發明 明白可對本發料行許多變更、似及其他應用。 【圖式簡單說明】 本文中已參考隨圖而僅以 m , - 』方式說明本發明,苴中, 化流程圖。 較佳具體實施例的掏取程序之簡However, the present invention has been described with respect to a limited number of specific embodiments. It is apparent that many variations, similar applications, and other applications can be made to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS In the present specification, the present invention has been described with reference to the accompanying drawings only in the form of m, -, and the flow chart is shown. A simple embodiment of the capture program
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