TWI357017B - Systems and methods for synchronous code retrieval - Google Patents

Description

</ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; ..., [Prior Art] The memory management system is well known in the art of computer engineering as a component for enhancing fast random access by dynamically swapping sub-regions of RAM with other larger (but slower) storage memories. Taking the performance of the memory (RAM), the fast RAM is always available for program execution. Such a system is controlled by a memory management list &quot;MMU. In the prior art, a typical memory management system includes a host processor (with an internal or external MMU), non-volatile memory (nvm, which is a larger but slower memory), and RAM (which is usually Faster and smaller volatile memory (VM) for code execution). The MMU typically maps the regions in the RAM to the nvm. The host • The system processor loads the code in the following way: (4) After the application requests, when the application intentionally tries to load and

Run another application (such as MS) that happens to be stored in the NVM

Wind〇WsTM dynamic link library (or DLL)); (b) After a page miss, when an unintentional &quot;page missed&quot; occurs, the MMU is responsible for loading from the NVM This data, and use the following sequence of operations to complete this operation · (1) code cache: When possible, the MMU saves the active code in a 123608.doc 1357017 cache memory, thereby eliminating the host system The need for the processor to read the code from an external resource (such as DRAM (dynamic RAM)/RAM or any external storage device) is less than reducing the number of transactions (thus reducing power consumption) and improving - processor performance and Output; (11) Map virtual addresses to physical addresses, use the virtual to entity conversion table to enable the software program to implement the demand paging mechanism (as explained below)' and usually through various operating systems (eg Windows • Mobile) (Symbian and Linux) use; (in) one of the requirements of the paging mechanism coefficient implementation (by the MMU enablement) that makes the virtual memory space equal to or greater than the physical memory space; (A) when booting One When the paging mechanism is sought and the host system processor attempts to read content from the virtual memory space (eg, during code execution or by code usage), the MMU computes the requested virtual page and is in the internal cache memory Looking for the page; (B) if the page is not in the cache memory, the mmu searches for the physical address in the ram where the code or data is located in the virtual to entity table; (C) if The code or data is not mapped to a RAM physical address (and because: this can not be retrieved) 'then a page miss occurs; and (D) should be page missed, the MMU will call an abnormal interrupt to the The host system processes n 'the system is expected to be provided by the nvm. The 123608.doc 1357017 missing page The above prior art to multiple management systems becomes difficult to handle.

The main problem with the method is the complexity of the program. This program is caused by the drive, the protocol involved, and the prior art, Microsoft Windows CE (4.2 or higher) supports the Thunder eight answer and then seeks the page. To support this demand paging mechanism, developers need to provide dedicated integration for this operating system. During development, 'developers need to install — file system drives and a device driver' and in a unique way (ie not similar to the cups required for storage memory that does not store code for demanding paging - 敕 Α, Α μ ^ water Any integration) to format the storage memory. Need a memory management system #,# tfc ·χ+· i 其中 其中 该 该 该 该 该 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机 主机Directly or indirectly). However, the host system processor requires that the data be obtained synchronously and within a very short response time (e.g., typically 4 to 5 clock cycles). This solution is difficult to provide because some of these system components (e.g., the NVM) cannot operate synchronously and/or cannot provide a coarse-grained door for the required response time. In this case, together with the search for the rest of the host vehicle, the fact that the charging processor cannot be externally interrupted during the operation is the first month, and the technical troublesome method seems to be the only possible solution. There is a need to provide a memory management system that can be used synchronously with a host system processor for code requirements, regardless of where the code is stored (ie, in the cache, in the RAM, or in the NVM) The present invention provides the code. SUMMARY OF THE INVENTION The object of the present invention is to provide a code delivery 123608.doc 1357017 system capable of processing a demand page code, which is independent of a host system processor and job and has no latent For the sake of clarity, 'there are specific tombs for the use of this article. (7) The following terms are used. The term &quot;program counter is used in this article, and &quot;Pc" is used. . The internal memory of one of the host system devices is not included in the table.

The current command executed by Ji Tian's host system processor... When the processor completes the command execution, the host system processor automatically recurs the ρ to optimize the host system.

The processor uses a special &quot;branch&quot; or &quot;jump&quot; command to make the job a single address. In this article, the term "software interrupt" 盥 &quot;SWI&quot; decision_^ I a a W1 table is not a processor command, which automatically sets the PC to a &quot;reset vector&quot; address. After the reset vector address, the host system processor immediately begins executing the code at the address. The term, software interrupt handler, is used herein to denote the code at the reset vector address and it is After the software interrupt is executed, it is executed by the host system processor.

The term "processor cache memory" is used herein to mean a portion of a memory in a computing system that has the fastest performance and typically a finite volume. The term &quot;page&quot; is used herein to mean a given The smallest unit (usually 2 to 4 kilobytes) of data used for memory management in a given system. The term "fragment" is used in this article to mean a contiguous set of pages of the same type of use (such as VM and NVM in the load or store method). The term "•code" is used in this article to mean that it can be handled by one. A processor command set to be executed by the device. The term "resident code" is used herein to mean that the code that resides in the vm is retained once the VM is loaded and that it does not need 123608.doc 1357017 immediately after the request. NVM loading. The resident code is also / the execution of % does not involve latent time. This article uses the term &quot;CPU month; # &amp; atom does not make M to represent a CPU (central

Proc — y central processing unit) operation, which cannot be done by anything

The device is interrupted (for example, hardware or software interrupt) and thus will always be completed if it is started. The term &quot;code feed device&quot; and &quot;CDS&quot; are used herein to refer to a hardware controller that is coupled to a host system processor by a master _p@1 匕 hidden bus. The CDS is connected to the main system memory or embedded in the main system memory by a Li Wei Futian system 6 memory bus. Before the request reaches the main system memory, the CDS Each access request of the system record & +, μ ^ u is passed through the CDS. In the present invention, the CDS is responsible for responding to the request - one of the command code CPU requests to deliver the following command code (a) the command code from the main system memory, or (b) one of the command codes different from the request. The term, the code segment table is used herein to mean that the processor is maintained in the host system. In a table, each code segment in # is represented by a start address or segment number and the length of the command code. In a preferred embodiment of the present invention, the teaching-memory management system 'satisfies Synchronous CPU requests for command codes, thus by various sources (some sources The code is provided in a non-synchronized manner. In another preferred embodiment of the present invention, a teaching-memory management mechanism is provided that provides a host system processor having a synchronous response to any code read request, regardless of the request Whether the code is available in the VM. The CDS is used to route to each access request. After receiving the code read request from the host system processor, the CDS will forward the request to the host. The VM receives the data from the request of the primary VM and delivers the data from the 123608.doc • 10· 1357017 the VM to the host system processor. The host system processor requires a number of clock pulses (usually 11 to 8) (3 to 5 pulses) within the delivery code (ie data read request). If the code is already in the middle, then the box is usually

It is enough. However, if the code is not resident in the VM and must be loaded from the NVM, then the box is insufficient for the CDS to retrieve the code from the NVM. In the preferred embodiment of the present invention, in the case where the requested code cannot be delivered from the VM on time by the CDS (since the code can be stored in the octave k-speed storage device), the 〇1)8 By avoiding the latent situation by providing the host system processor with the WI form "Replacement Code". The host system processor continues to fetch and execute the SWI instead of the actual code. After performing the (4), the host system processor immediately disables the hardware interrupt in the "cafe atom operation", stores the CPU (4), etc., and temporarily jumps to the state and jumps to the -reset vector address. * The reset vector includes a code that causes the host system processor to execute the code in a finite loop (&quot;wait, road). When the host system processor completes the resetting to the mile mode, the host system processor restores the CPU register state, enabling the hardware interrupts and jumping back to the address of the SWI (all in the Executed within a CPU atomic operation time). If the CDS is loading the actual requested code from the NVM to the dump when the host system processor executes the reset vector program, the C(10) provides the SWI again so that the host system processor will Again, the reset vector wait loop program is repeated until the code that completes the request is taken from the NVM. When the CDS has completed the cancellation of the code, the CDS waits for the next time the host system is at 123608.doc • 11 (d) The CDS identifies the address of the SWI and calculates the corresponding load. a virtual memory segment number; (e) the CDS then loads the calculated virtual memory segment number data from the NVM to the system and the main memory; and (f) once the material is loaded into the system main memory Body, the CDS updates the virtual to entity table (ie, updates the &quot;newload number&quot; main memory entity address and marks the previous page as &quot;missing·,). Therefore, in accordance with the present invention, for the first time, a computer readable storage medium is provided which has a computer readable reading on the computer readable storage medium. The reading code includes: (4) a code for Responding to one of the command codes from one machine, the first host system processor, a cpu request to deliver one of the SWIs different from the command code. Preferably, the SWI is operable to cause the host system processor to again request the command code. Preferably, the command code resides in an NVM. Preferably, the command code is retrieved from a remote source. Preferably, the code is embedded in one of the host system's main v pieces. More preferably, the computer readable code further comprises: (1?) code for converting the virtual address to the physical address of the read request, and immediately reading each read request Oriented to the main component, regardless of whether the command code is part of a code segment or a missing code segment. τ'&quot; Preferably, the computer readable code further comprises: (b) a code for selecting between providing the command code and providing the 123608.doc 1357017 SW7 based on the availability of the command code. . Preferably, the computer readable code further comprises: (8) a program mother for identifying the resident code; and (4) a code for avoiding receiving the pair of resident code &lt; accessing the user Preferably, the computer readable code further comprises: (8) a code, and a second (4) command code table to distinguish - a command code read request and a data read The request, wherein the command code read request is different from the request (4) fetch request. Preferably, the computer readable code step comprises: (b) a code for identifying whether the requested code data segment is available in the primary VM component of the host system. Preferably, the computer readable code further comprises: (8) a code that uses the machine code to respond to the host system processor without causing latency when the command code is missing a portion of the code segment. Preferably, the computer readable code further comprises: (b) a code for providing a synchronous response to one of the CPU requests. Preferably, the computer readable code further comprises: (8) a code for converting the virtual address into a physical address and storing the address in a conversion table; and (c) a program Code, which is used for command code management. The sub-optimal system, the code for command code management, is operable to update the conversion table in accordance with an update command transmitted by the host system processor. These and other specific embodiments will be apparent from the following detailed description and examples. [Embodiment] 123608.doc -15- 1357017 The present invention relates to a system capable of handling code delivery management of demand page numbers, which is independent of a host system processor and operating system and has no latency. The principles and operation of the code delivery management for the monthly processing of demand paging according to the present invention can be better understood with reference to the accompanying description and drawings.

Referring now to the drawings, Figure 1 shows a simplified flow diagram of a capture program in accordance with a preferred embodiment of the present invention. After receiving a request for reading or writing from the host system processor (step 20), the CDS checks the request for the following problem (step 22):

(1) Is the request a read request? (7) Is the material a break in one of the &quot;codes&quot; areas? (3) Is the fragment not in the mind (ie, • Missing data &quot;)? If all three of the problem answers in step 22 are answered, then the CDS uses the S WI to back up the host system processor (step 24). If the answer to the question such as β or the answer to the question (4) in step 22 is no, then (10) the access is

The request is forwarded to the memory (step 26). Regarding the first two questions in step 22, it should be noted that the present invention Φ is mainly about the retrieval request and the code, not the information. An example code of a fill code having one of the processor commands that changes the PC value to a value of the address (eg, the reset vector address): swi 0x1 (with one of the input parameters 1 soft) Micro tb age, interrupt). In this example the processor commands a SWI. The software interrupt handler knows how to process the SWI based on the input parameters. When the host is ready to perform the SWI from the winter system, the other interrupts are stopped.

The sub-device is automatically stored to a specific location and the PC 123608.doc -16- 1357017

The value changes to the reset vector. The PC is changed by invoking the SWI, which stores all the scratchpads in a stack and automatically jumps to the reset vector address. The following shows that the reset vector code (i.e., the software interrupt handler) is located at the reset vector address and is executed immediately after receiving a SWI after deactivating all other interrupts. (1) push r4 ; (2) wait in loop 〇f 1000 ; (3) mov r4, #l〇〇〇; (4) LI subs r4, r4, #1 ; (5) nop ; (wait) (6) bne %B1 ; (5) end of loop; (6) (push register) (initial r4 (counter) to looo) (label 1: decrement r4) (if r4#0, jump to li) P〇P r4 : (Eject register) (8) (9) (The current lr value is SWI+4 (executed by SWI)) subs lr, lr, #4; (set lr value to the s WI address) ret ; (jump back to the SWI address) (Enable interrupt) When the system processor jumps to the reset vector code, the post range is deactivated and the register of the host system processor is saved (including the &quot The most temporary storage benefit, which immediately has a &quot;jumpback&quot; for the host system processor after the completion of the reset vector code, and the reset vector code indicates the host system ring, and everyone is 叽The processor loops through 1000 loops and executes a nop command (ie, &quot;no operation 7). The host system is at 123608.doc 1357017

When the processor finishes executing the loop, the LR register is set to the address from which the swi is called. In the case where the host system processor is an ARM processor, the ARM processor saves the &quot;SWI address +4· in the LR register after the SWI is executed. To calculate the SWI address, the host system processor subtracts four from the value in the LR register. When the host system processor executes the return command, the re-enable interrupt resumes the registers, and the host system processor returns the SWI address (all executed in the -epu original +=).

However, the present invention has been described with respect to a limited number of specific embodiments. It is apparent that many variations, similar applications, and other applications can be made to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS In the present specification, the present invention has been described with reference to the accompanying drawings only in the form of m, -, and the flow chart is shown. A simple embodiment of the capture program

123608.doc

Claims (1)

1357017 • Patent Application No. 096129149 (Replacement of Patent Application Range (August 10)) X. Patent Application Range: 1 · A storage system comprising: a code delivery server CDS defined by a hardware controller The m mnemonic 'operates to connect the cds, and via the: CDS delivery - the code 'The code includes - the software interrupt SWI, to... the response - the command code - the CPU request, wherein the software interrupt is different In the life of 7 ́ and where the main system memory is - asynchronous external resources; and though. a machine system processor 'connected to the CDS, the host system processor being operative to execute the code stored in the main system memory in response to receiving the software interrupt, wherein the CPU request system belongs to a host The host system processor of the system. 2. For example. The storage system of item 1, wherein the software interrupt is operable to cause the host system processor to request the command code again. 3. The storage system of claim 1, wherein the main system and the memory are an NVM. Lu 4. For example. The storage system of item 1 of claim 1, wherein the command code is retrieved from the source of the remote end. 5. The storage system of claim 1 wherein the code is embedded in a main system memory component of the host system. The storage system of item 5, wherein the code is further operable to direct each read request to the main system memory component after converting the virtual address of one of the read requests into a physical address Regardless of whether the τ 7 code is a part of the existing code segment or a missing segment. I23608-1000804.doc 1357017 7. The storage system of claim 1, wherein the code is further operable to select between providing the command code and the softening based on the availability of the command code. 8. The storage system of the present invention, wherein the code is further operable to identify the resident image and to avoid checking the access code for the resident code after receiving the access request to the residual code System memory. 9. The storage system of claim 1 wherein the program is operable to distinguish between the command code reading table and the command code reading request, wherein the command code reading request It is different from this data read request. 10. If the request t is stored (4), wherein the program is operable to identify whether a requested code data segment is available in one of the host system main system memory components. η·such as the requestor's storage system' wherein the code is further operable to use a software interrupting the machine code when the command code is part of a missing code segment, back and forth to the host system processor without causing latency. 12. As requested! The storage system, wherein the code is further operable to provide a synchronous response to one of the CPU requests. *, 13. The storage system of the requester, wherein the code is further operable to convert the virtual address into a physical address, to store the material address in a conversion table, and for command code management. 14. The storage system of claim π, wherein the code for the 7-code official is operable to update the conversion table in accordance with an update command communicated by the host system processing the A+ state. 123608-1000804.doc -2- 1357017 15 - a storage system comprising: a code delivery server CDS defined by a hardware controller; a main system memory operatively connected to the cDS, and Delivering a code via the CDS, the code including a software interrupt swi in response to a CPU request for a command code, wherein the software makes the break system different from the command code, and the code code is stored in the a primary system memory reset vector; and a host system processor coupled to the CDS, the host system processing operation to execute the code stored in the main system memory in response to receiving the software interrupt And wherein the 匚〇8 jumps to the reset vector and the host system processor executes the code stored in the reset vector in response to a command code not present in the main system memory. 16. The storage system of claim 15, wherein after executing the code, the CDS jumps to an address that initiates the software interrupt, and the CDs determines whether the command code is present in the memory. 17. A method for delivering a code to a host system. The method comprises the steps of: (a) accepting a cpu request for one of the code segments from a host processor of the host system; (b) Initiating a capture program to retrieve the code segment; (c) immediately after the expiration of a pre-hair time, checking whether the code segment is ready for delivery; (d) after the expiration of the predetermined time period and in the code segment Before preparing for delivery, provide a software interrupt SWI different from one of the code segments, where the swi bow! 123608-1000804.doc The host system processor disables hardware interrupts, stores all cpu registers and states, and jumps to a reset vector address, and () after the expiration of the preview time and The code segment is provided after the code segment is ready for delivery. 18. The method of claim 17, wherein one of the reset vector addresses is reset. The vector code includes a command to request the segment again. The method of month length item 17, wherein the reset vector includes a mom that causes the host system processor to execute the code in the -finite loop. 2. The method of claim 17, wherein the operation of deactivating the hardware interrupt, the operation of storing all of the CPU registers and states, and the operation of the jump to a reset address are Executed in a CPU atomic operation. The method of claim 17, wherein after completing the reset vector program, the SWI causes the host system processor to resume the hardware interrupt of the CPU register and the jump to the start. The address of the s. 22. The method of claim 21, wherein the recovering the cpu operation, the hard-working operation, and the operation of jumping back to the address of the SWI are performed in a CPU atomic operation. 23. The method of claim 17, wherein the method satisfies a CPU request for one of the command codes. The command code has a code from an asynchronous source. 24. A method for satisfying a synchronization request for a command code, the method comprising: accepting a CPU request for one of the code segments, the CPU requesting a host processor from the host system; initiating a fetch procedure Take the code segment; 123608-1000804.doc -4- 25. 26. 27. 28. When it is determined that the code segment can be delivered on time, the code request is provided immediately; when it is determined that the code segment cannot be delivered on time Immediately avoiding the latent situation by providing a replacement code to the host system processor, the replacement code being configured to cause the host system processor to disable the hardware interrupt in the -cpu atomic operation's storage of all CPU temporary storage Fang Ziyi and the state, and jump to a reset vector address to start a reset vector program. The method of claim 24, wherein the vector program defines a wait-back mode. In the method of claim 24, the substitute chess 3 code is configured to cause the host system processor to 'restore the CPU register' in a CPU atomic operation upon completion of the reset vector And the strong Atkk condition, enable the hardware to break, and jump back to the address that initiated the replacement code. The method of claim 24, further comprising: upon determining that the code segment has not been loaded during execution of the reset vector program, then immediately providing the processor with a replacement horse. As in the method of claim 24, If the code segment is located in the volatile memory, the code segment can be delivered on time to be determined; and if the code segment is located in the non-volatile memory, the code segment cannot be delivered on time to be determined. 1000804.doc 1357017 Η , Drawing: Patent Application No. 096129149 (Chinese version of the original application) (Review of 100 years) 123608-fig-1000908.doc