TWI355808B - - Google Patents

Description

1355808 May 4, 100 revised replacement page

-------H IX, invention description: [Technology of the invention] The present invention relates to a triangular integral modulator, especially a multi-bit triangle of circuit error used in a digital analog converter Integral modulator. [Prior Art]

Although the delta-sigma modulator, DSMJ uses a coarser quantizer, it is still widely used to achieve high-resolution digital analog conversion. The first picture is the traditional second-order triangular integral. A functional block diagram of the modulator, the modulator comprising a first summing circuit HQ, a first, a divider 120, a second summing circuit 13A, a second integrator 14A, a quantization f L50, a first digital analog converter '17〇 and a second digital analog to digital conversion circuit is used to subtract a modulation input signal = scoop feedback signal (or global feedback signal); The first integrator two-way 0.5ZV (1/) conversion function is used to set the first-plus total electric first product 八m, and the second totaling circuit 130 is used to divide the ' ^ having - near the second inverse 11 signal / 2 (9); the output of the second product summing circuit 130 is subjected to a transfer function for the second converter, for use in convolving to the quantizer; 150 (ie analog analog bit modulation output signal; <Λ). ^; product / ^ 140 round-out digitization into an N-bit conversion of the Ν-bit modulation ^ a digital analog converter 17 〇 (or DAC) Z0?); the second digit class. . > X77) to become the first feedback signal Κ/7) to become the second inverse, & 160 convert the 调 bit modulation output signal 1515 to /2(η).

The signal of the 'γ θ - A system mentioned in this specification. When the sampling frequency of _, the model (4) time index or the discrete time month 'J 5 K/2) is much higher than the bandwidth of the transmission 1355808, the triangular integral π hangs and yI-- replaces the page to suppress its frequency band. The role of: Zhou • iso $ converter (10), triangulation and the first-to-digital analog ratio (S chat 1 10 is a high intra-frequency signal to quantify the Quantization noise ratio, SQMR) 〇 ^ ^ ^ Tune: The number of integrators used for money represents the order of the modulator. 3 . Brother's a gradual change of crying wood unstable intra-frequency signal pairs. The light of the ^; the light of the image, the 'a image and the better one but the second two, the _ _, is the (10) triangular integral tone; the =I1 bit metadata conversion is linear in nature and is more simple. In the modulator, you can use 1]-] 』] weekday 7 action however, the range is small, conditionally stable, and the production and delivery points can be hunted by using multi-bit metadata conversion (ie Ν>1) *2k The second deficiency causes the source circuit error, which is the same as or _ linear) and the delta-sigma modulator suppresses. η, 里化4 ' can not effectively be used by the kernel can not be applied to very high speed y y, the bit algorithm, by the triangular integral modulator 4 = ^ ^ a simple number of characteristics to effectively suppress the circuit error . , *Conversion non-linearity] May 4, 00 revised replacement page • [Invention] Digital power 'dl' f provides a kind of non-integral input using a digital-to-digital analog converter, tree-feedback signal To reduce the total circuit month: the delta-sigma modulator, which includes - the first-quantization of the crying and product $ circuit, the second summing circuit, the chopper circuit, the number, and the - ° first - total circuit based on - modulating the input signal interrogation signal to generate a first - - first product, ~ road scale 5 - the intermediate signal is integrated to generate a second feedback &; = = total circuit is based on the first - integral signal and - One 〒 '丨化5虎. The filter circuit includes - 筮 - the display signal to generate - ^ wave ^. The knife circuit 'is used to process the second generated - W - r / , to quantize the filtered signal to generate an N-bit (or multi-bit) output signal (N > 1, _ illusion. The feedback circuit receives the N-bit rounds out, you have enough to change the -----__==== turn Ϊ a path includes - (four) bits _: in the example 'where the second feedback path produces two The w tiger' is provided to the first-plus-slave circuit as an 八, or, in the embodiment, the signal is fed to the second feedback path and passed to the second summing circuit. In the example, the feedback circuit further includes a - (Ν~1:) bit to receive the 调 bit modulated output signal ((4) has: used for significant blts). (4) The bit accumulator includes a "coffee device" and a delay element Generate - (Ν - 累 的 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Slgmflcant bits) is to generate a first feedback to generate a first feedback. The feedback path is provided to the output of the digital analog converter as a ChG V embodiment by providing (N-1) bits. The bit digit analog analog converts the crying wheel: = the input of the converter = and converts the (N-1) feedback signal to the first force: '. 2 additional bits 延迟 the delay wheel of the adder — 1 , by the (M) (N-1) bit digit analog analog bitwise analog converter and multiply the round of the na sister, the special state by a scale, Huai 吝 4 '" The feedback signal is given to the second summing circuit. The 乂 generation can be matched with the first group signal and further includes a third feedback signal. For example, - set #-number _, ratio converter to receive N sin three feedback signals to Secondly, the output end of the sub-product transformer and the total power _^:^ feedback path axis are connected to the second embodiment t, and the chopper circuit further includes a third total circuit, using a second group, The red dragonfly is re-added to generate a third intermediate signal, wherein the tiger includes the output of the second integrating circuit and the input; or, the =2 includes the output of the second integrating circuit and the output of the second summing circuit - , 4 can have other feed-forward compensation paths that bypass the - or multiple summing circuits. There are also consistent applications where the money circuit includes at least - Less total circuit - additional integration circuit to increase the order of multiple (four) delta-sigma modulators Multi-bit 7L two-angle integral modulation H The integrator can be continuous-time integrators or discrete time Integral ^ (discrete-time integrators). For example, discrete time integral crying knife = - use - differential switching capacitive integrator for input capacitance (switch-capacitor integrator), a differential operation to enlarge Da ( Differential 〇Perational amplifier), _ for the feedback capacitor to 2 10 L100 May 4 correction replacement page multiple pulse signal control ^^ - in a single differential operation to enlarge the crying (four) one after the 1% case - The summing circuit is combined with the first-to-on-axis, the circuit is 'in which the analog-to-analog turns to touch the second pair of capacitors to the digital output' and the multi-signal is used to calculate the amplifier and the plurality of switches. Similarly, the first force i == differential capacitance on the power amplifier 8 is added to the weight ratio second - in the embodiment, the 'digital analog converter system is set in the three pairs of 4 (3-to-l Multipiexer) differential circuit (diff_tiai circu. For example, 'provide a 2-bit input signal to the two-way three-way: select the ternary digitizer on the line (10), ;, three: solid reference voltage for each three The input end of the multiplexer. The first eve of the work produces the pQsitive end of the wire signal, while the second three-pair multiplexer produces the negative side of the differential signal (negative _). In the example, the present invention discloses a method for reducing circuit error, which is based on the -N-ary three-dimensional partial modulation conversion 11 - N-bit feedback digital analog conversion gram, where the multi-digit triangular integral modulator Substituting the N-bit feedback digits, the ratio converter is a -(N-1)-bit digital-to-bit analog converter and a digit-to-digital analog converter. The execution steps include: performing a first weight addition on the first-group signal to generate - The first-mediation says that the first set of signals contains a modulated input signal and a -th-feedback signal. The signal is integrated to generate an integrated signal. The method further includes performing a second weight addition on the second set of signals to generate a second intermediate signal 'where the second set of signals includes a first integrated signal and a second feedback signal After filtering, the second intermediate signal will generate a "me:" number, and the filtered signal is then quantized to generate an N-bit modulated output signal.

丄JJJOUO bit to generate _ (N ^ N bit modulation output signal _ - l) lower significant bit signal plus N bit ^ ^ signal and - 丨 red health key, the incoming signal, through the digit :ΐί. The most significant bit of the signal is output to generate a total of additional signals, and the converted signal is converted into a first feedback signal. (N-i) Bits and domains will still pass - contain numbers. For example, the (four)^--the feedback path is converted into the second feedback signal. (4) The lower-effective bit and the variable=signal are provided and the _-nn is delayed to generate the 0^1 bit sum signal. (N-1) bit number two = become the (N-1) bit analog converter output) bit 疋 digital analog converter output will be scaled = I digital analog converter and pair (Ν _ υ bit input, The differential signal is used to generate the feedback signal, wherein == the first group signal is combined to generate the first intermediate signal. Other feedback U tiger can be used to perform the bit position view_recording dragon_conversion ^=70 triangular integral modulation The feedforward compensation method can also be used to enter the service. The above summary and the following detailed description and the accompanying drawings are all for the purpose of shovel and one step to explain the purpose, means and merits of the purpose of the release. Further objects and advantages of the present invention will be described in the following description and drawings. [Embodiment] The present invention discloses a method and apparatus for reducing electric power difference, for example, in a plurality of positions. Feedback digital analog converter in the meta-triangular integral modulator.

Amendment of the replacement page on May 4, 100, and the description of the present invention _ indicates that the 剌 剌 在 在 在 在 在 在 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 By means of the second and second, the embodiment is a multi-bit triangle disclosed by the present invention. The multi (four) three_segment transformer wrapper summation circuit 210Α generates a first intermediaries (five) earning dire) signal ri(3) according to the domain value of a first set of letters f. Example ', the second domain electric _ _ machine "Qian Xin" minus M - feedback signal f and the younger one feedback letter, heart) to generate the first intermediary signal coffee, and by the = integral circuit coffee to the first - intervening (3) Integrate to generate the di-and sub-signal /, ω. For example, the first-integral electric paste has a transfer function of about 5 ζ / (11), providing the first-integral signal 9 (9) to the second summation, 23Q-A, the weight of the two sets of signals plus the total value (we god d _) two produces the first: t AK /?) 'For example, by the second summing circuit 2 将 to reduce the brother-integrated signal / heart) Going to the third feedback signal a heart) (or region feedback signal) to generate a second intermediate signal r2 〇 7). The multi-element triangular integral modulator employs a wave circuit 24 〇 for processing the second intermediary The signal is (5) to generate a filtered signal/heart. As in the second Figure A, the filter circuit 240 includes a second integrator, which is suitable for a second-order delta-sigma modulator, which may also include additional The integrator and the summing circuit are applied to a more order triangular integral modulator. In addition, the product of the first-integral circuit and the chopper circuit 240 The a-plane discrete time integral n can also be a continuous time integrator. For example, the I-wave circuit 240 has a transfer function of -Jorsong-νπγ, providing a filtered signal (or a second integrated signal)/2 (/ 7) to the N-bit quantizer 25A, the quantizer 250 quantizes the level signal Λ(/7) to generate a -N-bit modulated output signal y(/?), where N is a An integer greater than 1. 13 Multi-bit triangular integral modulator 200A includes a plurality of feedback circuits. The first feedback circuit 295A generates a first feedback signal ai (9) and a second feedback signal 2 (9) and The second feedback circuit 26 generates a third feedback signal output )7) and supplies it to the second summing circuit 23A. An additional feedback circuit is used to generate an additional feedback signal. a first summing circuit 21A, a second summing circuit or other summing circuit on the filter circuit 240. In one embodiment, the second counter 260 and any other (10) circuit system bit contacts, The input end of the converter is connected to the N-bit modulation output signal ^(^). In the embodiment, the 'first-feedback circuit m includes (4) Bit addition 295, - delay circuit 265 (eg: one unit sample (-a qing (6) delay ^), : (N-D bit digital analog converter 270, - differentiator 275A, a tl bit tl Adder 293 and - ternary digit analog conversion · Q. The delay delay circuit shifts 0H) The bit adder 280 accumulates the N bit modulated output signal (6)) the lower significant bit (ie, coffee)) to generate a (6)) the addition signal s (f) of the bit and the carry signal c 〇 7) of the element. The (μ) bit addition signal is supplied to the delay circuit 265 to generate the -delay addition signal (10) as the (four) bit plus function. The turn-in value. In addition, it provides (four) Fu Jiafa signal to give (four) bits to the digital analogy of Laihu to produce - analog output coffee, shop ratio, step by step through the differential fiber and iron to become the second anti-age, heart). = = the most significant bit of the heart-level output signal (ie, coffee) is added to the adder 293 of the bit to generate a 2-bit three-conversion, and the three-dimensional letter is compared to the map. The multi-bit triangular integral modulator 2_ and the multi-bit triangular integral modulator of the first graph, the difference is to use the first feedback =

1355808 1 I May 4th, 100th revised replacement page 295A replaces the first N-bit digital analog converter 17〇. The following describes how the first feedback circuit 295A having the function of the ternary digit analog converter 290 and the (N-1) bit digital analog converter 27 is up to the first function of the dynamometer analog converter 17 ^ The N-bit modulation output signal y(/?) has a possible value of 2〃: {〇, L 2' , 2 }, which assumes that all the digital analog conversions in the first and second eight graphs are It is ideal and the weight of the lower significant bit is approximately Δ. The first feedback signal force (9) of the modulator 100 in the first figure is defined by the following equation: f\ (^) = y(ri) Δ (1) In the second A diagram, the differential operation is performed by the analog wheel (knife) from the (N-1)-bit digital analog converter. Further, a second feedback signal <9' 2(/7) is obtained. The second feedback signal in Figure 2A is defined by the following equation: a\ {n)^a2{n)-a2{n-\) (2) Ν 调 调 轮 轮 轮 ΟΜ) The most significant bits of the effective bit and the 调 bit modulated output signal can be represented by the following mathematical formula: 八(8)=mod(y(8),2"-丨) (3) yM («) = \y(rt) - yL (n) ]/2N-] (4) The (N-1) bit adder 280 of the additional unit sample delay (unit_sampledelay) 265 accumulates the (N-丨) lower significant bits of the N-bit modulated output signal (N) -1) The addition signal of the bit is the sum signal) and the 1-bit carry signal ^ (knife), the (N_1)-bit addition signal 〆 is) and the 1-bit carry signal C (/7) is the following mathematics The expression is: 5(^) = mod^^ (n) + s(n -1), 2 ) (5) ♦) = [^(8) + coffee-1) - φ)]/2ΛΜ (6) The following formula can be used It can be seen that the 2-bit ternary signal 甙77) is obtained by summing C(;7) and j^/7): 15 100 May 4曰d{n) = c{n) + yM{n ) Correct replacement page

The weight of the least significant bit of the (N-1) bit addition signal han/7) is also similar to 厶, but the 1-bit carry signal ^(/7) is about 2"1 times higher because it is from ( Ν _ υ 加 加 加 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 280 Therefore, the analogy output signal (1) from the (Ν)) bit number class = conversion β 270 and the first feedback number 5丨 (/?) in the second a picture can be obtained by the following formula: . A2(n) = s(n)-A (8) 4 (8) Whistle "). (2ΛΜ △) = [c(8) + &(8)].(2"-ι △) (9) According to equations (2) and (8), second The second feedback signal in the eight diagrams can be changed by the following formula: a'2 («) = α2 (η) - α2 (η -1) = s(n)d, - s(n - 1) Δ (J〇) According to equations (10), (9), (6) and (4), the second feedback signal 2(/2) in the second graph can be simplified by the following formula: 2 (deduction, (8) = s(8) Δ-咖-ΐμ + 咖)_(2λμ△)+~(8)(2called △) (11) -々)△ φ - !)△ + h (8) + coffee _ _ _ 咖)]△ + ♦) △(8)△ = y(n) · Δ - From equations (1) and (11), the first feedback signal /1(/7) in the first graph is equivalent to the first feedback signal a in the second Ail (/? And the second feedback signal? 2〇?), so 'if all digital analog converters are ideal, then have a ternary digit analog conversion 290 and (N-1) bit analog converter 27〇 The first feedback circuit 295A is functionally equivalent to the first-to-digital ratio converter [7]. / (8) two-core (8) + coincidence (8) (12) u when the number-pitch converter is not ideal, the second A The figure has the first anti The multi-element delta-sigma-integrator 2_ of the feed circuit 295A will be better than the multi-element 1355808 in the first picture. The modified page delta-integral modulator (10) is better on May 4th of the following year. ^ Modulator In 100, the delta-level delta integration difference from the first·μ map will be at the input end of the first-to-high total circuit 11〇, and the circuit error generated by the circuit is like a modulation input H槐. "Λ ", outside the noise. These extra signals, the effect of the (four)f tiger's transmission characteristics, and thus the miscellaneous...'s method is suppressed at the output of the § week. Secondly, the conversion of multiple bits of the triangular integral modulator 2_ can suppress the digital analogy. , the difference a in the convergence of the 275A input terminal = knot: the first - plus total circuit test modulation input letter: before = transformer output::: bit digital analog converter (10) noise can be provided The output value of the ternary analog converter 29〇 is given to the first addition 210A, so any circuit error generated by the second opening f / the east g μ 〜 毛 数 数 数 数 数 290 290 290 290 will be in the first total The input of the circuit 210Α causes additional noise to be transmitted like a modulated input signal, which is affected by the transmission characteristics. The noise of the 1=2=number-to-toe conversion is not available at the output of the modulator. inhibition. At the same time, the ternary number on the fully differential circuit topology (fully gamma _〇1) is compared to the minimum surface correlation circuit. When the combination is 1 red, the linear effect can still be achieved. Therefore, the adjustment k: output # in the second A diagram can relatively avoid the noise by feeding back the circuit error of the digital analog converter. second. B. The figure illustrates an embodiment of another multi-bit delta-sigma modulator 2_. This modulator 200B more preferably omits the differentiator 275A. The differentiator 275A in the second A picture is set after the first-integration circuit 2 is silent. If the differentiator is placed after the integrator, it means that the signal is not 17 100 years except that a delay and a scaling signal are generated. Correcting the replacement page on May 4 will have any effect. 5的放大。 For example, the value of the unit sampling delay is 0.25. action). Thus, the differentiator circuit 275 can be bypassed to remove the differentiator 275A to produce an appropriate scaling and delay value to the analog output of the (N-1) bit digital analog converter 27A (9). The first summing circuit 210B in the second B diagram generates a first intermediate signal 〆, (/3) according to the summed value of the modulated input signal X/7) and the first feedback signal "si (/?). Then, the first integration circuit 220 integrates the first intermediate signal r', (/?) to generate a first integrated signal corpse, 0). A first integrated signal factory 1 (/?) is then provided to the second summing circuit 23 0B to generate a second intermediate signal 竣1 (/?) based on the weighted total value of the second set of signals. For example, the second summing circuit 230B will generate the first from the first integral signal /,, (... minus the first feedback 彳§ 〇. 5a" 2 (/?-1) and the third feedback signal !!! The second intermediate signal r2 (/?h is then processed by the filter circuit 24〇 to process the second intermediate signal factory 2(^) to generate a filtered signal/2(Λ) 'the filtered signal, (or the second integrated signal) is provided The bit quantizer 250 digitizes it to generate the erecting element modulation signal jK/?). The multi-bit binaural integral modulator 2〇〇b includes a first feedback circuit 295B, which is - feedback circuit 2 ship side to generate a first feedback money ai (five) to the first summing circuit 210B and generate a first feedback number 〇 2 (Λ _ι) to the second summing circuit 230 Β. The second feedback circuit 26 〇 (ie ν bit) The digital bit analog converter) also generates a second anti-lock signal (/?) to the second summing circuit 23 〇 β. In an embodiment, the 'first feedback circuit 295 Β includes -oh) the bit adder 280, the delay circuit 265, - (Ν-1) bit digital analog converter 27, a scaling parametric lion, -1 bit addition · 3 and - ternary - ratio converter 290. Delay circuit 265 is attached. (5)) The bit adder accumulates the N bit modulation transfer 18 1355808 • < On May 4, 100, the replacement page is replaced by the (N-1) lower effective bit (ie only ()), and then An addition 一 唬 / ? ? ? ? ? ? ? ? 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 产生 7 7 7 7 7 7 7 7 The addition signal is used as an input value of the (N-1)-bit adder 28〇, and then the delayed addition signal is transmitted to the (N-1)-bit digital analog converter 27 to generate A delay analog output 5, further scaling the delay analog output 5" 2 (/?-1) through the scaling parameter 275B to become the second feedback signal 〇. 5a" "knife ^. The 1-bit carry signal K/7) and the most significant bit of the N-bit modulated output signal (ie, <;?)) are then provided to the 1-bit adder 293 to generate a summed signal (eg, The 2-bit ternary signal is /?)). The binary digital analog converter 290 processes the ternary signal to generate a first feedback signal 51 (77). The multi-bit delta-sigma modulator 2 〇〇 B in the second B diagram is functionally equivalent to the multi-bit delta-sigma modulator 2 〇〇 A in the second A diagram. The first feedback circuit 29 删 more simplifies deleting the differentiator 275B to achieve the function of the first feedback circuit 295A in Figure 2A by providing a delayed addition signal $& to (n) bit digits The ratio is converted to 270' and the analog output value of the (Ni) bit digital analog converter wo is appropriately scaled, and the scaled value is used as the second feedback signal to the second summing circuit 230B' instead of the first plus The total circuit 2i〇b. A further embodiment of a multi-bit delta-sigma delta transformer 200C is disclosed in Figure 2C. The multi-bit two-angle integral modulator 2〇〇c in the first C picture is essentially similar to the multi-element triangular integral modulator 2〇〇Β in the second β-picture, the only difference being that the second feedback is reduced. Circuit 260 also adds a feedforward path. The present invention is applicable to a multi-element triangular integral modulator using feedforward compensation, regional feedforward compensation, or a combination thereof. For example, as shown in the second c-picture, the multi-bit delta-sigma modulator 2〇〇c has a feedforward path around the filter circuit 240 and includes at least one integration circuit. 19 1355808 May 4, 2014 Correction Replacement Page The feedforward path described above includes a gainer (gain bl. (8) for receiving the output value of the second summing circuit 23QC (or the rounding value of the filter circuit 24Q) and generating A feed forward ##, and shai two feed # number will then combine the output value of the filter circuit 240 in the third total circuit ms. The front diameter is functionally equivalent to the second (four) towel ^ yuan ^ analog converter The regional feedback path. The feedforward path can also bypass the first-integral band 220 or other integration circuit (not shown). The third figure reveals the ternary digits on the full-differential circuit. Analog converter 300 - embodiment. The ternary analog converter 3 receives a 2-bit ternary signal (or (4) DATA) and outputs - the corresponding differential signal, the three in the three The seam value _, 丨, 2), and the differential signal includes a forward end (four) rib e end, V 〇 UTP) and a negative end (clear (10) _ vo_. The ternary digit analog converter 300 uses three reference voltages: V_, 'VCM and face, the positive end of the differential money - "fine three kinds of = pressure, and the negative of the differential signal The end is connected to the ^^131°' control through the second multiplexer 32, and the three-reader ratio converter 3_wheeling is the voltage difference between the forward end and the negative end (ie, the multiplexer 31〇' 32 The individual outputs of the ) are analogous to the transition of (), and the three possible outputs of the three domain are generated at equal intervals. Therefore, the ternary analog converter 300 is linear in nature. Qing / for

VOUTP VREFN

DAC OUTPUT

VOUTN VREFN-VREFP

20

Correction Replacement Page 2 May 4, 100 VREFP —————— VREFN ------—VREFP-VREFN Table 1135808, Rev. 4, Example of Discrete Time Integrator, Discrete Time Product The difference can be compared with the capacitance integral material. _Sewing capacitor

Cm2) is the input end of the fully differential op amp side, and the feedback capacitor (Cfbl, Cfb2) is at the output of the fully differential op amp shed, and is controlled by a plurality of clock signals. (switeh) to achieve the function of time-integration. The fifth figure discloses an embodiment of an integrating circuit having a summing circuit function, wherein the integrating circuit is implemented using a discrete time integrator. As shown in FIG. 5, the summing circuit in front of the integrating circuit receives a feedback signal from the digital-to-digital converter, and the summing circuit can be efficiently combined with the integrator to a single-channel fully differential parent. Switching capacitor circuit. For example, the first-plus-electricity (10) and the first integrator 220 can be combined with each other on a single-channel fully differential switched capacitor circuit, wherein the single-channel fully differential switched capacitor circuit has a first pair of input capacitors (ie cini, (:1112) to receive the _ change input signal and by the second pair of input capacitors (ie (10), Cin4) to receive the first feedback signal generated by the digital analog converter. The second summation' The circuit 230B can also be combined with a second integrator on the filter circuit 240 on a single fully differential switched capacitor circuit, wherein the single full differential switched capacitor circuit is received by a first pair of input capacitors The first integrated signal receives the first feedback 彳§ by a second pair of input valleys and receives the third feedback signal by a third pair of input capacitors. In an embodiment, the switched capacitor circuit can be borrowed The scaling parameter 275B is included by setting the capacitance ratio of each pair of input capacitors.

And the description of the specific embodiments of the present invention is only a detailed description of the specific embodiments of the present invention and the drawings. All the scope of the present invention shall be based on the following, and the following is applicable to those skilled in the art. In the field, the changes or modifications of Fan Fanyi can be covered in the following patents defined in this case [Simple Description]: ^ is a functional block diagram of the self-knowledge - 卩 兀 position 兀 triangle integral modulator; An embodiment of the functional block diagram of the multi-bit 7° delta-sigma modulator of the present invention is further implemented in the functional block diagram of the multi-bit three-distribution variable of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a schematic diagram of a functional block diagram of a three-dimensional digital converter of the present invention. FIG. Figure. Fifth _4 Shuming's silk-type capacitive surface - an embodiment of the schematic [main component symbol description] Conventional: First-order triangular integral modulator 100 First totaling circuit U〇22 1355808 Correction replacement on May 4, 100 Page first integrator 120 second summing circuit 130 second integrator 140 quantizer 150 first digital analog converter 170 second digital analog converter 160 modulated input signal X / 7) first feedback signal /; ( / ?) Second feedback signal / 2 (/?) N-bit modulation output signal X /?) The present invention: 200A, 200B, 200C: multi-bit triangular integral modulator 21.0A, 210B: the first total circuit 220: first integrating circuit 230A, 230B, 230C: second summing circuit 240: filter circuit 245: third summing circuit 250: quantizer 260: second feedback circuit 265: delay circuit 270: (N-1) bit Meta-digital analog converter 275A: differentiator 275B: scaling parameterizer 280: (N-1) bit adder 290, 300: ternary digit analog converter 1355808 May 4, 2014 Correction replacement page 293: 1-bit Adder 295A, 295B: first feedback circuit / (/?): modulation input signal 7 * 1 (77), corpse 1 (77): first intermediate signal 7 * 2 (77): Two intermediate signals / ι (/7), corpse 1 (77): first integral signal / 2 ( η): filtered signal y (77): Ν bit modulated output signal aO?): first feedback signal a, (/7) '0.53' 2(77-1): second feedback signal a" 2(77-1): delay analog output <33(7?): third feedback signal S(/7): addition signal C(/7) : 1-bit carry signal 5 (/7-/): delayed addition signal 32 (77): analog output d(n): ternary signal yz (/7): N-bit modulation output (N-1) lower effective bit M of the signal; ?) : most significant bit of the N-bit modulated output signal 310, 320: multiplexer 400: fully differential operational amplifier

Cfbl, Ofb2: feedback capacitor

Cinl, Cin2 first pair of input capacitors

Cin3, Cin4 second pair of input capacitors 24

Claims (1)

1355808 _ May 2014 4 曰Revision and replacement page X. Patent application scope: 1. A triangular integral modulator, comprising: - a first-plus total circuit is based on a modulated input signal and a first feedback signal Adding = and * - the first group of money to produce n intermediate signals; • a first knife circuit 'is used to integrate the first intermediate signal to produce: a first integrated signal; - the first road based on The weights of the first integrated signal and the second feedback signal are summed to obtain a second intermediate signal to generate a second intermediate signal; the circuit is configured to process the second intermediate signal to generate a chirp, a wave signal. The data circuit includes a second integration circuit; the chemistry system is used to quantize the data signal to generate a 调 bit modulation output signal; and the feedback power 珞 Hx receives the Ν bit 调Varying the output signal and using a digital analog converter to generate the first feedback signal and a -(Ν-1) bit digital analog converter to generate the second feedback signal. 2. For example, claim 4 Demodulator, wherein the feedback The circuit further includes: - a (Ν_1) bit accumulator for receiving the '(Ν-丨) lower significant bit in the 调 bit modulated output signal to generate a (Ν-1) bit An accumulation signal and a 1-bit carry signal, wherein the (.丨) bit accumulation signal is coupled to one of the input terminals of the (Ν-1)-bit digital analog converter; and, an adder, The highest significant bits of the 调 bit modulated output signal and the carry signal are used to generate a force ' ', wherein the sum signal is connected to the first digital analog to convert the cry , ^ 25 1355808 Corrected the replacement page input on May 4, 100. The second group of signals further includes a third feedback signal as described in claim 1 of the scope of the patent application. A second digital analogy produces the third inverter as described in claim 3, and further includes a converter for receiving the N-bit modulated round-out signal. °~' If the modulator described in the first application of the patent scope, 苴h ^^咕, the Jiahaohai filter circuit further includes a second summing circuit, based on a third set of signals 栺· Qnm\ Ab ^ t weighted sum to generate a third intermediate signal, wherein the - 弁 eight $, the music-level signal includes one of the input and an output of the first lance circuit. j. Please refer to the adjustment surface described in the third paragraph of the patent scope, wherein the hopping circuit further comprises a second two-plus circuit, which generates a second intermediate signal according to the weight of the third group of signals, wherein the third group is subtracted Including the first, ^ and the second summing circuit - output. ^The powder out 7. If you apply for the patent scope! The modulator according to the item, wherein the first integration circuit and the second integration circuit are both - discrete time integrators, and the discrete time integrator (differential switch-capacitor^ integrator 2 and the differential exchange capacitance integral The device includes a pair of input capacitors, a differential operation to amplify, - a feedback capacitor and a plurality of switches controlled by a plurality of time signals. 26 1355808 The modulating device of claim 1, wherein the first integrating circuit and the first integrating circuit are both a continuous time integrator. .9, as in the Cap's 1st review, the towel domain circuit is further included. There are at least - an additional summing circuit and at least one additional integrating circuit to increase the order of the delta-sigma modulator ( Order). 10. For example, please refer to the adjustment mentioned in item 1, where the first-to-digital analog converter is implemented on a differential circuit topology (T〇p〇1〇gy). Park contains - the first 3 pairs of i (3_ΐ〇_υ multiplexer, a second (3-to-l) multiplexer, a 2-bit round-in signal and three reference voltages, which: 'The The -3 to 1 (3-t〇-l) multiplexer is used to generate a differential ^ ^ upper forward end 'the second 3 to 1 (3-to-l). multiplexer system Generating a negative signal of one of the differential signals, the input signal of the two bits being used as a selection of the first three-to-one and the second three-pair multiplexer in the first-digital analog converter a line, the three reference voltages are used as input signals of the input ends of the first three-to-one and the second three-to-one-single state. 11. The modulator according to claim 1, The first summing circuit is coupled to the first integrator circuit in a single differential switching capacitor circuit, wherein the single differential switched capacitor circuit includes - coupling to the modulation The first pair of capacitors of the input signal, one coupled One output of the first digital to analog converter of the second capacitor, a feedback capacitor, a differential operational amplifier liters, and a plurality controlled by a clock signal of a plurality of switches. 2712 = Please refer to the modulator described in item i of the patent range, I; the early differential exchange capacitor circuit plus ~, the circuit Ϊ two groups of weights and the system, by setting the Γ-bit combination, and in the circuit The capacitance ratio is achieved. , ^ Early differential exchange capacitor 13 in the multi-element triangular integral 5 Xuan method includes: In the first method, in the modulator to suppress the circuit error group signal to perform a first right, the number includes - The modulated input signal and the -first-feedback signal (9) are grouped to integrate the 5th first intermediate signal to generate a first: a second set of signals is applied - the second weighting is added to the = ft feedback signal (4) including the first-integrated signal and the second detecting the second intervening buckle to generate a fine-grained output of the chopping signal = (4), and extracting the signal from the de-emphasis The operation is to generate a _ and the 欢 氐 施 施 施 施 施 累 累 累 累 累 累 累 累 累 累 累 累 累 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The carry signal is converted into the first feedback signal by the trans-digital analog converter. The method further includes: 14. The method according to claim 13 of the patent application, 28 1355808, _ • . Correction of the replacement page on the 4th. The sum of (N-1) bits is passed through a feedback path. It converts the number into a second feedback signal, wherein the feedback path comprises an (N-1) bit digital converter than class. 15. The method of claim 13, wherein the step of performing an accumulation operation on the (N-1) lower significant bit of the N-bit modulated output signal further comprises: (N-1) a bit adder to add the (N-1) lower significant bit of the N-bit modulated output signal to the sum signal of the (N-1) bit; and delaying the One of the (N-1) bit adders is output to generate the sum signal of the (N-1) bit. The method of claim 13, wherein the second group of signals further comprises a third feedback signal, and the third feedback signal is a digital analog conversion through the N-bit modulated output signal. And produced. 17. The method of claim 13, wherein the step of filtering the second intermediate signal further comprises: integrating the second intermediate signal. 29 1355808 May 4, 100 revised replacement page. 7. Designated representative map: (1) The representative representative of the case is: (2A). (2) A brief description of the symbol of the representative figure: (The representative figure in the present case is a step flow chart, so there is no component representative symbol) 200A: Multi-bit triangular integral modulator 210A: First summing circuit 220: First integrating circuit 230A: second summing circuit 240: filter circuit 250: quantizer 260: second feedback circuit 265: delay circuit 270 · (N-1) bit digital analog converter 275A: differentiator 280: (N-1) Bit adder 290: ternary analog converter 293: 1-bit adder 295A: first feedback circuit X/7): modulation input signal r2 (/?): second intermediate signal /2 (7?) : Filter wave signal y (/7): Ν bit modulation output signal ^ (/7): first feedback signal i 2 (77): second feedback signal < 93 (77): third feedback signal 5 1355808 J * ., , _ May 4, 100 revised replacement page. S [/7): addition signal C (/7): 1-bit carry signal. 5 (77- /): delayed addition signal 32 ( 7?): Analog output 'd(n): ternary signal 8. If there is a chemical formula in this case, please reveal the chemical formula that best shows the characteristics of the invention: