1354364 2011年9月5日修正替換頁 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種多晶片交錯堆疊封裝結構，特別是有關於一種在 導線架之内引腳上配置有轉接焊塾之多晶片交錯堆疊封裝結構。 【先前技術】 近年來，半導體的後段製程都在進行三度空間（ThreeDimensi〇n ; 3D) 的封裝，以期利用最少的面積來達到相對大的半導體集成度（Integrated) 或是記憶體的容量等。為了能達到此一目的，現階段已發展出使用晶片堆 疊（chipstacked)的方式來達成三度空間（ThreeDimensi〇n ; 3D)的封裝。 在習知技術中，晶片的堆疊方式係將複數個晶片相互堆疊於一基板 上，然後使用打線的製程（wire bonding process)來將複數個晶片與基板連 接。第1A圖係習知之具有相同或是相近晶片尺寸之堆疊型晶片封裝結構的 剖面示意圖。如第1A圖所示，習知的堆疊型晶片封裝結構丨⑻包括一電路 基板（packagesubstrate) 110、晶片 120a、晶片 120b、一間隔物（spacer) 130、多條導線140與一封裝勝體（encapSuiant) mo。電路基板no上具有 多個焊墊112，且晶片i20a與120b上亦分別具有多個焊墊122a與122b， 其中;fcp塾122a與122b係以周圍型態(peripheral type)排列於晶片n〇a與120b 上。晶片120a係配置於電路基板11()上，且晶片12〇b經由間隔物13〇而配 置於晶片120a之上方。導線14〇之兩端係經由打線製程而分別連接於焊墊 112與122a ’以使晶片12〇a電性連接於電路基板11〇。而其他部分導線14〇 之兩端亦經由打線製程而分別連接於焊墊112與122b，以使晶片12〇b電性 連接於電路基板110。至於封裝膠體15〇則配置於電路基板110上，並包覆 這些導線140、晶片12〇a與120b。 6 13543.64 2011年9月5日修正替換頁 由於焊墊122a與122b係以周圍型態排列於晶片120a與120b上，因 此晶片120a無法直接承載晶片120b’是以習知技術必須在晶片12加與12〇13 之間配置間隔物130，使得晶片i20a與120b之間相距一適當的距離，以利 後續之打線製程的進行。然而，間隔物13〇的使用卻容易造成習知堆疊型 晶片封裝結構100的厚度無法進一步地縮減。 另外，習知技術提出另一種具有不同晶片尺寸之堆疊型晶片封裝結 構，其剖面示意圖如第1B圖所示β請參考第1B圖，習知的堆疊型晶片封 裝結構10包括一電路基板（package substrate) 11〇、晶片l2〇c、晶片12〇d、 多條導線140與一封裝膠體15〇。電路基板11〇上具有多個焊墊112。晶片 120c之尺寸係大於晶片12〇d之尺寸，且晶片上亦分別具有多 個焊墊mc與md ’其中焊塾既與㈣係以周圍型態咖離㈣咖) 排列於晶片120c與I20d上。晶片120C係配置於電路基板11()上，且晶片 120d配置於晶片120c之上方。部分導線14〇之兩端係經由打線製程（wire bonding process)而分別連接於焊墊112與^，以使晶片i2〇c電性連接 =電路基板110。而其他部分導線14〇之兩端亦經由打線製程而分別連接於 焊墊112與122d，以使晶片電性連接於電路基板UG。至於封裝膠體 15〇則配置於電路基板110上，並包覆這些導線M〇、晶片隱與·。 由於晶片12(Μ小於晶片12〇c，因此當晶片12〇d酉己置於晶片隱上 夺阳片120d*會覆蓋住晶片12〇c之焊塾既。但是當習知技術將多個 不同尺寸大㈣晶W上述的方式堆疊出堆疊型晶片封裝賴⑴時由於 f上層之晶狀寸必須越小，如堆疊型⑼封裝結彳㈣有晶片 垔的限制。 在上述兩種傳_堆疊方式中，除了有第u圖使闕_ 13〇的方 i第封親構⑽的厚找—频_的缺點以 μ 1Β ® 越上層竭尺寸必須越小，如 用時會受侧崎她㈣繼 7 1354364 2011年9月5日修正替換頁 益複雜而使得晶片上的電路連接必須跳線或跨線，進而在製程上產生出的 問題’例如：因為進行封膠（m〇lding)而注入高壓的模流時，可能會造成 這些相互跳線或跨線的金屬導線產生位移而造成短路，使得堆疊型晶片封 裝結構的產能或是可靠度可能會降低。 【發明内容】 有鑒於發明背景中所述之晶片堆疊方式之缺點及問題，本發明提供一 種使用多晶片交錯堆疊的方式，來將複數個尺寸相近似的晶片堆疊成一種 二度空間的封裝結構。 本發明之主要目的在於提供一種在導線架中的内引腳上再配置複數個 金屬焊塾之結構來進行多晶片交錯堆疊封裝之結構，使其藉由增加了内引 腳上配置複數個金屬焊塾之結構而具有較佳的電路設計彈性及較佳的可 靠度。 /夕本發明之另-主要目祕提供—種在導雜巾配置匯雜之結構來進 行多晶片交錯堆疊封裝之結構’使其藉由增加匯流架之結構而具有較佳的 電路設計彈性及較佳的可靠度。 據此，本發明提供一種導線架之内引腳上具有轉接焊墊之堆疊式晶片 封裝結構，包含：一個由複數個相對排列的内引腳群、複數個外引腳群以 及一晶片承座所組成的導線架，其中晶片承座係配置於複數個相對排列的 ^引腳群之間’且與複數個相對制_引腳群形成-高度差；—多晶片 父錯堆疊結構，係、由複數個晶片堆疊而成，多晶片交錯堆疊結構配置^曰 片承座上且與複數個相對排列的内引腳群形成電性連接；以及一封装體曰，曰 包覆多晶片交錯堆疊結構及導線架並將複數個外引腳群係伸出於該封 外’，、特徵在於導線架中的内引腳更被覆—絕緣層且絕緣層 ^ 形成複數個金屬_。 史弹性地 8 1354364 2011年9月5日修正替換頁 本發明接著提供-種㈣腳上具有轉接之導驗結構，由複數個 呈相對排列的㈣腳群、複數個外引腳群以及—晶片承座所組成，晶片承 座配置於複數個相對排列的内引聊群之間且與該複數個相對排列的内引腳 群形成-高度差，其特徵在於㈣腳局部被覆—絕緣層且簡緣層上選擇 性地形成複數個金屬銲墊。 本發明接著再提供-種導線钱構，係由複數個㈣贿複數個外引 腳所構成’内引腳包括有複數個平行之第一内引腳群與平行之第二内引腳 群，第-内引腳群與第二内引腳群之末端係以__間隔相對排列之，第一内 引腳群具有-沉置結構而形成第—内引腳群之末端位置與第二内引腳群之 末端位置具有不同之垂直高度，其特徵在於第—内引腳群或第二内引腳群 或是該第-㈣聊群與第二㈣腳群等之末_近處，局部賊一絕緣層 且該絕緣層上選擇性地形成複數個金屬銲墊。 【實施方式】 本發明在此峨討的方向為—種個“交錯量堆㈣方式，來將複 相近似的晶牌疊成—種三度空間的封裝結構。為了能徹底地瞭 ”明，將在下列_述巾提鱗盡的倾及其域^顯舰，本發明 的施行並未限定晶片堆疊的方式之技藝者所熟f的特殊細節。另一方面， 知的“形成方式以及^雜㈣段餘之詳”魅未描述於 二㈣，㈣免錢本發料必要之關。細，對於本發_較佳實施 則《雜描述如下，⑼除了這些詳細描述之外，本發明還可以廣泛 在其他的實施例中，且本發明的綱不受岐，其以之後的專利範 在現代的料體封裝製財，均是將—個已經完成前段製程听⑽咖 ⑽）之晶圓（wafer)先進行薄化處理（施ningPr_s)，將 1354364 2011年9月5日修正替換頁 度研磨至2〜20 mil之間；然後’再塗佈（coating)或網印（pricing) 一層 咼分子（polymer)材料於晶片的背面，此高分子材料可以是一種樹脂 (resine) ’特別是一種B-Stage樹脂。再經由一個洪烤或是照光製程，使得 向分子材料呈現一種具有黏稠度的半固化勝；再接著，將一個可以移除的 膠帶（tape)貼附於半固化狀的高分子材料上；然後，進行晶圓的切割（sawing process)，使晶圓成為一顆顆的晶片（die);最後，就可將一顆顆的晶片與 基板連接並且將晶片形成堆疊晶片結構。 如參考第2A圖及第2B圖所示，係一完成前述製程之晶片2〇〇之平面 示意圖及剖面示意圖。如第2A圖所示，晶片200具有一主動面21〇及一相 對主動面之背面220 ’且晶片背面220上已形成一黏著層23〇;在此要強調， 本發明之黏著層230並未限定為前述之半固化膠，此黏著層23〇之目的在 與導線架或是晶片形成接合，因此，只要是具有此—功能之黏著材料，均 為本發明之貫施態樣，例如：膠膜（die attache(j fiim)。此外，在本發明之 實施例中，晶片200的主動面210上配置有複數個焊墊24〇，且複數個焊墊 240已配置於晶片200的一側邊上，而另一晶片2〇的主動面训上的複數 個焊墊240配置在另-側邊上，在此強調，晶片2〇與晶片2〇〇上的複數個 焊墊240是配置在相對的一側邊上，請參考帛2C _及第2d圖所示。因此， 可以形成-種多晶>}交錯堆疊結構％，如第π崎示^而在形成本發明之 多晶片交錯堆疊的結構3G時’細所要堆疊的晶#數量為依據，來決定每 -晶片交錯堆疊的重疊面積，例如，最下層的兩晶片2〇a及施以黏著層 230來接合時’晶片施交互覆蓋晶片2〇a大於一半以上的面積；而當晶 片20b父互覆蓋於晶片鳥上時，其覆蓋於晶片2〇〇a的面細大於晶片 施覆，晶片20a的面積，且愈上層的晶片交互覆蓋下層晶片的面積愈曰^ 同時晶片以焊線接合區25〇之邊緣線為對準線來形成，因此可 以在此多晶#交錯堆疊結構的兩側邊形賴似階梯狀之結構，使得配置在 片的焊墊均未被上層之晶片所覆蓋或遮蔽。此外，要強調的是，邊緣 10 13543.64 線挪實際上是不存在晶片上，其僅•參考 =〇:广〇或晶片200之尺寸約為】一3—，而晶片2〇或 之黏著層230的厚度約為60um，而承載多晶片交錯堆疊結構 的土板厚度約為2_m至25Gum ;故依上述晶片之尺寸結構，本發明之交 錯堆疊結構完成堆疊後的最大堆疊展職度（Gverhang) ·以6層晶片 約為1咖；以8層晶片為例則會小於。再次要強調的是對於上述 形成多晶片交錯堆疊的結構之晶片的數量及其尺寸大小，本發明並未加以 限制，只要能符合上述綱之可形❹晶片交錯堆疊的結構，均為本發明 之實施祕’例如2層晶片之交錯堆疊結構或是4層晶片之交錯堆疊結構。 接者說明本發明在晶片20或晶片2⑻上配置複數個焊塾之另一實施 例’在本實施例中係使用一種重配置層（Redistribmi〇n⑽；祗）來將 晶片上的焊墊配置到晶片的一側邊上，以便能形成多晶片交錯堆疊的結 構，而此重配置線路層之實施方式說明如下。 月，考第3A〜3C ’係為本發明之具有重配置線路層之晶片結構的製 過私不意圖。如第3A圖所示，首先提供晶片本體训，紅在鄰近於晶 片本體310之單一側邊規劃出焊線接合區320，並將晶片本體31〇之主動: 面上的夕個焊塾312區分為第—料312a以及第二料312b，其中第一谭 塾312'係4立於焊線接合區32〇内，而第二焊塾迎則位於焊線接合區汹 外。接著明參考第3B B，於晶片本體31〇上形成第一保護層33〇，其中第 保。蒦層330具有多個第一開口 332，以曝露出第一焊塾3以與第二焊塾 312b。紐在第―保護層33()上職纽置祕層34q。而重配置線路層 34〇包括夕條導線342與多個第三焊塾Μ4，其中第王㈣344係位於鲜線 接合區32〇 0 ’且這些導線M2係分別從第二焊塾遍延伸至第三焊塾 344以使第一焊墊312b電性連接於第三焊塾344。此外，重配置線路層 34〇的材料可以為金、銅、錦鈦化鎢鈦或其它的導電材料。再請參考 第3C圊’在形成重配置線路層34〇後，將第二保護層35〇覆蓋於重配置線 1354364 2011年9月5日修正替換頁 路層340上，而形成晶片300之結構，其中第二保護層35〇具有多個第二 開口 352 ’以暴露出第一焊墊312a與第三焊墊344 » 要強調的是，雖然上述之第-焊塾312a與第二焊塾迎係以周圍型 態排列於晶片本體31〇之主動表面上，然而第一焊塾312a與第二焊塾 亦可以經由面陣列型態(area array type)或其它的型態排列於晶片本體3i〇 上，當然第二焊塾312b亦是經由導線342 *電性連接於第三焊墊344。另 外’本實施例亦不限定第三焊塾344的排列方式，雖然在第3B圖中第三焊 墊344與第-焊塾312a係排列成關，並且沿著晶片本體之單一側邊 排列，但是第三焊塾3料與第-焊塾312a亦可以以單列、多歹或是其它的 方式排列於焊線接合區320内。 請繼續參考第4A圓與第犯圖，係為第冗圖中分別沿剖面線A_A，與 B-B，所繪示之剖面示意圖。由上述第3圖可知晶片3⑻主要包括晶片本體 310以及重配置層4〇〇所組成，其中重配置層働係由第—保護層33〇、重 配置線路層340與第二保護層35〇所形成。晶片本體3⑴具有焊線接合區 320，且焊線接合區32〇係鄰近於晶片本體31〇之單一側邊。另外，晶片本 體310具有多個第一焊墊312a以及第二焊墊312b，其中第一焊墊Mb位 於焊線接合區320内，且第二焊墊312b位於焊線接合區32〇外。 第-保護層330配置於晶片本體310上’其中第一保護層33〇具有多 個第開〇 332 ’以暴露出這些第一焊塾312a與第二谭塾312b。重配置線 路層340配置於第一保護層33〇上，其中重配置線路層34〇從第二焊墊31处 延伸至銲線接合區320内，且重配置線路層34〇具有多個第三焊墊344，其 配置於焊線接合區32G内。第二保護層350覆蓋於重配置線路層34〇上， 其中第二保護層350具有多個第二開口 352，以暴露出這些第一焊墊 與第三焊墊344。由於第-焊塾312a與第三焊塾344均位於焊線接合區32〇 内，因此第二保護層350上之焊線接合區32〇以外之區域便能夠提供一個 12 13543.64 2. ^ . 2011年9月5曰修正替換頁 •。，財載另-個晶#結構，因此，可以形成 疊的結構30。 夕曰日乃父錯堆 心考第5圖所不’穌發明之__種多晶片交錯堆疊的結構％。多晶 =父錯堆疊結構50係由複數個晶請堆叠而成，例如由4個晶片交錯堆 ^其ΐΓ"ί片上具有重配置層4GG，故可將晶片上的焊塾312b配置於 合區32G之上，而爾日日日片_4轉5心由於多晶片 111 it 5〇 30 "卜’械多晶片交錯堆4結構％之個晶片5GG之間係以一 1•八 子材料所形成之黏著層23〇來連接。 ’、阿刀 ，瓣4嶋了嫩娜卜，^交錯堆疊 、.:構30及50，也可將晶片20與具有重配置層之晶片500交互堆疊以 =成另-種多W交錯堆疊結構7G，如第6圖所示，其由6個晶片交錯堆 及由Γ多晶片交錯堆疊結構70之堆疊方式與形成多晶片交錯^疊 ;。構3〇及5〇的堆疊方式相同’在此不再贅述。然而要強調的是本實施 ^並^限定⑸2〇與晶片5〇〇何者在上層何者在下層，本發明並未加以限 只要是以晶片2〇或晶片2〇0與晶片500來形成本發明之多晶片交錯 隹^結構，均為本發明之實施態樣。同時，也要再次要強調，對於上辦 ^晶片:她構之晶織量’本發明並未加以_，例如㈣ ^所不，其由8個晶片交錯堆疊而成；第5 _示，其由4個晶片交錯堆 第6圖所示，其由6個晶片交錯堆疊而成；當然也能有其他的租 發明能符合上述說明之可形成多晶片交錯堆4的結構，均為本 接著，本發明依據上述之多晶片交錯堆疊結構3〇、5〇及％ 種堆疊式晶片封I結構，並且詳細說明如下。同時，在如下之說 將以多晶片交錯堆疊結構5〇為實施例，然而要強調的是，多晶片錯王堆属 13 1354364 2011年9月5曰修正替換頁 結構30及70亦適用本實施例所揭露之内容。 首先，請參考第7圖，縣發明之堆疊式晶㈣裝結構之平面示意圖。 如第7圖所示’堆疊式晶片封裝結構魏括導線架6()及多晶片交錯堆疊結 構50A所組成，其中導線㈣係由複數個成相對排列的㈣腳群_、複 數個外引腳群（未標示於圖上）以及—晶片承座伽所組成，其中晶片承 座62(M系配置於複數個相對排列的内引腳群61〇之間，同 列的内引腳群⑽與晶料座62〇也可以形成一高度差。在本實施例中， 多晶片交錯堆疊結構50A係配置在晶片承座62〇之上並藉由一黏著層23〇 固接多晶片交錯堆疊結構50A與晶片承座62〇;此黏著層23〇未限定為前述 之半固化膠〃要疋具有此一功能之黏著材料，均為本發明之實施態樣， 例勝膜（dle attached film)。然後，再經由複數條金屬導線64〇將多晶 片父錯堆疊結構50A與導線架6〇之内引腳群⑽連接。此外，在晶片观 的焊線接合區裡轉墊可以是單列排列（如第2A圖所示），也可以是雙列 排列（如帛3B圖或3C圓所示），本發明並未限制。 繼續請參考第7圓，在本發明之堆疊式晶片封裝結構之導線架6〇中， 為了使導雜60麟提做多的雜接點，以作為電源接點、接地接點 或訊號接點之電性連接，在本發明中的内引腳_的局部位置上更進一步 置，.邑緣層61卜並且在絕緣層611上再配置至少一金屬焊塾6⑴如此 來使得内引腳610上多了許多的轉接焊塾（即金屬谭塾613)，故可以 提供電路設計上更多的彈性及應用。 此外，就上述之絕緣層611而言，其可利用塗佈（咖或是網印 (printing) -高分子材料來形成，例如：聚亞酿胺㈣如啦叩或是使 用黏貼（戯hing)的方式來職，例如使_帶（此咖咖。而金 屬谭墊613則可利用電鑛（plating)製程或是钱刻⑽㈣）製程，將一金 屬層（即金屬焊塾613)形成在絕緣層611之上。在此要強調，本發明之絕 13543.64 2011年9月5日修正替換頁 緣層611可以是配置在整個内⑽61〇或是局部的内引腳⑽之上，錢也 可以使用多段方式形成在㈣腳61G之上，本發明也未加以限制^外， 本發明亦可以在金屬焊塾613上再形成-絕緣層611並且再於此絕緣層6ιι 上再-次的形成金屬焊塾613，如此可使得㈣腳⑽上再多了許多的轉接 焊墊。 接著說明本發明使用内引腳61〇上的金屬焊塾來達成金屬導線64〇跳 線連接的過程，請再參考第7圖。第7圖顯示將下層晶片與晶片5〇〇上的 焊塾b⑽及焊墊c (〇與内引腳_ (6123)及内引腳㈣⑽2) 連接之示意圖。很明顯地’本實施例可以利用内引腳61〇上的複數個金屬 焊塾613作為轉接點來達到將焊堅b(b，）及焊墊c(〇與内引腳細(6123) 及内引腳6102 (6122)跳線連接，而不會產生金屬導線64〇相互跨越的情 形。例如，以-條金屬導線64〇將晶片5⑽上的焊墊b先連接到内引腳 6102上的金屬焊塾613 ± ’然後再以另一條金屬導線_將内引腳_上 的金屬焊塾613與内引腳娜連接。因此，可以達到將焊塾b與内引腳細 完成連接’而避免將焊塾b直接與㈣腳刪連接時所必須跨越另一條連 接焊墊c及内引腳6102的金屬導線640。然後，進行將焊墊a與内引腳61〇1 以一條金屬導線640連接，再將晶片500上的焊墊c先連接到匯流架61〇2 上，接著再以另一條金屬導線640將焊墊d連接到匯流架61〇4上。因此， 可以達到將焊墊b與内引腳6103完成連接的過程中，避免跨越另一條連接 ¥塾c及内引腳6102的金屬導線640。而在另一側邊的焊塾b，及焊塾c，與 内引腳6123及内引腳6122跳線連接過程也是使用相同過程完成連接，因 此在完成焊墊b，及焊墊c’與内引腳6123及内引腳6122的連接後，也不會 產生金屬導線640相互跨越的情形。 繼續請參考第8A圖及第8B圖，在本發明之交錯堆疊式晶片封裝結構 之導線架600中，更進一步包括至少一個匯流架63〇 (busbar)配置於晶片 承座620與複數個相對排列的内引腳群61〇之間，其中匯流架63〇可以採 1354364 2011年9月5日修正替換頁 用條狀配置’如第8A圖及第8B圖所示；同時匯流架63〇也可以採用環狀 配置（未顯示於圖中）。此外，如前所述，在晶片5〇〇的焊線接合區裡的焊 墊可以是單列排列，也可以是雙列排列，本發明並未限制。 接著說明本發明使用匯流架630及内引腳610來達成金屬導線64〇跳 線連接的過程，請再參考第8A圖。第8A圖顯示一個將晶片5〇〇上的焊墊 與匯流架630及内引腳群610連接之示意圖。很明顯地，本實施例可以利 用匯流架6301及匯流架6302作為接地之轉接點，將焊墊3及焊墊a，與内引 腳6101及内引腳6121連接；接著，將下層晶片與晶片5〇〇上的焊墊c(c，） 及焊墊d (d，）與内引腳6101 (6121)及内引腳6103 (6123)連接之示意 圖。很明顯地，本實施例可先選擇以一條金屬導線64〇將晶片上的焊墊c 及焊墊c’先連接到内引腳6102上的金屬焊墊6131及内引腳6122上的金屬 焊墊6132上，然後再以另一條金屬導線64〇將金屬焊墊6131及金屬焊墊 6132與内引腳6101及内引腳6121連接；接著，將焊墊d及焊墊d，先連接 到内引腳6103上的金屬焊堅6133及内引腳6123上的金屬焊墊6134上， 然後再以另-條金屬導線640將金屬焊塾6133及金屬焊塾6134與内引腳 6104及内引腳6124連接。因此，可以達到將 c及焊塾c，與内引腳6ι〇ι 及内引腳6121完成連接的過程中，避免將焊塾c (c，）直接與内引腳鑛 (6121)連接時’所必須跨越另一條連接谭塾b (b，）及内引腳(6⑵） 的金屬導線640;同時，在到將焊塾d及焊塾d，與内引腳61〇4及内引腳隨 完成連接時，避紐焊墊d (d，）直接與㈣腳刪（6124)連接時，所必 須跨越另-條連接焊墊e(e’）及内引腳61〇3 (6123)的金屬導線_。 而在另-實施例中’如第8B圖所示，係使用多條匯流架63〇的結構來 達成跳線連接之示思圖。在第8B圖即是顯示一個將晶片$⑻上的焊塾。 ()焊墊d(d)及焊墊e(e，）與内引腳61()1(6⑵）、内引腳⑽4(6以） 及内引腳6103 (6123)連接之示意圖，其中焊墊&及焊塾&，與匯流架㈣】 及匯机架63G2連接’以作為接地轉接點連接,腦地，本實施例可以利 1354364 2011年9月5曰修正替換頁 用匯流架6301及匯流架6302作為接地轉接點，並利用匯流架6305及匯流 架6304作為訊號之轉接點。例如’先以一條金屬導線64〇將晶片5〇〇上的 焊塾c及焊墊c’先連接到内引腳6102上的金屬焊墊6131及内引腳6122上 的金屬焊墊6132上，然後再以另一條金屬導線64〇將金屬焊墊6131及金 屬焊墊613與内引腳6101及内引腳6121連接；另外，將焊塾d及焊塾d， 先連接到内引腳6103上的金屬焊墊6133及内引腳6123上的金屬焊墊6134 上，然後再以另一條金屬導線640將金屬焊墊6133及金屬焊墊6134與内 引腳6104及内引腳6124連接；再接著，將焊墊e及焊墊e，先連接到匯流架 6305及匯流架6304上，然後再以另一條金屬導線64〇將匯流架63〇5及匯 流架6304與内引腳6103及内引腳6123連接。因此，可以達到將焊墊c及 焊墊c’與内引腳6101及内引腳6121完成連接，而避免將焊墊c (c，）直接 與内引腳6101 (6121)連接時，所必須跨越另一條連接焊墊1> (b，）及内引 腳6102 (6122)的金屬導線640;而在將焊墊d及焊墊d，與内引腳61〇4及 内引腳6124完成連接’而避免將焊墊d(d，）直接與内引腳61〇4(6124) 連接時，所必須跨越另-條連接焊塾e (e，）及内引腳刪（6123)的金屬 導線640。 因此，本發明之藉由導線架600中的内引腳上的金屬焊塾613 (即 6131〜6134)及匯流架630 (即6301、6302、6304、6305)來作為多個轉接 點之結構，使得在進行電路連接而必須跳線連接時，可以避免金屬導線的 交錯跨越，而造成不必要的短路，使得封裝完成的晶片產生可靠度的問題， 也可使得電路設計時可以更彈性。 接著，請參考第SC圖及第圖所示，係本發明之堆疊式晶片封裝結 構之另-實施例之平面示意圖。如第8C圖及第8B圖所示，堆疊式晶片^ 裝結構係包括導線架600及多晶片交錯堆疊結構5〇所組成，其中導線架咖 係由複數個成相對排列的内引腳群610、複數個外引腳群（未標示於圖上） 以及-晶片承座62。所組成，其片承座62。係配置於複J個相對排列 1354364 2011年9月5日修正替換頁 的内引腳群610之間，同時複數個相對排列的内引腳群61〇與晶片承座62〇 之間也可以形成一高度差或是形成一共平面。在本實施例中，更為了使導 線架600能夠提供更多的電性接點，以作為電源接點、接地接點或訊號接 點之電性連接’故在内引腳群61〇的局部位置上更進一步配置一絕緣層611 並且在絕緣層611上再配置至少一個金屬焊塾613。如此一來，使得内引腳 610上多了許多的轉接焊墊613，故可以提供電路設計上更多的彈性及應 用。此外，在本實施例中，導線架6〇〇更進一步包括至少一個匯流架63〇 (bus bar)配置於晶片承座62〇與複數個相對排列的内引腳群61〇之間其 中匯流架630可以採用至少-條狀配置，而每一條狀配置之匯流架63〇係 以多個的金屬片段（即鑛、63G2、63G3、6304、63G5、6306)所形成， 如第8C圖及第8D圖所示；js]時匯流架63〇也可以採用環狀配置，並且每 -%狀配置之匯流架630也是以多個的金屬片段來形成，本發明並未加以 限制。此外，如前所述，在晶片5〇〇的焊線接合區裡的焊墊312/344可以是 單列排列，也可以是雙列排列，本發明也並未限制。另外，由於本發明的 匯流架630均是以多個的金屬片段（例如：63〇1〜63〇6)來形成，因此每個 金屬片段均各自獨立’使得導驗_無形巾增加了料金W段所形成 之匯流架630 ’而這些金屬片段則可用以作為電源接點、接地接點或訊號 接點之電性連接，故可更以進—步提供電路設計上更多的彈性及應用。 …接著說明本發明使用匯流架63〇來達成金屬導線64〇跳線連接的過 程’凊再參考帛8C ®。第8C ®顯示一個將多晶片交錯堆疊結構5〇上的焊 塾與導線架之㈣腳連接之示意圖。很_地，本實施例係湘内引腳群 ⑽上的金屬焊墊犯以及形成匯流架MO之複數個金屬4段（例如： 6301〜63〇6)作為轉接點，用來達到將焊墊a (a，）至焊墊f(f，）與内引腳 61〇1 (6叫至㈣腳祕（6125)跳線連接，而不會產生金屬導線_ 相互跨越的情形。例如，先以一條金屬導線64〇將多晶片交錯堆疊結構5〇 上的焊塾a先連接到匯流架㈣之金屬片段鑛，而此金屬片段鑛係作 18 1354364 2011年9月5日修正替換頁 為一接地連接點’·接著將焊墊b直接連接到内引腳61〇2 ;然後以一條金屬 導線640將多晶片交錯堆疊結構50上的焊塾c先連接到匯流架63〇之金屬 片段6303，然後再以另一條金屬導線540將匯流架63〇之金屬片段63〇3與 内引腳6103連接；接著，以一條金屬導線64〇將晶片5〇〇上的焊先連 接到内引腳6102上的金屬_ 6131上，然後再以另一條金屬導線64〇將 金屬焊墊6131與内引腳6101連接。因此，當焊墊c及焊墊d與内引腳61〇3 及内引腳6101完成連接時，即可避免將連接焊與内引腳61〇3的金屬導 線640與焊墊d及内引腳6101的金屬導線64〇間的相互跨越。然後，進行 將焊墊e與内引腳6105的跳線連接，先以一條金屬導線64〇將多晶片交錯 堆疊結構50上的焊墊e先連接到匯流架63〇之金屬片段63〇5，然後再以另 一條金屬導線640將匯流架630之金屬片段6305與内引腳6105連接。因 此’當焊墊e與内引腳61〇5完成連接時，即可避免連接焊墊e與内引腳61〇5 的金屬導線640必須跨越另一條連接焊墊f及内引腳61〇4的金屬導線64〇。 而在另-側邊的焊墊a，至烊塾f與内引腳6121至内引腳6125的配置與前 述相同，故其跳線連接過程也與前述相同，故不再贅述。因此在完成焊墊a， 至焊塾f’與内引腳6121至内引腳6125的連接後，也不會產生金屬導線64〇 相互跨越的情形β 而在另一實施例中，當多晶片交錯堆疊結構50上有多個焊墊必須要進 行跳線連接時，即可使用多條匯流架630的結構來達成，如第8C圖所示。 第8C圖也是顯示一個將多晶片交錯堆疊結構5〇上的焊墊與内引腳連接之 示意圖。很明顯地’在本實施例中，也是使用内引腳群61〇上配置絕緣層 611並且在絕緣層611上再配置至少一個金屬焊塾613，以及配合由複數個 金屬片段（例如：_〜〇)所形成之匯流架63〇來作為轉接點，用來 達到將焊塾（a/a，〜f/f，）與内引腳610跳線連接，而不會產生金屬導線64〇 相互跨越的情形。例如’先以一條金屬導線640將多晶片交錯堆疊結構5〇 上的焊墊a或a，絲接到匯贿630上的金屬片段_或鑛，而此金屬 19 1354364 2011年9月5曰修正替換頁 片段6305或6306係作為一接地連接點；然後以一條金屬導線64〇將多晶 片交錯堆疊結構50上的焊墊b或b，先直接連接到匯流架63〇之金屬片段 6301或6302上，接著再以另一條金屬導線64〇將匯流架63〇之金屬片段 6301或6302連接到内引腳6102或6122上的金屬焊墊6131或6132上然 後再以另一條金屬導線640將金屬焊墊6131與内引腳6101連接到内引腳 6104或6124上。然後，以一條金屬導線64〇將多晶片交錯堆疊結構5〇上 的焊墊d或d’先直接連接到内引腳61〇3或6123上的金屬焊墊6133或6134 上，然後再以另一條金屬導線64〇將金屬焊墊6133或6134與内引腳61〇5 或6125連接。 因此，當焊墊b或b’與内引腳6102或6122以及焊墊d或d，與内引腳 6105或6125完成連接時’即可避免將連接焊墊b或b，與内引腳61〇2或6122 的金屬導線640與連接焊墊d^d，與内引腳㈣5或仍之的金屬導線_ 間的相互跨越。再接魏焊墊e或e，先連接顺流架63()之金則段咖7 或6308上，然後再以另一條金屬導線64〇將匯流架63〇之金屬片段纪町 或6308與内引腳6102或6122完成連接’如此，也可有效地避免將連麟 墊e或e，與内引腳6102或6122的金屬導線64〇跨越另一條連接焊塾f或f, 及内引腳6103或6123的金屬導線640。 因此’本實施例之藉由導線架㈣中的内引腳群61〇上的複數铜金屬 焊墊犯與複數個金屬片段（例如：63〇1〜63〇1〇)所形成之匯流架63〇來 作為多個轉無之職，麵行連接而必須跳線連接時，可以避免金 屬導線較錯跨越’而造成移要聰路，故可以提高封裝晶片的可靠度。 同時，也可使得電路設計時可以更彈性。 又 明參考第9A圖及第9B圖’係本發明之堆疊式晶片封裝結構之再一實 施例之平面示意圖。如第9A圖及第9B圖所示，堆疊式晶片封裝結構係包 括導線架600及多晶片交錯堆疊結構·所組成，其中導線架_係由複 數個成相對排列的内5_61G、複數個利腳群（未標示於圖上）以及一 20 1354364 2011年9月5日修正替換頁 晶片承座620所組成’其中晶片承座62〇係龙置於複數個相對排列的内引 腳群610之間，同時複數個相對排列的内引腳群61〇與晶片承座62〇之間 也可以形成一尚度差。在本實施例中，多晶片交錯堆疊結構5〇〇係配置在 晶片承座620之上，並且經由金屬導線64〇將多晶片交錯堆疊結構5〇〇與 導線架600之内引腳群610連接。 繼續請參考第9A圖及第9B圖，在本發明之堆疊式晶片封裝結構之導 線架600中’内引腳群610上配置一絕緣層611並且在絕緣層611上再配置 至少一個金屬焊墊613 ’如此一來’使得内引腳群61〇上多了許多的轉接焊 墊’故可以提供電路設計上更多的彈性及應用。此外，在本發明中的匯流 架630上更配置一絕緣層632並且在絕緣層632上再配置至少一個金屬焊 墊634，使得匯流架630上也多了許多的轉接焊墊，故可以提供電路設計上 更多的彈性及應用。 要強調的是’匯流架630可以採用條狀配置，如第9A圖及第9B圖所 示；同時匯流架630也可以採用環狀配置（未顯示於圖中），本發明並未限 制。此外，如前所述，在晶片5〇〇的焊線接合區裡的焊塾可以是單列排列， 也可以是雙列排列’本發明也並未限制。 接著說明本實施例使用金屬導線64〇跳線連接的過程，很明顯地本 實施例係利用㈣腳群_上的金屬焊墊613及匯流架_及匯流架罐 上的複數個金屬焊墊634作為轉接點來達到將焊墊a(a，）至焊墊⑽，）與 内引腳6101 (6121)至内引腳61〇5 (6125)跳線連接，而不會產生金屬'導 線640相互跨越的情形。例如，先以一條金屬導線_將多晶片交錯堆疊 結構上^焊塾a先連接龜流㈣G1，而祕流架隨係作為—接地連^ 點；，著將焊塾b直接連接到内引腳缝；然後以—條金屬導線_將多 晶片父錯堆疊結構上的焊塾c先連接到到内引腳缝上的金屬焊塾㈣ 上’然後再以另一條金屬導線64〇將金屬焊塾6131與㈣腳_連接。 21 1354364 因此， 腳 6101 跨越》 也 2011年9月5曰修正替換頁 ^ C與㈣聊6101完成連糾，即可避免將連接焊塾c與内引 的金屬導線64〇與焊墊b及内引腳61〇2的金屬導線柳間的相互 再接著，以一條金屬導線640將多晶片交錯堆疊結構上的焊墊d先連 墙綱 61 齡== 的跳線連接，Γ3細丨腳6104連接；然後，進行將料e與内引腳_5 接到到邮I M—條金屬導線_將多晶片交錯堆疊結構上的焊墊e先連 ==16104上的金屬焊塾6135上，然後再以另一條金屬導線柳 與㈣腳祕連接；最後，進行繼f與㈣腳_3 的跳線連接’先以-條金屬導線柳將多^交錯堆疊結構上的焊墊f先連 1 賴t63G1之金屬焊㈣41，錢再以另—條金斜線_將匯流架 之金屬焊塾634i與内_ 61G3連接。因此，當焊塾d、焊墊e、焊塾 ^與内引腳_、内引腳61〇4、内引腳61〇5完成連接時，即可避免連接焊 塾d⑻與内引腳6104 (娜）的金屬導線64〇必須跨越另一條連接焊塾f 及内引腳6103的金屬導線64〇。而在另一侧邊的焊塾&，至焊塾f，與内引腳 ㈣至内引腳6125 _己置與前述相同，故其跳線連接過程也與前述相同， 故不再贅述。因此在完成輝塾a’至焊W，與内引腳⑽至内引腳㈣的 連接後，也不會產生金屬導線64〇相互跨越的情形。 而在另-實施例中，如第9B圖所示’當晶片5〇〇上有多個焊塾必須要 進行跳線連接時，即可使用多條匯流架63〇的結構來達成。在本實施例中， 内引腳群6U)上均配置有複數的金屬焊塾613並且複數個匯流架63〇上也 配置複數個金屬焊墊634來作為轉接點，其中金屬焊塾613及金屬焊塾伽 與内引腳群⑽及匯流架⑽間係藉由—絕緣層來_ ^於，本實施例 的實際連線及跳線過程與前述之第9A圖相同，故不再贅述。 另外’要再次強調，本發明之多晶片交錯堆疊結構係固接於導線架_ 22 1354364 2011年9月5日修正替換頁 之上，其中多晶片交錯堆疊結構中的複數個晶片5〇〇，其可以是相同尺寸及 相同功能之晶片（例如：記憶體晶片），或是複數個晶片5〇〇中的晶片尺寸 及功能不相同（例如：最上層之晶片是驅動晶片而其他的晶片則是記憶體 晶片）。而對於多晶片交錯堆疊之晶片尺寸或是晶片功能等，並非本發明之 特徵，於此便不再贅述。 接著請參考第10圖，係本發明沿第7圖沿从線段剖面之多晶片交錯 堆疊封裝結構之剖面示意圖。如第10圖所示，導線架600與多晶片交錯堆 疊結構50之間係由複數條金屬導線64〇a、64〇b、64〇c、64〇d來連接，其中 導線架600係由複數個相對排列的内引腳群61 〇、複數個外引腳群（未標示 於圖上）以及-晶片承座62〇所組成，而晶片承座62〇係配置於複數個相 對排列的㈣腳群610之間，且與複數個姆排顺㈣腳群_形成一 高度差。在本實施例中内引腳群61〇上配置一絕緣層611並且在絕緣層6ιι 上再配置至少-個金屬焊塾613。如此一來，使得内引腳群⑽上多了許多 的轉接焊墊’故可以提供電路設計上更麵雜及應用。 如第10圖所示，金屬導線係以打線製程將金屬導線64〇3的一端連接 於晶片5〇〇a之科上，金屬導線64〇a之另一端則連接於晶片結構獅之 焊塾上。接著，將金屬導線祕之一端連接於晶片5_之焊塾上，然後 再將金屬導線640b之另-端連接至晶片5〇〇c之焊塾上。接著再重複金屬導 線織及祕的過程，以金屬導線撕錢來將晶片嫌與晶片删， 以及晶片5〇〇c與晶片腑完成電性連接。再接著，以金屬導線64〇§分別 將晶片50〇a、5〇〇d與導線架600之複數個摘排列的内引腳群61〇(例如： 内引腳61G1或6121)完成電性連接’此—來，經由金屬導線_'祕、 640c及640d #逐層完成連接後，便可以將晶片5〇〇a、獅驗及細 電性連接於導雜_，其中這些金屬魏_的材f可贿用金。 同時’由於本實施例之導線架_之内引腳群61〇上配置有金屬焊塾 23 1354364 201丨年9月5曰修正替換頁 ^可作為包括電源接點、接地接點或訊號接點之轉接焊整。例如， 田金屬焊墊613作為電路連接之訊號轉接點時，故可將金屬導線織的一 端連接於晶片观之焊塾（例如：焊墊b，）上，而金屬導線織之另一 端連接至金屬轉613 (例如：金屬焊塾6132)之上，織再由金屬導線 640f將金屬焊塾6132連接至某一個内引腳（例如：内引腳6⑵）上。故在 s曰片500a的另側邊’則可藉由複數條金屬導線來將晶片(例 如：_a)與内引腳群⑽（例如：内引腳刪）連接。然後將金屬導線 640g的-端連接於晶片·a之焊塾（例如：焊塾b)上而金屬導線6卿 之另-端連接至金屬焊墊613 (例如：金屬焊塾6131)之上，然後再由金 屬導線6.雜將金屑焊塾6131連接至某一個内引腳(例如：内引腳娜） 上。如此，經由金祕塾613之轉接，就不會產生為了跨越其他金屬導線 而使要跨越的金屬導線雜度增加，仙此不但可以增加電路設計或是應 用上的彈性，也可以有效的提高封裝製程的產能及可靠度。 ,另外，還要強調的是，晶片5〇〇b係直接堆疊於晶片500a上，兩者間 係以一南分子材料230作為黏著層來固接在一起，並且晶片5〇〇b是堆疊於 晶片500a之焊線接合H 32〇以外的區域，是以後續之打線製程能夠順利地 進行。此外，本實施例並未限制金屬導線64〇之打線製程，故其也可以選 擇由晶片500f上的焊墊向晶片500a的方向來依序連接，最後再將晶片5〇〇a 與導線架600連接。 接著請參考第11圖，係本發明之多晶片交錯堆疊封裝結構之剖面示意 圖（即第8A圖沿AA線段或第8C圖沿AA線段之剖面示意圖）。如第u 圖所示’導線架600與多晶片交錯堆疊結構50之間係由複數條金屬導線64〇 來連接，其中導線架600係由複數個相對排列的内引腳群61〇、複數個外引 腳群（未標示於圖上）以及一晶片承座620所組成，而晶片承座62〇係配 置於複數個相對排列的内引腳群610之間’且與複數個相對排列的内引腳 群610形成一高度差，以及至少一條匯流架630配置於内引腳群61〇與晶 1354364 2011年9月5日修正替換頁 片承座620之間。在本實施例中的匯流架是與晶片承座62〇成一共平面之 配置。在本實施例中，内引腳群610上配置一絕緣層611並且在絕緣層611 上再配置至少一個金屬焊墊613。 如第11圖所示，金屬導線640係以打線製程將金屬導線的一端連接於 晶片500a之焊墊上，而金屬導線之另一端則連接於晶片結構5〇此之焊墊 上；接著，將金屬導線之一端連接於晶片500b之焊墊上，然後再將金屬導 線之另-端連接至晶片5GGe之焊塾上；接著再重複金屬導線騎程，以金 屬導線來將晶片500c與晶片500d完成電性連接；再接著，以金屬導線_ 將晶片500a與導線架600之複數個相對排列的内引腳群61〇 (例如内引 腳6102或6122)完成電性連接。如此一來，經由金屬導線64〇及織等 逐層完成連接後’便可以將晶片500a、500b、5〇〇c及5〇〇d電性連接於導線 架600 ’其中這些金屬導線64〇的材質可以使用金。 同時，由於本實施例之導線架600除了在内引腳群61〇上配置有複數 個金屬焊墊613外，&置有匯流架63〇，其可作為包括電源接點、接地 接點或訊雜點之紐連接點或是城轉無。例如，以第8c圖為例， 當以匯流架63G作為電路連接之轉接點時，故可將金屬導線條的一端連 接於晶片5GGa之料上，而金料線㈣r另—端連接至匯流架（例如： 匯流架6301)之上，然後再由金屬導線64〇k來將匯流架63〇丨連接至某一 個内引腳（例如：内引腳6123)上。接著，將金屬導線㈣的一端連接於 晶片500a之焊墊上’而金屬導線跑之另一端連接至内引腳上的金屬焊 塾金屬焊墊613 ;然後再以另一條金屬導線64〇n將金屬焊塾613連接至某 一個内引腳（例如：内引腳6121)上。 ” 此外，多晶片交錯堆疊結構50之晶片鳩，其也可再將其上的 個焊塾配置於⑼的另—側邊上。故在晶片鳩的，邊，藉由複數條金 屬導線6吨來將晶片屬上的焊塾連接。接著，以金屬導線織的一端 25 1354364 2011年9月5日修正替換頁 連接於晶片500c之焊墊（例如：焊墊c)上，而金屬導線64〇e之另一端連 接至匯流架（例如：匯流架6302)之上，然後再由金屬導線64沉將匯流架 6302連接至某一個内引腳（例如：内引腳613)上。再接著，將金屬導線 64〇g的一端連接於晶片500b之焊墊上，而金屬導線64〇§之另一端連接至 内引聊613上的金屬焊塾，然後再以另一條金屬導線64他將金屬焊墊犯 連接至某一個内引腳上。 另外，還要強調的是，晶片500b係直接堆疊於晶片遍上，兩者間 係以-高分子材料作為黏著層來固接在一起，並且晶片5_是堆疊於晶片 500a之焊線接合區以外的區域’是以後續之打線製程能夠順利地進行。此 外’本實施例並未關金屬導線_之打線製程，故其也可以選擇由晶片 麵上的焊墊向“施的方向來依序連接，最後再將 架600連接。 ，、导琛 接著請參考第！2圖〜U圖，為沿第SA圖沿从線段或第sc圖沿从 線=剖面示意圖，係'本個之多晶収錯堆叠結構之另—實施例之剖面 :意圖。本發明之第12圖〜14 _上述第u圖之間的差異在於導線架_ 於内引腳群610與晶片承座620之間的幾何位置不相 L例如在本貫_中的第12圖，其匯流架630是與内引腳群_成一共 承庙2置本貫施例中的第13圓，其匯流架630與内引腳群610及晶片 成成—高度差之配置；而在本__ Μ，纽上 形成而匯流架630與内引腳群610與晶片承座伽之間的則 外，導::600:,=也:第12圖〜14圖除了導線架600的結構略有不同 連接過程則相同5〇之間係由複數條金屬導線_來 且打雜程並縣翻之舰，故不再賢述。 再接著請再參考㈣圖，係本發明第8B圖沿助線段或第阳圖沿 26 2011年9月5日修正替換頁 BB線段之再—實施例之剖Φ示意圖。 第15圖與第11圖〜14圖間的差異在 於第15圖中的匯流架630是使用複數個匯流架的結構，而此複數個匯流架 630的配置方式可以是第8B目的條狀配置也可以是的環狀配置本發明 則並未加以限制。同樣的，在本實施例中的匯流架630上也可進一步地以 複數個金屬片段（例如：63G1〜63G1G)來形成。很明顯地，由於匯流架數 量的増加’使得可以作為電性連接的數量也就增加，因此可以使得多晶片 堆疊結構50上的焊墊（312a ; 344)的連接更具彈性，如此，就不會產生為 了跨越其他金屬導線而使要跨越的金屬導線的弧度增加，也因此不但可以 ^加電路設計或是躺上轉性，也可財賴提高封裝製程的產能及可 罪度由於導線架6〇〇與多晶片交錯堆疊結構％之間係由複數條金屬導線 640來連接_則相同，幼線製程並非本發明之舰，故不再贊述。 請參考第16圖〜第19圖，係本發明沿第9a圖沿aa線段剖面之多晶 片父錯隹疊封裝結才冓之剖面示意圖。如帛16圖所示，導線架6〇〇與多晶片 、· a .且、、.0構50之間係由複數條金屬導線640來連接，其中導線架6〇〇係 由，數個相對排列的内引腳群61〇、複數個外引腳群（未標示於圖上）以及 阳片承座620所組成，而晶片承座62G係配置於複數個相對排列的内引 腳群610之間，且與複數個相對排列的内引腳群61〇形成一高度差，以及 至少-條匯流架63G 置於㈣腳群61〇與晶片承座62G之間。在本實施 例中内引腳群610上配置一絕緣層611並且在絕緣層611上再配置至少一個 金屬焊塾613。如此-來，使得内引腳群61〇上多了許多的轉接焊塾，故可 以提供電路設計上更多的彈性及應用。此外，本實施例中的匯流架⑽與 晶片承座62G之間係成—共平面之配置，其中匯流架⑽可以採用條狀配 置’如第9A圖及第9B圖所示；同時匯流架_也可以採用環狀配置（未 顯示於圖_)。此外，為了使導線架_能夠提供更多的電性接點，以作為 電源接點、接地接點或訊號接點之電性連接，在本發明中的匯流架伽 上更配置-絕緣層632並且在絕緣層632上再配置至少—個金屬焊塾伽。 27 1354364 2011年9月5日修正替換頁 如此一來，使得匯流架630上多了許多的轉接焊墊，故可以提供電路設計 上更多的彈性及應用。 如第16圖所示，金屬導線64〇係以打線製程將金屬導線64〇a的一端 連接於晶片500a之第一焊墊312a或第三焊墊344(例如前述第3圖中第一 焊塾312a或第三焊墊344) ’而金屬導線640a之另一端則連接於晶片結構 500b之第一焊墊312a或第三焊墊344 ;接著，將金屬導線640b之一端連接 於晶片500b之第一焊墊312a或第三焊墊344上，然後再將金屬導線6〇〇b 之另一端連接至晶片500c之第一焊墊312a或第三焊墊344上；接著再重複 金屬導線640a及640b的過程，以金屬導線640c來將晶片500c與晶片500d 完成電性連接；再接著，以金屬導線640d將晶片5〇〇3上的焊墊（例如：焊 塾b )與導線架600之複數個相對排列的内引腳群61〇 (例如：内引腳6102 或6122)完成電性連接。如此一來，經由金屬導線640a、640b、640c及640d 等逐層完成連接後，便可以將晶片500a、500b、500c及500d電性連接於導 線架600，其中這些金屬導線64〇的材質可以使用金。 同時’由於本實施例之導線架600除了在内引腳群61〇上配置有複數 個金屬焊墊613外，還在匯流架630上再配置有複數個金屬焊墊634，其可 作為括電源接點、接地接點或訊號接點之電性連接點或是訊號轉接 點。例如，以第9A圖為例，當以匯流架630上的金屬焊墊634作為電路 連接之轉接點時，故可將金屬導線640e的一端連接於晶片500a之焊墊（例 如：焊墊f’）上，而金屬導線64〇e之另一端連接至匯流架（例如：匯流架 6342)之上，然後再由金屬導線640f來將匯流架6342連接至某一個内引腳 (例如：内引腳6123 )上。接著，將金屬導線640g的一端連接於晶片5〇〇a 之烊墊（例如：焊墊c’）上，而金屬導線64〇g之另一端連接至内引腳6122 上的金屬焊塾（例如：金屬焊⑦6132);然後再以另一條金屬導線6·將 金屬焊墊6132連接至某一個内引腳（例如：内引腳6121)上。此外，多晶 片交錯堆疊結構5〇最上層之晶月5〇〇d，其也可再將其上的複數個焊墊配置 1354364 ο ,, , 2011年9月5曰修正替換頁 曰;！的另一側邊上’如第2D及5Β圖所示。故在晶片聰的另一側邊， 則可稭由複歸金屬導線_來將“通上的轉（例如：焊斑 3腳群610 (例如：内引腳_2)連接。接著，以金屬導線640」的-端 =接於晶片·之焊墊（例如：焊塾f)上，而金屬導線_之另一端連 流如匯流架6341)之上，然後再由另—金屬導線雛將匯 M八 接至某一個内引腳（例如：内引腳6103)上。再接著，將金屬 導線_n的-端連接於晶片麵之_ (例如： d)上而金属導 =〇m之另一端連接至内引腳缝上的金屬焊塾(例如:金屬焊墊_; =後再以另-條金屬導線64〇n將金屬焊塾6133連接至某一個 如··内引腳6104)上。 传太路^月第_·!7圖〜19圖’為沿第9A圖沿Μ線段之剖面示意圖’ ^ 之Β曰片乂錯堆疊結構之另一實施例之剖面示意圖。本發明之第 =19圖與上述第16圖之間的差異在於導線架_㈣賊 === "士_ 机架630疋與内引腳群610成-共平面之配置；本實施 ^ ，18圖，其匯_63〇與内引腳群61〇及晶片承座必之間成一高 實施例中的第19圖，其與上述第16圖〜第18圖之間 「& 中内引腳群610與晶片承座620之間為共平面，而 =架㈣與内引腳群⑽與晶片承座62〇之間的則形成一高度差。很明 圖除了導線架_的結構略有不同外，導線架_與多 #峻^·^、。構5G之間係、由複數條金屬導線64G來連接過程則相同，且 打線製程並非本發明之特徵，故不再贅述。 ㈣參考第2〇圖，係本發明第9B圖沿BB線段線段之再一實 Ί 630 :圖第2〇圖與第％圖〜19圖間的差異在於第20圖中的匯 Γ用複數個匯流架的結構，而此複數個匯流架630的配置方式 可以疋心圖的條狀配置，也可以是的環狀配置（未顯示於圖中），本發 00 1354364 2011年9月5曰修正替換頁 明則並未加以限制。很明顯地，由於匯流架數量的增加，使得可以作為電 性連接的數量也就增加，因此可以使得多晶片堆疊結構5〇上的焊墊（3i2a ; 344)的連接更具彈性，如此，就不會產生為了跨越其他金屬導線而使要跨 越的金屬導線的弧度增加，也因此不但可以增加電路設計或是應用上的彈 性，也可以有效的提高封裝製程的產能及可靠度。由於導線架6〇〇與多晶 片交錯堆疊結構50之間係由複數條金屬導線64〇來連接過程則相同，且打 線製程並非本發明之特徵，故不再贅述。 經由以上之說明，本發明中所述之實施例並未限制堆疊晶片5〇〇的數 量，凡热知此項技藝者應可依據上述所揭露之方法，而製作出具有三個以 上之晶片500的堆疊式晶片封裝結構。同時，本發明之多晶片交錯堆疊結 構50的堆疊方向也不限定實施例中所揭露者，其亦可將晶片5〇〇的堆疊方 向以一相對於先前實施例中所揭露之方向進行交錯量的堆疊。由於不同方 向之多晶片交錯堆疊結構（稱為70)之間的晶片接合方式以及多晶片交錯 堆疊結構70與導線架600接合之方式，及使用金屬導線柳連接多晶片^ 錯堆叠結構70與導線架600之方式等等，触先前所述實施姻同，因此 對於多晶片交錯堆疊結構與導線架6〇〇的實施方式，於此便不再贅述。 在此要再強調，在本發明上述的所有實施例中，内引腳群61〇上的絕 緣層611以及匯流架630上的絕緣層632，均可利时佈（c〇ating)或是網 印（printing) —高分子材料來形成，例如：聚亞醯胺②〇lyimide，ρι)，或是 也可以利轉貼（attaching)的^絲形成，例如使轉帶（此 film)。而金屬焊塾613及金屬焊塾634則可利用電鍍（plating)製程或是餘 刻（etching)製程，將一金屬層形成在絕緣層611及絕緣層632之上。在此 要強調，本發明之絕緣層611及絕緣層632可以是配置在整個内引腳61〇 以及匯流架630之上，當純可以以多段方式形成在内引腳61()以及匯流 架630之上，本發明也未加以限制。此外，本發明亦可以在金屬焊墊6ιι 及金屬焊墊634上再形成-絕緣層並且再於此絕緣層上再一次的形成金屬 1354364 LB , 2011年9月5曰修正替換頁 焊塾，如此可錄本發明之導線架上再多了許多的轉接焊塾。 顯然地，依照上面實施财_述，本發明可能有許麵修正企 飾犠财__峨，心_：_述 發_可_泛地在其_實_ +断。上碰為本發明之較佳 實施例而已，並義赚定本發明之申請專利細；凡其它未脱 7示之精神下所完成的等效改變或修飾，均應包含在下述”專利範圍 【圖式簡單說明】 第1A〜1D圖係先前技術之示意圖； 第2A與2C圖係本發明之晶片結構之上視圖； 第2B與2D圖係本發明之晶片結構之剖視圖； 第2E圖係本發明之多晶片交錯堆疊結構之剖視圖； 第3A'3B與3C圖係本發明之重配置層製造過程之示意圖丨 第4A與4B圖係本發明之重配置層中之焊線接合區之剖視圖； 第5與6圖係本發明之具有重配置層之多晶片交錯堆叠結構之剖娜 第7圓係本發明之多晶片交錯堆疊結構封裝之上視圖； 晶片交錯堆疊結構封裝之另一 第8A、8B、8C與8D圖係本發明之多 實施例之上視圖； 視圖 第9A與9B圖係本發明之多晶片交錯堆疊結構封裝之另 實施例之上 第10圖係本發明第7圖之多晶片交錯堆疊結贿裝之剖視圖； 31 1354364 2011年9月5日修正替換頁 第11圖係本發明之多晶片交錯堆疊結構封裝之一實施例之剖視圖； 第12圖係本發明之多晶片交錯堆疊結構封裝之另一實施例之剖視圖； 第13圖係本發明之多阳片父錯堆疊結構之另一實施例之剖視圖； 第14圖係本發明之多晶片交錯堆疊結構之另一實施例之剖視圖； 第15圖係本發明之多晶片交錯堆疊結構之另一實施例之剖視圖； 第16圖係本發明之多晶片交錯堆疊結構之另一實施例之剖視圖； 第17圖係本發明之多晶片交錯堆疊結構之另一實施例之剖視圖； 第18圖係本發明之多晶片交錯堆疊結構之另_實施例之剖視圖； 第19圖係本發明之多晶片交錯堆疊結構之另一實施例之剖視圖；及 第20圖係本發日月之多晶片交錯堆疊結構之另一實施例之剖視圖。 【主要元件符號說明】 10、100、400 :堆疊型晶片封裝結構 110、410:電路基板 112、122a、122b、122c、122d :焊墊 120a、120b、120c、120d :晶片 130 :間隔物 140、242、420、420a、420b :導線 150、430 ··封裝膠體 200 :晶片 210 .晶片主動面 220 :晶片背面 230 :黏著層 32 1354364 2011年9月5日修正替換頁 240 :焊墊 250 :焊線接合區 260 :焊線區邊緣 30 :多晶片交錯堆疊結構 310 :晶片本體 312a :第一焊墊 312b :第二焊墊 320 :焊線接合區 330 :第一保護層 332:第一開口 340 :重配置線路層 344 :第三焊墊 350 :第二保護層 352 :第二開口 300 :晶片結構 400 :重配置層 50 :多晶片交錯堆疊結構 500 (a，b,c，d):晶片結構 600 :導線架 610 :内引腳群 6101〜6104 :内引腳 611 :絕緣層 6121〜6124 :内引腳 613 :金屬焊墊 615 :第一内引腳群 616 :第二内引腳群 33 1354364 2011年9月5日修正替換頁 617 :連接部 618 :平台部 620 :晶片承座 630 :匯流架 6301〜63010 :匯流架 632 :絕緣層 634 :金屬焊墊 6341〜6343 :金屬焊墊 640 (a〜η):金屬導線 70 :多晶片交錯堆疊結構 a〜f :焊墊 a’〜f’ ：焊墊 341354364 Modified on September 5, 2011. Illustrated: [Technical Field] The present invention relates to a multi-chip interleaved stacked package structure, and more particularly to a pin disposed on a lead frame Multi-wafer staggered stacked package structure of the solder fillet. [Prior Art] In recent years, the semiconductor back-end process is being packaged in a three-dimensional space (ThreeDimensi〇n; 3D) in order to achieve a relatively large semiconductor integration (integrated) or memory capacity with a minimum area. . In order to achieve this goal, a chip-stacked approach has been developed to achieve a three-dimensional (Three Dimensi〇n; 3D) package. In the prior art, a wafer is stacked by stacking a plurality of wafers on a substrate, and then a plurality of wafers are connected to the substrate using a wire bonding process. Fig. 1A is a schematic cross-sectional view showing a conventional stacked wafer package structure having the same or similar wafer size. As shown in FIG. 1A, a conventional stacked chip package structure (8) includes a circuit substrate 110, a wafer 120a, a wafer 120b, a spacer 130, a plurality of wires 140, and a package body ( encapSuiant) mo. The circuit board no has a plurality of pads 112 thereon, and the pads i20a and 120b also have a plurality of pads 122a and 122b, respectively; wherein the fcp塾122a and 122b are arranged in a peripheral type on the wafer n〇a. With 120b on. The wafer 120a is disposed on the circuit substrate 11(), and the wafer 12b is disposed above the wafer 120a via the spacers 13'. Both ends of the wire 14 are connected to the pads 112 and 122a' via the wire bonding process to electrically connect the wafer 12A to the circuit substrate 11A. The other ends of the other wires 14 are also connected to the pads 112 and 122b via a wire bonding process, so that the wafers 12A are electrically connected to the circuit substrate 110. The encapsulant 15 is disposed on the circuit substrate 110 and covers the wires 140 and 12a and 120b. 6 13543. 64. Correction Replacement Page, September 5, 2011 Since the pads 122a and 122b are arranged on the wafers 120a and 120b in a peripheral pattern, the wafer 120a cannot directly carry the wafer 120b'. It is necessary to add 12 to the wafer 12 by conventional techniques. The spacers 130 are disposed between the crucibles 13 such that the wafers i20a and 120b are spaced apart by an appropriate distance to facilitate subsequent wire bonding processes. However, the use of the spacers 13 is likely to cause the thickness of the conventional stacked type package structure 100 to be further reduced. In addition, the conventional technology proposes another stacked chip package structure having different wafer sizes, and the cross-sectional view thereof is as shown in FIG. 1B. Please refer to FIG. 1B. The conventional stacked chip package structure 10 includes a circuit substrate (package). Substrate 11 〇, wafer l2 〇 c, wafer 12 〇 d, a plurality of wires 140 and an encapsulant 15 〇. The circuit board 11 has a plurality of pads 112 thereon. The size of the wafer 120c is larger than the size of the wafer 12〇d, and the wafer also has a plurality of pads mc and md respectively, wherein the soldering pads are arranged on the wafers 120c and I20d, respectively, and (4) are surrounded by a type of coffee (4). . The wafer 120C is disposed on the circuit substrate 11 (), and the wafer 120d is disposed above the wafer 120c. The two ends of the plurality of wires 14 are respectively connected to the pads 112 and 241 via a wire bonding process to electrically connect the chips i2 〇 c to the circuit substrate 110. The other ends of the plurality of wires 14 are also connected to the pads 112 and 122d via a wire bonding process to electrically connect the chip to the circuit substrate UG. As for the encapsulant 15 〇 , it is disposed on the circuit substrate 110 and covers the wires M 〇 and the wafers. Since the wafer 12 (Μ is smaller than the wafer 12〇c, when the wafer 12 is placed on the wafer, the wafer 120d* will cover the solder bumps of the wafer 12〇c. However, when the conventional technology will be different Large size (four) crystal W The above method stacks the stacked chip package lam (1) because the crystal size of the upper layer of f must be smaller, such as the stacked type (9) package 彳 (4) has the limitation of the wafer 。. In addition to the u-th image, the thickness of the _ _ 〇 第 第 第 亲 ( ( 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 μ μ μ 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 缺点 的 的7 1354364 On September 5, 2011, the replacement page was complicated, so that the circuit connections on the wafer had to be jumpered or jumped, which caused problems in the process. For example, high voltage was injected due to encapsulation (m〇lding). During the mold flow, the mutual jump wires or the metal wires across the wires may be displaced to cause a short circuit, so that the productivity or reliability of the stacked chip package structure may be reduced. [Invention] Disadvantages of the wafer stacking method described above The present invention provides a method of stacking a plurality of wafers having similar dimensions by using a multi-stack interleaving stack into a two-degree space package structure. The main object of the present invention is to provide an inner pin in a lead frame. The structure of the plurality of metal soldering fins is further configured to perform the structure of the multi-stack interleaved package, which has better circuit design flexibility and better reliability by increasing the structure of the plurality of metal soldering pads on the inner leads. / 夕 本 发明 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要 主要Accordingly, the present invention provides a stacked chip package structure having an adapter pad on a lead of a lead frame, comprising: a plurality of oppositely arranged inner pin groups, a plurality of An outer lead group and a lead frame composed of a wafer holder, wherein the wafer holder is disposed between a plurality of oppositely arranged groups of pins and is opposed to a plurality of Foot group formation-height difference; multi-chip parent error stacking structure, which is formed by stacking a plurality of wafers, and the multi-wafer staggered stack structure is arranged on the cymbal holder and electrically formed with a plurality of oppositely arranged inner lead groups And a package body, a multi-wafer interleaved stack structure and a lead frame and a plurality of outer pin groups extending out of the package, wherein the inner leads in the lead frame are more covered - Insulating layer and insulating layer ^ forming a plurality of metals _. History of elastic 8 1354364 September 5, 2011 revised replacement page The present invention then provides - (4) a guide structure with transitions on the foot, which are arranged in a plurality of relative arrangements (4) a foot group, a plurality of outer pin groups, and a wafer carrier, the wafer holder being disposed between the plurality of oppositely arranged inner chat groups and forming a height difference from the plurality of oppositely arranged inner pin groups The feature is that (4) the foot partially covers the insulating layer and the plurality of metal pads are selectively formed on the simple layer. The present invention further provides a wire structure, which is composed of a plurality of (four) bribes and a plurality of outer pins. The inner pin includes a plurality of parallel first inner pin groups and a parallel second inner pin group. The ends of the first inner pin group and the second inner pin group are arranged at intervals of __, and the first inner pin group has a sinking structure to form an end position of the first inner pin group and the second inner portion The end positions of the pin groups have different vertical heights, and are characterized by the first inner pin group or the second inner pin group or the end of the first (four) chat group and the second (four) foot group, etc. The thief is an insulating layer and a plurality of metal pads are selectively formed on the insulating layer. [Embodiment] The present invention is in the direction of begging - a kind of "staggered stack (four) mode, to stack the complex phase-approximation crystal card into a three-dimensional space package structure. In order to thoroughly understand, The details of the method of the present invention are not limited to those skilled in the art of wafer stacking. On the other hand, the "formation method and the details of the formation of the miscellaneous (four) paragraphs" are not described in the second (four), (four) the necessary to clear the money. Fine, for the present invention, the preferred description is as follows: (9) In addition to these detailed descriptions, the present invention can be widely applied in other embodiments, and the outline of the present invention is not limited, and the subsequent patents are In the modern material packaging and manufacturing, the wafers that have already completed the front-end process (10) coffee (10) are first thinned (Shi ningPr_s), and the 1354364 revised order page on September 5, 2011 Grinding to between 2 and 20 mils; then 'coating or pricing a layer of a polymer material on the back side of the wafer. The polymer material can be a resin (resine). A B-Stage resin. Then, through a bake or illuminating process, a semi-curing with a viscosity is presented to the molecular material; and then a removable tape is attached to the semi-cured polymer material; The wafer is subjected to a sawing process to make the wafer a single die; finally, the individual wafers are connected to the substrate and the wafer is formed into a stacked wafer structure. As shown in Figs. 2A and 2B, a plan view and a cross-sectional view of the wafer 2 of the above process are completed. As shown in FIG. 2A, the wafer 200 has an active surface 21A and a back surface 220' opposite the active surface, and an adhesive layer 23 is formed on the wafer back surface 220. It is emphasized here that the adhesive layer 230 of the present invention is not It is defined as the aforementioned semi-cured adhesive. The purpose of the adhesive layer 23 is to form a joint with the lead frame or the wafer. Therefore, as long as it has the adhesive material of this function, it is a consistent aspect of the present invention, for example: glue In addition, in the embodiment of the present invention, a plurality of pads 24 are disposed on the active surface 210 of the wafer 200, and a plurality of pads 240 are disposed on one side of the wafer 200. On the other side, the plurality of pads 240 on the active surface of the other wafer are disposed on the other side, and it is emphasized that the plurality of pads 240 on the wafer 2 and the wafer 2 are disposed opposite each other. On one side, please refer to 帛2C _ and 2d. Therefore, it is possible to form a polycrystalline >} staggered stack structure %, such as the π θ ^ , in forming the multi-stack interleaved stack of the present invention The structure of 3G is based on the number of crystals to be stacked, to determine each wafer. The overlapping stacking area, for example, the lowermost two wafers 2〇a and the adhesive layer 230 are applied to bond the wafers to cover the wafer 2〇a more than half of the area; and when the wafers 20b are covered by the wafer birds In the upper case, the surface of the wafer 2〇〇a is thinner than the wafer application, the area of the wafer 20a, and the upper layer of the wafer overlaps the area of the lower layer wafer, and the wafer is bonded to the edge line of the bonding wire 25 It is formed for the alignment line, so that the two sides of the polycrystalline interlaced stacked structure can be formed in a stepped structure, so that the pads disposed on the sheet are not covered or shielded by the wafer of the upper layer. Emphasize that the edge 10 13543. The 64-line shift is actually not present on the wafer, and only • reference = 〇: the size of the wafer or the wafer 200 is about 1-3, and the thickness of the adhesive layer 230 of the wafer 2 or is about 60 um, and the load is large. The thickness of the soil plate of the wafer staggered stack structure is about 2_m to 25Gum; therefore, according to the size structure of the above wafer, the staggered stack structure of the present invention completes the maximum stacking degree after stacking (Gverhang), and the number of chips of 6 layers is about 1 coffee; Taking an 8-layer wafer as an example, it will be smaller. It is again emphasized that the number and size of the wafers for forming the multi-stack staggered stack described above are not limited in the present invention, as long as they conform to the above-described structure of the stackable stack of the shapeable wafers, which are all of the present invention. Implementation of the secret 'for example, a 2-layer wafer staggered stack structure or a 4-layer wafer staggered stack structure. Another embodiment of the present invention for arranging a plurality of solder bumps on wafer 20 or wafer 2 (8) is described in this embodiment using a reconfigurable layer (Redistribmi(n) (10); 祗) to place the pads on the wafer to One side of the wafer is so as to form a multi-wafer interleaved stack structure, and an embodiment of the re-distribution circuit layer is described below. In the month, the test 3A to 3C' is a system for the reconfiguration of the wafer structure having the reconfigured circuit layer. As shown in FIG. 3A, the wafer body is first provided, and the red wire is planned to be adjacent to the single side of the wafer body 310, and the wafer body 31 is separated from the active surface: The first material 312a and the second material 312b, wherein the first tantalum 312' is 4 in the wire bonding zone 32, and the second soldering wire is located outside the wire bonding zone. Next, referring to the third portion BB, a first protective layer 33A is formed on the wafer body 31A, wherein it is guaranteed. The tantalum layer 330 has a plurality of first openings 332 to expose the first solder fillet 3 to the second solder fillet 312b. New Zealand in the first - protective layer 33 () on the job of the secret layer 34q. The reconfigurable circuit layer 34 includes a welcoming wire 342 and a plurality of third dies 4, wherein the wang (4) 344 is located at the fresh wire junction 32 〇 0 ' and the wires M2 extend from the second stencil to the first The third pad 344 is electrically connected to the third pad 344. Further, the material of the reconfigurable wiring layer 34 may be gold, copper, tantalum titanium titanium or other conductive material. Referring to FIG. 3C', after forming the reconfiguration circuit layer 34, the second protective layer 35 is overlaid on the reconfiguration line 1354364 on September 5, 2011 to modify the replacement page layer 340 to form the structure of the wafer 300. The second protective layer 35A has a plurality of second openings 352' to expose the first pads 312a and the third pads 344. » It is emphasized that although the first-weld 312a and the second solder-pad are welcoming The first solder fillet 312a and the second solder fillet may also be arranged on the wafer body 3i via an area array type or other types. Above, of course, the second pad 312b is also electrically connected to the third pad 344 via the wire 342*. In addition, the present embodiment does not limit the arrangement of the third solder pads 344. Although the third pads 344 and the first pads 312a are arranged to be closed in FIG. 3B, and are arranged along a single side of the wafer body, However, the third solder fillet 3 and the first solder fillet 312a may also be arranged in the bonding wire bonding region 320 in a single row, a plurality of turns or other manners. Please refer to the 4A circle and the first map, which are schematic diagrams of the cross-section lines A_A and B-B in the redundant diagram. It can be seen from the above FIG. 3 that the wafer 3 (8) mainly comprises a wafer body 310 and a reconfiguration layer 4, wherein the reconfiguration layer is composed of a first protective layer 33, a reconfigured wiring layer 340 and a second protective layer 35. form. The wafer body 3(1) has a wire bond area 320, and the wire bond area 32 is adjacent to a single side of the wafer body 31. In addition, the wafer body 310 has a plurality of first pads 312a and second pads 312b, wherein the first pads Mb are located in the wire bonding regions 320, and the second pads 312b are located outside the wire bonding regions 32. The first protective layer 330 is disposed on the wafer body 310. The first protective layer 33 has a plurality of opening openings 332' to expose the first solder bumps 312a and the second solder bumps 312b. The reconfiguration wiring layer 340 is disposed on the first protective layer 33A, wherein the reconfiguration wiring layer 34 extends from the second pad 31 into the bonding wire bonding region 320, and the reconfiguration wiring layer 34 has a plurality of third A pad 344 is disposed in the wire bonding region 32G. The second protective layer 350 covers the reconfigured wiring layer 34, wherein the second protective layer 350 has a plurality of second openings 352 to expose the first and third pads 344. Since both the first soldering pad 312a and the third soldering pad 344 are located in the bonding wire bonding region 32A, a region other than the bonding wire bonding region 32 of the second protective layer 350 can provide a 12 13543. 64 2. ^ . September 5, 2011 revised replacement page •. The structure carries another structure, so that a stacked structure 30 can be formed. Xi Xia is the father's fault. The heart of the 5th picture is not the invention of the __ multi-chip staggered stack structure %. The polycrystalline=parent stack structure 50 is formed by stacking a plurality of crystals, for example, four wafers are interleaved and stacked, and the wafer has a reconfigurable layer 4GG, so that the solder pads 312b on the wafer can be disposed in the joint region. On top of 32G, the Japanese and Japanese films _4 to 5 hearts due to the multi-chip 111 it 5〇30 " Bu's multi-chip interstitial stack 4 structure% of the wafer 5GG is formed by a 1⁄8 sub-material The adhesive layer 23 is connected to connect. ', A knife, the flap 4 licked the tender Nab, ^ staggered stacking. : 30 and 50, the wafer 20 can also be stacked alternately with the wafer 500 having the reconfiguration layer to form another multi-W interleaved stack structure 7G. As shown in FIG. 6, it is interleaved by 6 wafers and The stacking manner of the multi-wafer staggered stack structure 70 is formed by interleaving the multi-wafer formation. The stacking manner of 3〇 and 5〇 is the same' and will not be described here. However, it should be emphasized that the present embodiment defines (5) 2〇 and the wafer 5 which are in the upper layer and which is in the lower layer. The present invention is not limited to the formation of the present invention by using the wafer 2 or the wafer 2〇0 and the wafer 500. The multi-wafer interleaving structure is an embodiment of the present invention. At the same time, it is necessary to emphasize again that for the wafers: the crystal weave amount of her structure is not _, for example, (4) ^, it is composed of 8 wafers staggered and stacked; the fifth _ shows that As shown in Fig. 6 of the four wafer interleaving stacks, the six wafers are alternately stacked; of course, there are other constructions that can conform to the above description to form the multi-stack interlace stack 4, which are all in this case. The present invention is based on the above-described multi-wafer staggered stack structure 3〇, 5〇 and % stacked wafer package I structures, and is described in detail below. Meanwhile, in the following, a multi-stack interleaved stacked structure 5 〇 will be taken as an embodiment, however, it is emphasized that the multi-chip Wypo plexus 13 1354364 September 5, 2011, the modified replacement page structures 30 and 70 are also applicable to the present embodiment. The content disclosed in the example. First, please refer to Figure 7, a plan view of the stacked crystal (four) assembly structure of the county invention. As shown in FIG. 7, the stacked chip package structure includes a lead frame 6 () and a multi-stack staggered stack structure 50A, wherein the wire (4) is composed of a plurality of oppositely arranged (four) leg groups _, a plurality of outer pins The group (not shown) and the wafer carrier gamma, wherein the wafer holder 62 (the M system is disposed between the plurality of oppositely arranged inner pin groups 61 ,, the inner pin group (10) and the crystal in the same column A height difference can also be formed in the holder 62. In this embodiment, the multi-stack interleaved stack structure 50A is disposed on the wafer holder 62A and is fixed to the multi-wafer staggered stack structure 50A by an adhesive layer 23 The wafer holder 62 is not limited to the aforementioned semi-cured adhesive, and the adhesive material having such a function is an embodiment of the present invention, and a dle attached film. The multi-chip parent-staggered stack structure 50A is connected to the inner lead group (10) of the lead frame 6A via a plurality of metal wires 64. In addition, the turn pads may be arranged in a single column in the wire bond area of the wafer view (eg, 2A). As shown in the figure), it can also be a double-column arrangement (such as 帛3B diagram) Or the 3C circle), the present invention is not limited. Continue to refer to the 7th circle, in the lead frame 6〇 of the stacked chip package structure of the present invention, in order to make the miscellaneous joints of the conductive line 60, The electrical connection as a power contact, a ground contact or a signal contact is further set at a local position of the inner pin _ in the present invention. The edge layer 61 and the at least one metal pad 6 (1) are disposed on the insulating layer 611. Thus, the inner lead 610 has a large number of adapter pads (ie, metal Tan 613), so that the circuit design can be provided. More flexibility and application. In addition, as for the above-mentioned insulating layer 611, it can be formed by coating (coffee or printing-polymer material), for example, poly-arasamine (four) such as 叩 叩 or use paste (playing hing) The way to work, for example, to make _ belt (this café. And the metal tan pad 613 can use the electroplating process or the money engraving (10) (four)) process, a metal layer (ie metal 塾613) is formed in the insulation Above layer 611. It is emphasized here that the invention is only 13543. 64 On September 5, 2011, the modified replacement margin layer 611 may be disposed over the entire inner (10) 61 〇 or local inner lead (10), and the money may be formed on the (four) foot 61G using a multi-segment method, and the present invention does not. In addition, the present invention can also form an insulating layer 611 on the metal soldering iron 613 and further form a metal soldering 613 on the insulating layer 6 ι, so that the (four) foot (10) can be further increased. Transfer pads. Next, the present invention will be described using the metal pad on the inner lead 61〇 to achieve the metal wire jumper connection. Please refer to FIG. Fig. 7 is a view showing the connection of the lower layer wafer to the pad b (10) and the pad c (〇 and the inner pin _ (6123) and the inner pin (4) (10) 2) on the wafer 5. Obviously, this embodiment can use the plurality of metal soldering fins 613 on the inner lead 61 作为 as the transfer point to achieve the soldering b (b,) and the solder pad c (the 〇 and the inner pins are thin (6123)) And the inner pin 6102 (6122) jumper connection, and does not cause the metal wires 64 to cross each other. For example, the pad b on the wafer 5 (10) is first connected to the inner pin 6102 by a metal wire 64? The metal soldering iron 613 ± 'and then the other metal wire _ the metal solder 613 on the inner pin _ is connected to the inner pin Na. Therefore, it can be achieved that the soldering b is finely connected to the inner pin' To avoid connecting the solder bump b directly to the (four) leg, it is necessary to cross the other metal wire 640 connecting the pad c and the inner pin 6102. Then, the pad a and the inner pin 61〇1 are made as a metal wire 640. Connecting, the pad c on the wafer 500 is first connected to the bus bar 61〇2, and then the pad d is connected to the bus bar 61〇4 by another metal wire 640. Therefore, the pad b can be achieved. In the process of completing the connection with the internal pin 6103, avoid crossing the metal guide of the other connection pin 塾c and the inner pin 6102 640. On the other side of the soldering b, and soldering c, and the internal pin 6123 and the internal pin 6122 jumper connection process is also completed using the same process, so in the completion of the pad b, and the pad c 'After the connection with the inner pin 6123 and the inner pin 6122, the metal wires 640 do not cross each other. Continuing to refer to FIGS. 8A and 8B, the wires of the staggered stacked chip package structure of the present invention. The rack 600 further includes at least one bus bar 63 busbar disposed between the wafer holder 620 and a plurality of oppositely arranged inner pin groups 61〇, wherein the bus bar 63〇 can be used 1354364 September 5, 2011 The daily correction replacement page is arranged in a strip configuration as shown in Figs. 8A and 8B; and the bus bar 63〇 can also be in a ring configuration (not shown). Further, as described above, on the wafer 5〇 The solder pads in the bond wire bonding area of the germanium may be arranged in a single column or in a double column arrangement, which is not limited by the present invention. Next, the present invention uses the bus bar 630 and the inner lead 610 to achieve a metal wire 64 jumper connection. Please refer to Figure 8A for the process. Figure 8A shows A schematic diagram showing the connection of the pads on the wafer 5 to the bus bar 630 and the inner pin group 610. Obviously, in this embodiment, the bus bar 6301 and the bus bar 6302 can be used as grounding points for soldering. The pad 3 and the pad a are connected to the inner lead 6101 and the inner lead 6121; then, the lower pad and the pad c(c,) and the pad d (d,) and the inner lead on the wafer 5 are connected. 6101 (6121) and the internal pin 6103 (6123) connection diagram. Obviously, this embodiment can first select a metal wire 64 〇 to connect the pad c and the pad c' on the wafer to the inner pin first. The metal pad 6131 on the 6102 and the metal pad 6132 on the inner lead 6122, and then the metal pad 6131 and the metal pad 6132 are connected to the inner pin 6101 and the inner pin 6121 by another metal wire 64? Then, the pad d and the pad d are first connected to the metal pad 6133 on the inner lead 6103 and the metal pad 6134 on the inner lead 6123, and then the metal is soldered by the other metal wire 640. The 塾6133 and the metal pad 6134 are connected to the inner pin 6104 and the inner pin 6124. Therefore, it is possible to avoid connecting the soldering c (c,) directly to the inner lead ore (6121) during the process of connecting c and the soldering c to the inner pin 6ι〇ι and the inner pin 6121. It is necessary to span another metal wire 640 that connects Tan B (b,) and the inner pin (6 (2)); at the same time, the solder d and the solder d, and the inner pin 61〇4 and the inner pin are included. When the connection is completed, when the solder pad d (d,) is directly connected to the (4) leg (6124), the metal of the pad e(e') and the inner pin 61〇3 (6123) must be crossed. wire_. In the other embodiment, as shown in Fig. 8B, a structure in which a plurality of bus bars 63 are used is used to achieve a jumper connection. In Figure 8B, a solder fillet on wafer $(8) is shown. () solder pad d (d) and pad e (e,) and the inner pin 61 () 1 (6 (2)), the inner pin (10) 4 (6) and the inner pin 6103 (6123) are connected, wherein the solder Pad & & soldering &, and busbar (4) and sink frame 63G2 connected 'as a grounding transfer point connection, brain, this embodiment can be 1354364 September 5, 2011 revised replacement page with the manifold The 6301 and the busbar 6302 function as a grounding transfer point, and use the busbar 6305 and the busbar 6304 as the transfer point of the signal. For example, the solder bump c and the solder pad c' on the wafer 5 are first connected to the metal pad 6131 on the inner lead 6102 and the metal pad 6132 on the inner lead 6122 by a metal wire 64 ,. Then, the metal pad 6131 and the metal pad 613 are connected to the inner lead 6101 and the inner lead 6121 by another metal wire 64. In addition, the solder d and the solder d are first connected to the inner lead 6103. Metal pad 6133 and metal pad 6134 on inner lead 6123, and then metal pad 6133 and metal pad 6134 are connected to inner pin 6104 and inner pin 6124 by another metal wire 640; The bonding pad e and the bonding pad e are first connected to the bus bar 6305 and the bus bar 6304, and then the other metal wire 64〇 is used to connect the bus bar 63〇5 and the bus bar 6304 with the inner pin 6103 and the inner pin. 6123 connection. Therefore, it is necessary to complete the connection between the pad c and the pad c' with the inner pin 6101 and the inner pin 6121, and to avoid connecting the pad c (c,) directly to the inner pin 6101 (6121). Crossing the other metal wire 640 connecting the pad 1 > (b,) and the inner pin 6102 (6122); and connecting the pad d and the pad d to the inner pin 61〇4 and the inner pin 6124 'When the pad d(d,) is not directly connected to the inner lead 61〇4 (6124), it is necessary to connect the metal wire of the soldering e (e,) and the inner lead (6123) across the other strip. 640. Therefore, the present invention utilizes the metal pads 613 (ie, 6131 to 6134) and the bus bar 630 (ie, 6301, 6302, 6304, 6305) on the inner leads in the lead frame 600 as the structure of a plurality of transfer points. When the circuit connection is made and the jumper connection is necessary, the staggered crossing of the metal wires can be avoided, and an unnecessary short circuit is caused, so that the reliability of the packaged wafer is generated, and the circuit design can be more flexible. Next, please refer to the SC and FIG., which are schematic plan views of another embodiment of the stacked chip package structure of the present invention. As shown in FIG. 8C and FIG. 8B, the stacked wafer mounting structure comprises a lead frame 600 and a multi-stack staggered stack structure 5, wherein the lead frame is composed of a plurality of oppositely arranged inner lead groups 610. , a plurality of outer pin groups (not shown) and a wafer holder 62. It consists of a sheet holder 62. The system is disposed between the inner pin groups 610 of the J-relative arrangement 1354364, the modified replacement page on September 5, 2011, and the plurality of oppositely arranged inner pin groups 61〇 and the wafer holder 62〇 may also be formed. A height difference or a common plane. In this embodiment, the lead frame 600 can be provided with more electrical contacts for electrical connection of the power contact, the ground contact or the signal contact, so that part of the inner lead group 61〇 An insulating layer 611 is further disposed at the position and at least one metal pad 613 is further disposed on the insulating layer 611. As a result, a large number of transfer pads 613 are provided on the inner leads 610, so that more flexibility and application in the circuit design can be provided. In addition, in the embodiment, the lead frame 6 further includes at least one bus bar disposed between the wafer holder 62 and the plurality of oppositely arranged inner pin groups 61〇, wherein the bus bar is disposed. 630 may be in at least a strip configuration, and the bus bar 63 of each strip configuration is formed by a plurality of metal segments (ie, mine, 63G2, 63G3, 6304, 63G5, 6306), such as 8C and 8D. As shown in the figure; js], the bus bar 63〇 can also adopt an annular configuration, and the busbar 630 arranged in a %-% manner is also formed by a plurality of metal segments, which is not limited by the present invention. Further, as described above, the pads 312/344 in the bonding pads of the wafer 5 may be arranged in a single column or in a double column arrangement, and the present invention is not limited thereto. In addition, since the bus bar 630 of the present invention is formed by a plurality of metal segments (for example, 63〇1 to 63〇6), each of the metal segments is independent of each other, so that the test_invisible towel adds a material W. The busbars 630' formed by the segments can be used as electrical connections for power contacts, ground contacts or signal contacts, so that more flexibility and application of circuit design can be provided in advance. Next, the process of the present invention using the bus bar 63〇 to achieve the metal wire 64 jumper connection is described. 凊Reference 帛8C®. The 8C® shows a schematic diagram of connecting the solder bumps on the multi-wafer staggered stack structure 5 to the (four) legs of the leadframe. Very well, this embodiment is a metal pad on the lead group (10) in Xiang and a plurality of metal segments 4 (for example: 6301~63〇6) forming the bus bar MO as transfer points for achieving welding. Pad a (a,) to pad f (f,) and inner pin 61〇1 (6 to (4) foot (6125) jumper connection, without the occurrence of metal wires _ cross each other. For example, first The wire bond a on the multi-wafer staggered stack structure 5 is first connected to the metal segment ore of the bus bar (4) with a metal wire 64〇, and the metal segment mine system is 18 1354364. The ground connection point '· then directly connects the pad b to the inner pin 61 〇 2; then the wire bond c on the multi-wafer staggered stack structure 50 is first connected to the metal segment 6303 of the bus bar 63 by a metal wire 640, Then, the metal strip 63〇3 of the bus bar 63 is connected to the inner lead 6103 by another metal wire 540; then, the solder on the wafer 5 is first connected to the inner lead 6102 by a metal wire 64? Metal _ 6131, and then another metal wire 64 〇 metal pad 6131 and inner pin 610 1 is connected. Therefore, when the pad c and the pad d are connected to the inner pin 61〇3 and the inner pin 6101, the metal wire 640 and the pad d which are soldered to the inner lead 61〇3 can be avoided. And the metal wires 64 of the inner pin 6101 are crossed across each other. Then, the jumper of the pad e and the inner pin 6105 is connected, and the pad on the stacked structure 50 is interleaved by a metal wire 64 first. e is first connected to the metal segment 63〇5 of the bus bar 63〇, and then the metal segment 6305 of the bus bar 630 is connected to the inner pin 6105 by another metal wire 640. Therefore, when the pad e and the inner pin 61 are connected 5 When the connection is completed, it can be avoided that the metal wire 640 connecting the pad e and the inner pin 61〇5 must cross the other metal wire 64〇 connecting the pad f and the inner pin 61〇4. On the other side The pads a, to f and the inner pin 6121 to the inner pin 6125 are arranged in the same manner as described above, so the jumper connection process is also the same as described above, and therefore will not be described again. Therefore, the pad a, to the solder is completed.塾f' and the connection of the inner pin 6121 to the inner pin 6125 do not cause the metal wires 64 to cross each other. In another embodiment, when a plurality of pads on the multi-stack interleaved stack structure 50 have to be jumpered, the structure of the plurality of bus bars 630 can be used, as shown in FIG. 8C. The 8C diagram also shows a schematic diagram of connecting the pads on the multi-stack staggered stack structure 5 to the inner leads. It is apparent that in the present embodiment, the insulating layer 611 is also disposed on the inner lead group 61. The insulating layer 611 is further provided with at least one metal soldering iron 613, and a bus bar 63〇 formed by a plurality of metal segments (for example, _~〇) is used as a transfer point for reaching the soldering iron (a/a). , ~f/f,) is connected to the inner pin 610 jumper without causing the metal wires 64 to cross each other. For example, 'a metal pad 640 is used to interleave the pads a or a on the stack 5 of the multi-wafer, and the wire is connected to the metal segment _ or mine on the bribe 630, and the metal 19 1354364 revised September 5, 2011 The replacement page segment 6305 or 6306 is used as a ground connection point; then the pad b or b on the multi-wafer interleaved stack structure 50 is first connected directly to the metal segment 6301 or 6302 of the bus bar 63 by a metal wire 64? Then, the metal segment 6311 or 6302 of the bus bar 63 is connected to the metal pad 6131 or 6132 on the inner lead 6102 or 6122 by another metal wire 64, and then the metal pad is replaced by another metal wire 640. The 6131 and the internal pin 6101 are connected to the internal pin 6104 or 6124. Then, the pad d or d' on the multi-stack interleaved stack structure 5 is directly connected to the metal pad 6133 or 6134 on the inner lead 61〇3 or 6123 by a metal wire 64〇, and then another A metal wire 64A connects the metal pad 6133 or 6134 to the inner lead 61〇5 or 6125. Therefore, when the pad b or b' and the inner lead 6102 or 6122 and the pad d or d are connected to the inner lead 6105 or 6125, the connection pad b or b and the inner pin 61 can be avoided. The metal wire 640 of the 〇2 or 6122 and the connection pad d^d, and the inner pin (4) 5 or the still metal wire _ cross each other. Then connect the solder pad e or e, first connect the gold on the downstream shelf 63 () to the segment 7 or 6308, and then use another metal wire 64 to connect the bus frame 63 to the metal segment Kyumachi or 6308. Pin 6102 or 6122 completes the connection 'So, it can also effectively avoid connecting the lining pad e or e, the metal wire 64 内 with the inner lead 6102 or 6122 across the other connection solder f or f, and the inner pin 6103 Or 6123 metal wire 640. Therefore, in the present embodiment, the plurality of metal segments (for example, 63〇1 to 63〇1〇) formed by the plurality of metal pads on the inner lead group 61 of the lead frame (4) are smashed into a bus 63 formed by a plurality of metal segments (for example, 63〇1 to 63〇1〇). 〇 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为 作为At the same time, it can also make the circuit design more flexible. Referring again to Figures 9A and 9B, there is shown a plan view of yet another embodiment of the stacked wafer package structure of the present invention. As shown in FIG. 9A and FIG. 9B, the stacked chip package structure comprises a lead frame 600 and a multi-stack staggered stack structure, wherein the lead frame _ is composed of a plurality of relatively arranged inner 5_61G, and a plurality of legs. Group (not shown) and a 20 1354364 September 5, 2011 revised replacement page wafer holder 620 consisting of 'where the wafer holder 62 is placed between a plurality of oppositely arranged inner pin groups 610 At the same time, a plurality of oppositely arranged inner pin groups 61 〇 and the wafer holder 62 也 can also form a difference in the degree of latitude. In the present embodiment, the multi-stack interleaved stack structure 5 is disposed on the wafer holder 620, and connects the multi-wafer staggered stack structure 5〇〇 to the inner lead group 610 of the lead frame 600 via the metal wires 64〇. . Continuing to refer to FIGS. 9A and 9B, in the lead frame 600 of the stacked chip package structure of the present invention, an insulating layer 611 is disposed on the inner lead group 610 and at least one metal pad is disposed on the insulating layer 611. 613 'This way, 'there is a lot of adapter pads on the inner lead group 61', so it can provide more flexibility and application in circuit design. In addition, an insulating layer 632 is further disposed on the bus bar 630 of the present invention, and at least one metal pad 634 is further disposed on the insulating layer 632, so that a plurality of adapter pads are also disposed on the bus bar 630, so More flexibility and application in circuit design. It is to be emphasized that the 'bump 630 can be arranged in a strip shape as shown in Figs. 9A and 9B; and the bus bar 630 can also be in a ring configuration (not shown), which is not limited by the present invention. Further, as described above, the solder bumps in the bonding wire bonding regions of the wafer 5 may be arranged in a single column or in a double column arrangement. The present invention is also not limited. Next, the process of using the metal wire 64 jumper connection in this embodiment will be described. It is obvious that the present embodiment utilizes the metal pad 613 on the (four) leg group _ and the bus bar _ and the plurality of metal pads 634 on the bus bar can. As a transfer point, the pad a(a,) to the pad (10), and the inner pin 6101 (6121) to the inner pin 61〇5 (6125) are jumpered, and the metal 'wire 640 is not generated. The situation of crossing each other. For example, first use a metal wire _ to multi-stack the stack structure on the stack 塾 a first connect the turtle flow (four) G1, and the secret flow frame as a grounding connection point; connect the solder 塾 b directly to the inner lead Then, with the metal wire _, the soldering c on the multi-chip parent-staggered stack structure is first connected to the metal soldering iron (4) on the inner pin slot, and then the metal wire is soldered with another metal wire 64〇 6131 is connected with (four) foot _. 21 1354364 Therefore, the foot 6101 spans. Also on September 5, 2011, the correction replacement page ^ C and (4) chat 6101 complete the connection, so as to avoid connecting the welding wire c and the inner lead metal wire 64 〇 and the pad b and The metal wires of the pins 61〇2 are successively connected to each other, and the metal pads 640 are used to connect the pads d on the multi-wafer staggered stack structure to the jumper of the 61-year-old ====3 Then, the material e and the inner pin _5 are connected to the mail IM-strip metal wire _ the pad e on the multi-wafer staggered stack structure is first connected to the metal pad 6135 on the == 16104, and then The other metal wire will be connected with (4) the foot; finally, the jumper connection of f and (4) foot _3 will be carried out. First, the metal wire will be used to connect the pad f on the stacking structure first. 1 赖 t63G1 Metal welding (4) 41, money and then another - gold slash _ the metal welding 634i of the busbar is connected to the inner _ 61G3. Therefore, when the solder fillet d, the pad e, the solder bump ^ and the inner pin _, the inner pin 61 〇 4, and the inner pin 61 〇 5 are connected, the connection of the solder d(8) and the inner pin 6104 can be avoided ( The metal wire 64〇 of the )) must span the other metal wire 64〇 connecting the solder f and the inner lead 6103. On the other side, the solder fillet &, to the solder fillet f, and the inner lead (4) to the inner lead 6125_ are set to be the same as described above, so the jumper connection process is also the same as described above, and therefore will not be described again. Therefore, after the connection of the inner leads (10) to the inner leads (4) is completed, the metal wires 64 〇 do not cross each other. In another embodiment, as shown in Fig. 9B, when a plurality of solder bumps on the wafer 5 are required to be jumper-connected, the structure of the plurality of bus bars 63A can be used. In this embodiment, a plurality of metal pads 613 are disposed on the inner lead group 6U), and a plurality of metal pads 634 are also disposed on the plurality of bus bars 63 as transfer points, wherein the metal pads 613 and The metal solder gamma and the inner lead group (10) and the bus bar (10) are connected by an insulating layer. The actual connection and jumper process of this embodiment are the same as those of the above-mentioned 9A, and therefore will not be described again. In addition, it is to be emphasized again that the multi-wafer staggered stack structure of the present invention is fixed on the lead frame _ 22 1354364 on the revised replacement page of September 5, 2011, in which a plurality of wafers in a multi-stack interleaved stacked structure are stacked, It can be a wafer of the same size and the same function (for example, a memory wafer), or a wafer of a plurality of wafers having different sizes and functions (for example, the uppermost wafer is a driving wafer and the other wafers are Memory chip). The wafer size or wafer function of the multi-stack interleaved stack is not a feature of the present invention, and will not be described herein. Next, please refer to FIG. 10, which is a cross-sectional view of the multi-wafer interleaved package structure along the section of the line along the seventh embodiment of the present invention. As shown in FIG. 10, the lead frame 600 and the multi-stack staggered stack structure 50 are connected by a plurality of metal wires 64A, 64B, 64A, 64, d, wherein the lead frame 600 is composed of a plurality of wires The oppositely arranged inner pin group 61 〇, the plurality of outer pin groups (not shown) and the wafer holder 62 , are formed, and the wafer holder 62 is disposed in a plurality of oppositely arranged (four) legs Between groups 610, and a plurality of squad (four) foot groups _ form a height difference. In the present embodiment, an insulating layer 611 is disposed on the inner lead group 61, and at least one metal pad 613 is disposed on the insulating layer 621. As a result, a large number of adapter pads are provided on the inner pin group (10), which can provide a more complicated circuit design and application. As shown in Fig. 10, the metal wire is connected to the wafer 5〇〇a by one end of the metal wire 64〇3 by a wire bonding process, and the other end of the metal wire 64〇a is connected to the solder wire of the wafer structure lion. . Next, one end of the metal wire is attached to the pad of the wafer 5, and then the other end of the wire 640b is attached to the pad of the wafer 5〇〇c. Then, the process of metal wire weaving and secret is repeated, the metal wire is torn to remove the wafer and the wafer is removed, and the wafer 5〇〇c is electrically connected to the wafer. Then, the metal wires 64 〇 § respectively connect the wafers 50 〇 a, 5 〇〇 d and the plurality of inner pin groups 61 〇 (for example, the inner leads 61G1 or 6121) of the lead frame 600 to be electrically connected. 'This - come, through the metal wire _ ' secret, 640c and 640d # to complete the connection layer by layer, you can connect the wafer 5〇〇a, lion and fine electrical connection to the conductive _, which metal f can use bribes. At the same time, because the lead frame 61 of the lead frame of the present embodiment is provided with a metal soldering iron 23 1354364 201 September 5, the revised replacement page can be used as a power contact, a ground contact or a signal contact. Transfer welding. For example, when the field metal pad 613 is used as a signal connection point for circuit connection, one end of the metal wire can be connected to the pad of the wafer (for example, the pad b), and the other end of the wire is connected. To the metal turn 613 (for example, the metal soldering iron 6132), the metal solder wire 6132 is connected by a metal wire 640f to an inner pin (for example, the inner lead 6 (2)). Therefore, on the other side of the s-chip 500a, a plurality of metal wires can be used to connect the wafer (e.g., _a) to the inner pin group (10) (for example, an internal pin). Then, the end of the metal wire 640g is connected to the pad of the wafer a (for example, the pad b), and the other end of the wire 6 is connected to the metal pad 613 (for example, the metal pad 6131). Then by the metal wire 6. Connect the gold shavings 6131 to an internal pin (for example: inner pin Na). In this way, through the transfer of the gold secret 613, there will be no increase in the heterogeneity of the metal wire to be crossed in order to span other metal wires, which can not only increase the flexibility of circuit design or application, but also effectively improve Capacity and reliability of the packaging process. In addition, it should be emphasized that the wafer 5〇〇b is directly stacked on the wafer 500a, and the two molecular materials 230 are fixed together as an adhesive layer, and the wafers 5〇〇b are stacked on the same. The bonding wire of the wafer 500a is bonded to a region other than H 32 , which can be smoothly performed by the subsequent wire bonding process. In addition, this embodiment does not limit the wire bonding process of the metal wires 64. Therefore, it is also possible to sequentially connect the pads on the wafer 500f to the direction of the wafer 500a, and finally the wafer 5A and the lead frame 600. connection. Next, please refer to Fig. 11, which is a schematic cross-sectional view of the multi-wafer staggered stacked package structure of the present invention (i.e., a cross-sectional view taken along line AA of Figure 8A or along line AA of Figure 8C). As shown in FIG. u, the lead frame 600 and the multi-stack interleaved stack structure 50 are connected by a plurality of metal wires 64 ,, wherein the lead frame 600 is composed of a plurality of oppositely arranged inner pin groups 61 〇, plural An outer pin group (not shown) and a wafer holder 620 are formed, and the wafer holder 62 is disposed between the plurality of oppositely arranged inner pin groups 610' and is arranged in a plurality of opposite rows The pin group 610 forms a height difference, and at least one bus bar 630 is disposed between the inner pin group 61 and the crystal 1354364 modified replacement page holder 620 on September 5, 2011. The bus bar in this embodiment is disposed in a plane with the wafer holder 62. In this embodiment, an insulating layer 611 is disposed on the inner lead group 610 and at least one metal pad 613 is disposed on the insulating layer 611. As shown in FIG. 11, the metal wire 640 is connected to the pad of the wafer 500a by a wire bonding process, and the other end of the metal wire is connected to the pad of the wafer structure 5; One end is connected to the pad of the chip 500b, and then the other end of the metal wire is connected to the pad of the chip 5GGe; then the metal wire is cycled, and the chip 500c is electrically connected to the chip 500d by the metal wire. Then, the inner lead group 61〇 (for example, the inner lead 6102 or 6122) of the plurality of oppositely arranged wafers 500a and the lead frame 600 is electrically connected by the metal wires _. In this way, after the connection is completed layer by layer through the metal wires 64 and woven, the wafers 500a, 500b, 5〇〇c, and 5〇〇d can be electrically connected to the lead frame 600', wherein the metal wires 64〇 The material can be gold. In the meantime, since the lead frame 600 of the present embodiment is provided with a plurality of metal pads 613 on the inner lead group 61, & is provided with a bus bar 63, which can be used as a power contact, a ground contact or The connection point of the news point or the city is not. For example, taking FIG. 8c as an example, when the bus bar 63G is used as the transfer point of the circuit connection, one end of the metal wire strip can be connected to the material of the wafer 5GGa, and the gold wire (4) is connected to the bus line at the other end. Above the shelf (eg, busbar 6301), the metal busbar 64〇k is then used to connect the busbar 63〇丨 to one of the internal pins (eg, inner pin 6123). Next, one end of the metal wire (4) is connected to the pad of the wafer 500a' and the other end of the metal wire is connected to the metal pad metal pad 613 on the inner lead; then the metal is fed by another metal wire 64〇n Solder pin 613 is connected to an internal pin (eg, inner pin 6121). In addition, the wafer stack of the multi-stack interleaved stack structure 50 can also be disposed on the other side of the (9). Therefore, on the side of the wafer, a plurality of metal wires are 6 tons. To connect the solder bumps on the wafer genus. Next, the metal wire woven end 25 1354364 September 5, 2011 modified replacement page is connected to the pad 500c of the wafer 500c (for example: pad c), and the metal wire 64 〇 The other end of the e is connected to a busbar (for example, the busbar 6302), and then the metal bus 64 sinks the busbar 6302 to an internal pin (for example, the inner pin 613). Then, One end of the metal wire 64〇g is connected to the pad of the wafer 500b, and the other end of the metal wire 64〇 is connected to the metal pad on the inside 613, and then the metal pad 64 is used to make the metal pad. It is also connected to an inner pin. In addition, it is also emphasized that the wafer 500b is directly stacked on the wafer, and the two are fixed together with a polymer material as an adhesive layer, and the wafer 5_ is Stacked on the area other than the bond wire bonding area of the wafer 500a In the following, the wire bonding process can be smoothly carried out. In addition, the present embodiment does not close the wire bonding process of the metal wire, so it is also possible to select the pads on the wafer surface to be sequentially connected in the direction of the application, and finally The rack 600 is connected. , Guides, then please refer to the first! 2 to U, which are along the line SA or the v-segment along the line SA = cross-sectional schematic view, which is another section of the polymorphic stacking structure of the present embodiment: intent. The difference between the 12th and 14thth aspects of the present invention is that the geometric position between the lead frame 610 and the wafer holder 620 is not phase L, for example, in the present embodiment. The bus bar 630 is formed in the same manner as the inner pin group _2, and the thirteenth circle in the present embodiment is configured, and the bus bar 630 is formed with the inner lead group 610 and the wafer - a height difference configuration; The __ Μ, formed on the button and the bus bar 630 and the inner pin group 610 and the wafer carrier gamma, the other: Guide: 600:, = also: Figure 12 to Figure 14 in addition to the structure of the lead frame 600 A slightly different connection process is the same between the 5 系 由 复 复 复 复 复 由 由 由 由 由 由 由 由 由 。 。 。 。 。 。 。 。 。 。 。 。 Next, please refer to (4) diagram again, which is a cross-sectional view of the re-executing example of the BB line segment of the replacement page BB line along the line segment or the second figure of the invention according to Fig. 8B of the present invention. The difference between Fig. 15 and Fig. 11 to Fig. 14 is that the bus bar 630 in Fig. 15 is a structure using a plurality of bus bars, and the configuration of the plurality of bus bars 630 may be the strip configuration of the eighth BB. The ring configuration which can be is not limited by the present invention. Similarly, the bus bar 630 in this embodiment may be further formed of a plurality of metal segments (e.g., 63G1 to 63G1G). Obviously, since the number of bus bars is increased, the number of electrical connections can be increased, so that the connections of the pads (312a; 344) on the multi-wafer stack 50 can be made more flexible, so that It will increase the arc of the metal wire to be crossed in order to cross other metal wires, and therefore not only can increase the circuit design or lie on the turn, but also increase the capacity and sin of the packaging process due to the lead frame 6 The 〇〇 and multi-wafer staggered stack structure % are connected by a plurality of metal wires 640 _ the same, the young line process is not the ship of the present invention, so it is not mentioned. Please refer to FIG. 16 to FIG. 19, which are schematic cross-sectional views of the multi-chip parent flip-chip package of the section along the aa line segment along the 9th drawing of the present invention. As shown in Figure 16, the lead frame 6〇〇 and multi-chip, · a . And,,. The 0 structure 50 is connected by a plurality of metal wires 640, wherein the lead frame 6 is composed of a plurality of relatively arranged inner pin groups 61 〇, a plurality of outer pin groups (not shown on the figure), and The wafer holder 62 is formed, and the wafer holder 62G is disposed between the plurality of oppositely arranged inner lead groups 610, and forms a height difference with a plurality of oppositely arranged inner lead groups 61, and at least - The strip manifold 63G is placed between the (four) leg group 61〇 and the wafer holder 62G. In the present embodiment, an insulating layer 611 is disposed on the inner lead group 610 and at least one metal pad 613 is disposed on the insulating layer 611. In this way, the inner lead group 61 has a large number of adapter pads, so that more flexibility and application in circuit design can be provided. In addition, the bus bar (10) and the wafer holder 62G in this embodiment are arranged in a coplanar configuration, wherein the bus bar (10) can be arranged in a strip shape as shown in FIGS. 9A and 9B; and the bus bar _ A ring configuration can also be used (not shown in Figure _). In addition, in order to enable the lead frame to provide more electrical contacts for electrical connection as a power contact, a ground contact or a signal contact, the bus bar in the present invention is further provided with an insulating layer 632. And at least one metal soldering gamma is further disposed on the insulating layer 632. 27 1354364 Revised replacement page on September 5, 2011 This resulted in a large number of adapter pads on the busbar 630, which provided more flexibility and application in circuit design. As shown in FIG. 16, the metal wire 64 is connected to the first pad 312a or the third pad 344 of the wafer 500a by a wire bonding process (for example, the first pad in the foregoing FIG. 3). 312a or third pad 344)' and the other end of the metal wire 640a is connected to the first pad 312a or the third pad 344 of the wafer structure 500b; then, one end of the metal wire 640b is connected to the first of the wafer 500b On the pad 312a or the third pad 344, the other end of the metal wire 6〇〇b is then connected to the first pad 312a or the third pad 344 of the wafer 500c; then the metal wires 640a and 640b are repeated. The process of electrically connecting the wafer 500c to the wafer 500d by the metal wire 640c; and then, the metal pad 640d is used to compare the pads (for example, the solder bump b) on the wafer 5〇〇3 with the plurality of lead frames 600. The arranged inner pin group 61〇 (for example, the inner pin 6102 or 6122) is electrically connected. In this way, after the metal wires 640a, 640b, 640c, and 640d are connected layer by layer, the wafers 500a, 500b, 500c, and 500d can be electrically connected to the lead frame 600, and the materials of the metal wires 64 can be used. gold. At the same time, the lead frame 600 of the present embodiment is provided with a plurality of metal pads 613 on the inner lead group 61 ,, and a plurality of metal pads 634 are further disposed on the bus frame 630, which can be used as a power source. Electrical connection point of the contact, ground contact or signal contact or signal transfer point. For example, taking FIG. 9A as an example, when the metal pad 634 on the bus bar 630 is used as the transfer point of the circuit connection, one end of the metal wire 640e can be connected to the pad of the wafer 500a (for example, the pad f) '), and the other end of the metal wire 64〇e is connected to the bus bar (for example, the bus bar 6342), and then the metal wire 640f is used to connect the bus bar 6342 to an inner pin (for example: internal lead) Foot 6123). Next, one end of the metal wire 640g is connected to the pad of the wafer 5〇〇a (for example, the pad c'), and the other end of the metal wire 64〇g is connected to the metal pad on the inner pin 6122 (for example : Metal welding 76132); then the metal pad 6132 is connected to one of the inner leads (for example, the inner lead 6121) by another metal wire 6·. In addition, the polycrystalline silicon staggered stack structure 5 〇 the top layer of the crystal moon 5 〇〇 d, which can also be configured with a plurality of pads on it 1354364 ο , , , September 5, 2011 revised replacement page 曰; On the other side of the 'as shown in Figures 2D and 5Β. Therefore, on the other side of the wafer, it is possible to connect the turn-on (for example, the solder bump 3 pin group 610 (for example, the inner pin_2)) by the returning metal wire _. The end of the wire 640" is connected to the pad of the wafer (for example, the soldering f), and the other end of the metal wire is connected to the bus bar 6341, and then the other metal wire will be merged. M8 is connected to an internal pin (for example, internal pin 6103). Then, the end of the metal wire _n is connected to the surface of the wafer (for example: d) and the other end of the metal conductor = 〇m is connected to the metal pad on the inner lead seam (for example: metal pad _ ; = Then connect the metal soldering iron 6133 to one of the inner pins 6104 with another metal wire 64〇n.传太路^月第_·! 7图〜19图' is a schematic cross-sectional view of another embodiment of the erroneous stacking structure of the slab along the Μ line section of Fig. 9A. The difference between the Fig. 19 of the present invention and the above Fig. 16 is that the lead frame _(4) thief === "士_架架630疋 is in a coplanar configuration with the inner pin group 610; In the figure 18, the _63 〇 and the inner lead group 61 〇 and the wafer holder must be in a high-fifth embodiment, and between the above-mentioned 16th and 18th drawings. The foot group 610 and the wafer holder 620 are coplanar, and the height difference between the frame (4) and the inner pin group (10) and the wafer holder 62 is formed. The structure of the lead frame _ is slightly different. Differently, the connection process between the lead frame _ and the multiple #峻^·^, the structure 5G, and the plurality of metal wires 64G are the same, and the wire bonding process is not a feature of the present invention, and therefore will not be described again. 2 〇 , , , 第 第 第 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 630 The structure, and the configuration of the plurality of bus bars 630 can be arranged in a strip shape of the heart map, or can be a ring configuration (not shown in the figure), the present invention 00 1354364 201 The revised replacement page of September 1st, 1st is not limited. Obviously, due to the increase in the number of busbars, the number of electrical connections can be increased, so that the welding on the multi-wafer stack structure can be made. The connection of the pads (3i2a; 344) is more flexible, so that there is no increase in the curvature of the metal wires to be spanned across other metal wires, and thus not only can increase the flexibility of the circuit design or application, but also Effectively improving the productivity and reliability of the packaging process. Since the connection process between the lead frame 6〇〇 and the multi-stack interleaved stack structure 50 is the same by a plurality of metal wires 64〇, and the wire bonding process is not a feature of the present invention, Throughout the above description, the embodiments described in the present invention do not limit the number of stacked wafers 5, and those skilled in the art should be able to make three according to the methods disclosed above. The stacked wafer package structure of the above wafer 500. Meanwhile, the stacking direction of the multi-wafer staggered stack structure 50 of the present invention is not limited to the embodiment. It is also possible to stack the stacking direction of the wafers 5 in a staggered amount relative to the direction disclosed in the previous embodiment. Due to the wafer bonding between the multi-wafer staggered stack structures (referred to as 70) in different directions And the manner in which the multi-stack interleaved stack structure 70 is bonded to the lead frame 600, and the manner in which the multi-wafer is used to connect the multi-wafer stacking structure 70 and the lead frame 600, etc., is performed in accordance with the foregoing, and thus is interleaved for multiple wafers. The embodiment of the stack structure and the lead frame 6〇〇 will not be described here. It is emphasized here that in all the above embodiments of the present invention, the insulating layer 611 on the inner lead group 61〇 and the bus bar 630 The upper insulating layer 632 can be formed by c〇ating or printing-polymer materials, for example, poly(imide) 2〇lyimide, ρι), or can also be reposted ( Attaching) the formation of a wire, such as a tape (this film). The metal soldering 613 and the metal soldering 634 may be formed on the insulating layer 611 and the insulating layer 632 by a plating process or an etching process. It should be emphasized that the insulating layer 611 and the insulating layer 632 of the present invention may be disposed on the entire inner lead 61〇 and the bus bar 630, and may be formed in the multi-stage manner in the inner lead 61 () and the bus bar 630 in pure manner. Above, the invention is also not limited. In addition, the present invention can also form an insulating layer on the metal pad 6 ι and the metal pad 634 and then form the metal 1354364 LB again on the insulating layer, and the replacement page soldering is corrected on September 5, 2011. A large number of adapter welds can be placed on the lead frame of the present invention. Obviously, according to the above implementation of the financial statement, the present invention may have a modified face decoration __峨, heart _: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The above is a preferred embodiment of the present invention, and the equivalent of the patent application of the present invention is exemplified; the equivalent changes or modifications performed in the spirit of the other inventions are included in the following patent scope. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are schematic views of the prior art; 2A and 2C are views of the wafer structure of the present invention; 2B and 2D are cross-sectional views of the wafer structure of the present invention; and FIG. 2E is the present invention A cross-sectional view of a multi-wafer staggered stack structure; 3A'3B and 3C are schematic views of a reconfigurable layer manufacturing process of the present invention, and FIGS. 4A and 4B are cross-sectional views of a bonding wire bonding region in the reconfigurable layer of the present invention; 5 and 6 are views of the multi-wafer staggered stack structure of the present invention having a reconfigured layer of a multi-wafer staggered stack structure. The top view of the multi-wafer staggered stack structure package of the present invention; another 8A, 8B of the wafer staggered stack structure package 8C and 8D are views of a plurality of embodiments of the present invention; views 9A and 9B are diagrams of another embodiment of the multi-wafer interleaved stacked package of the present invention. FIG. 10 is a multi-wafer of the seventh embodiment of the present invention. Staggered stacking bribes FIG. 11 is a cross-sectional view of one embodiment of a multi-wafer staggered stacked package of the present invention; FIG. 12 is another embodiment of the multi-wafer staggered stacked package of the present invention; Figure 13 is a cross-sectional view showing another embodiment of the multi-wafer stacking structure of the present invention; Figure 14 is a cross-sectional view showing another embodiment of the multi-wafer staggered stack structure of the present invention; 1 is a cross-sectional view of another embodiment of a multi-wafer staggered stack structure of the present invention; FIG. 16 is a cross-sectional view showing another embodiment of the multi-wafer staggered stack structure of the present invention; and FIG. 17 is a multi-wafer staggered stack structure of the present invention. 1 is a cross-sectional view of another embodiment of the multi-wafer staggered stack structure of the present invention; FIG. 19 is a cross-sectional view of another embodiment of the multi-wafer staggered stack structure of the present invention; and 20th BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing another embodiment of a multi-wafer staggered stack structure of the present invention. [Major component symbol description] 10, 100, 400: stacked chip package structure 110, 410: electricity The circuit substrate 112, 122a, 122b, 122c, 122d: pads 120a, 120b, 120c, 120d: wafer 130: spacers 140, 242, 420, 420a, 420b: wires 150, 430 · · encapsulant 200 : wafer 210 . Wafer Active Surface 220: Wafer Back 230: Adhesive Layer 32 1354364 Rev. 5, 2011 Revision Replacement Page 240: Pad 250: Wire Junction Zone 260: Wire Junction Edge 30: Multi-Layer Staggered Stack Structure 310: Wafer Body 312a : first pad 312b : second pad 320 : wire bond region 330 : first protective layer 332 : first opening 340 : re-distribution circuit layer 344 : third pad 350 : second protective layer 352 : second Opening 300: Wafer structure 400: Reconfiguration layer 50: Multi-wafer staggered stack structure 500 (a, b, c, d): Wafer structure 600: Lead frame 610: Inner lead group 6101 to 6104: Inner pin 611: Insulation Layers 6121 to 6124: inner pin 613: metal pad 615: first inner pin group 616: second inner pin group 33 1354364 September 5, 2011, correction replacement page 617: connection portion 618: platform portion 620: Wafer holder 630: bus bar 6301~63010: bus bar 632: insulating layer 634: metal pad 6341~6343: metal pad 640 (a~n): metal wire 70: multi-wafer staggered stack structure a~f: welding Pad a'~f': pad 34