1353720 六、發明說明： 100年8月18曰修正替換頁| 【發明所屬之技術領域】 本發明係關於一種單端輸型D類放大器，尤指一種雙 反饋差分迴路之單端輸出型D類放大器。 【先前技術】 一般來說，輸出級的放大電路概包含有A類、B類、 AB類及D類等放大器，早期較常見的為ab類放大器，但 隨者半導體製程的成熟，具有較低消耗功率的D類放大器 漸為常見。 D類放大器與AB類放大器最大差異即是輸出脈寬調變 訊號推動電感性負载’而非以線性訊號推動之；其中該脈 寬調變訊號係包含有聲音訊號以及脈寬調變開關訊號和諧 波訊號。由於D類放大器輸出脈寬調變訊號，使得輸出級 開關電路的各開關自高阻抗切換至極低阻抗，且導通時間 短，使得導通電流流經導通電阻時間相對縮短，而較Ab類 放大器更有效率，且消耗功率更小。 請參閱第五圖所示，係為一種既有開迴路的單端輸出 型D類放大器（70)，該D類放大器（70)包含有一增益放大器 (71)、一 PWM調變器（72)、一振盪器（73)、一邏輯電路（74) 及一半橋電路（75)〇其中該增益放大器（71)輸入端（vi)係連 接一外部類比聲音訊號，並將該外部類比聲音訊號予以放 大後’如第七圖所示，放大的聲音訊號（v)經對應的PWM 調變器（72)依據振盪器輸出的振盪訊號（S2)輸出脈寬調變 訊號（P，N)，藉由邏輯電路（74)依據脈寬調變訊號控制半橋 3 1353720 100年8月18曰修正替換頁 電路（75)啟閉，由於該半橋電路供外部電感性負載（6〇)連 接’該電感性負載（60)即可還原出聲音訊號。 由於該振盪器輸出的振盪訊號頻率高，以20Hz至 2〇KHz的聲音訊號為例，其配合採用的振盪訊號為 350KHz。請參閱第六圖所示，該PWM調變器（72)將放大後 的聲音訊號加入高頻振盪訊號進行脈寬調變訊號之脈 寬調變’故能將包含在放大後的聲音訊號（S1)中的雜訊（N1) 推至高頻段，由於該雜訊（N1)被移頻至較高頻段，而聲音資 料（S1)則保留在低頻段中，故d類放大器（70)輸出至電感性 負載（60)之前可透過該低通濾波器（8〇)的特性（81)，將高頻 的雜訊（N1)濾除。 由於上述單端輸出型D類放大器（70)雖能藉由調變技 術將雜訊移頻至高頻段，但必須再配合一高階低通濾波器 (80)才能將咼頻段的雜訊加以濾除，造成使用單端輸出端型 D類放大器電路的整體體積無法小型化。再者，由於增益放 大器（71)及PWM調變器（72)均分別使用放大器元件，而放 大器本身的雜訊基準（Noise Floor)又屬於動態雜訊的一 種’因此當聲音訊號輸入至該增益放大器（71)時，該動態雜 訊會併入放大後的聲音訊號中，造成最後輸出訊號的總諧 波失真加噪訊比（THD+N)與訊號失真雜訊比（SDNR)不佳。 是以’目前已有一種閉反饋迴路的單端輸出型D類放 大l§(70 a)推出’請配合參閱第八圖所示，其包含有： 一訊號放大器（71)’係包含有一類比輸入端（乂丨），供類 比聲音訊號輸入之； 一比較器（72)，其一輸入端係連接至該訊號放大器（71) 4 1353720 100年8月18日修正替換頁 的輸出端’另一輸入端則連接一振盈器（73)，將放大的聲音 訊號與振盪訊號比對後，以輸出脈寬調變訊號； 一邏輯電路（74) ’係連接至該比較器（72)的輸出端，依 據脈寬調變訊號輸出驅動訊號； 一半橋電路（75)，係由一上側開關電路（751)及一下側開 關電路（752)組成，其中該上側及下側開關電路（751，752)的 控制端均連接至該邏輯電路（74)的輸出端，以接受驅動訊號 而決疋上側及下側開關電路（7 5 1，7 5 2 )的啟閉，又該半橋電 路（75)的上側開關電路（751)及下側開關電路（752)的串聯節 點為D類放大器的輸出端（D〇)，故可供一電感性負載 連接；及 一階反饋電路（711)，係連接該半橋電路（75)的串聯節點 與訊號放大器（71)的類比輸入端（Vi)。 上述D類放大器（70a)包含有一階反饋電路（71)，可將 增益放大器本身放大器雜訊、參考電壓雜訊、增益/頻寬乘 積限制以及含三角波生器的非線性值之反饋輸出訊號等非 線性項（non-linear terms)予以消除，然而，上述一階反饋迴 路僅由單一訊號放大器將聲音訊號予以合成後作放大，因 此整體的開迴路增益相當有限。 【發明内容】 有鑑上述問題’本發明的主要目的係提供—種雙反饋差 分迴路之單端輸出型〇類放大器，能提供更佳的雜訊失真訊 號比0 ' 欲達上述目的所使用的主要技術手段係令該單端輸出 5 1353720 100年8月18日修正替換頁 型的D類放大器的單端輪出端連接&一反向器7^提供3 差分輸出訊號端;其中該D類放大器係包含有一增益調整電 路一階積勿窃、一比較器、一邏輯電路及一半橋電路； 其中該二階積分器係包含有： -第-差分放大器’係包含有一正向輸入端一反向 輸入端、-反向差分輪出端及一正向差分輸出端，其中該 正向輸入端係連接至該增益調整電路’以調整該第一差分 放大器的增益； 一第一 RC電路，係分別連接於D類放大器的差分輸出 訊號端與該第-差分放大II的正向及反向輸人端之間，構成 二組第一階積分電路； 一第二差分放大器，係包含有一正向輸入端、一反向 輸入端，其中該正向輸入端係連接至該第一差分放大器的 正向差分輸出端，而該反向輪入端則連接至該第一差分放 大器的反向差分輸出端；及 二第二RC電路，係分別連接於D類放大器的差分輸出 訊號端與該第二差分放大器的正向及反向輸入端之間，構成 二組第二階積分電路。 由於單端輸出型D類放大器僅有單一輸出端供電感性 負載連接，故本發明將該反向器連接至該單一輸出端，令〇 類放大器提供一組差分輸出訊號端，而能設計全差分電 路’並配合二階積分器構成二階回饋電路，以幫助第一及 第二差分放大器本身的雜訊等非線性元件能更快速衰減， 並且能提供更高的高頻衰減值，提高整體的雜訊失真雜訊 比；再者，本發明D類放大器差分輸出訊號經過二級增益 6 1353720 100年8月18日修正替換頁 處理後可以得更精細的修正。 綜上所述，本發明除了將全差分電路設計在單端輸出 型D類放大器外’更將第一及第二差分放大器納入二階回 饋系統中，而能有效消除非線性元件消除，而令整個D類 放大器全線性化’而相對得到更好的總諧波失真加雜訊比 (THD+N)效能。 本發明次一目的係提供一種可大幅降低電磁干擾的單 端輸出型D類放大器，意即上述半橋開關電路的高側開關 組與低側開關組再分成二組第一及第二子半橋電路，其中 第一子半橋電路的高/低側開關數量多於第二子半橋電路 的高/低側開關數量，其中第一及第二子半橋電路的事聯 節點係連接至D類放大器的單輸出端。令上述邏輯電路輸 出四組脈寬調變訊號至本發明的半橋電路，其中第二子半 橋電路的驅動方式不變，惟邏輯電路產生驅動第一子半橋 電路二組之脈寬調變訊號之邏輯運算式係為別="2_尤； 尸1 = ’其中X及Ν2為差分輸出訊號端之差分訊號與三 角波訊號比較後的數值。由此邏輯運算式可知當D類放 大器的差分輸出端無輸出時，χ*Ν2會完全相同，使得無 脈寬調變訊號輸出至第一子车抹 m，丄 于牛橋電路’因此本發明即能讓 開關數量多的第一子半橋雷说+ 丁干備電路在無訊號輸出時不作動；而 在D類放大器有訊號輸出時 -^ ^ a ^第一子丰橋電路的高/低側 開關組的其中一組有動作.θ 、， 另勒作，疋以’能有效降低半橋電路的 切換知失及輸出切換迴轉座〜+ + (output switch slew rate)，可降 低整體D類放大器的ΕΜί值。 7 1353720 【實施方式】 100年8月18曰修正替換頁 5月參閱第一圖所示，係為本發明雙反饋差分迴路之單端 輸出型D類放大器（1〇)一較佳實例施例的電路方塊圖其包 含有一增益調整電路（11)、二階積分器、二比較器（3〇,31)、 一邏輯電路（40)、一半橋電路（50)及一反向器（24)，其中該 半橋電路（50)係包含有二相串接的高側開關組（51)及一低側 開關組（52)，其串聯節點即為D類放大器單輸出端（D〇); 又，該單端輸出型（Do)的〇類放大器的單端輸出端（D〇)連接 該反向器（24)，以提供一組差分輸出訊號端（D〇+D〇_)。其中 該二階積分器係包含有： 一第一差分放大器（20)，係包含有一正向輸入端、 一反向輸入端（-)、一反向差分輸出端（+)及一正向差分輸出 端（-)，其中該正向輸入端（+)係連接至該增益調整電路 (11) ’以調整該第一差分放大器（20)的增益； 二第一 RC電路（21)，係分別連接至差分輸出訊號端 (Do +，D0-)與該第一差分放大器（2〇)的正向及反向輪入端 (+，-)之間’構成二組第一階積分電路； 一第二差分放大器（22)，係包含有一正向輸入端（+)、 一反向輸入端（-)’其中該正向輸入端（+)係連接至該第一差 分放大器（20)的正向差分輸出端（+)，而該反向輸入端㈠則 連接至該第一差分放大器（20)的反向差分輸出端（_);及 二第二RC電路（23)，係分別連接於差分輪出訊號端 (Do+，D0-)與該第二差分放大器（22)的正向及反向輸入端之 間，構成二組第二階積分電路。 本發明將該反向器（24)連接至該單一輸出端（D〇)，使單 8 1353720 100年8月18日修正替換頁 端輸出型D類放大器（1〇)提供t組差分輸出訊號^ <Dd+’D0 ；)»而構成一個全差分電路，並配合二階積分器構 C階_電路’幫助第-及第二差分放大器（20,22)本身 的雜訊等非線性元件能更快速衰減，如第二圖所示並且 能提供更咼的高頻衰減值，提高整體的雜訊失真雜訊比 (SDNR) ’再者’本發明〇類放大器(1〇)差分輸出訊號 (Do +，D0-)經過二級增益處理後可以得更精細的修正；因 此’本發明除了將全差分電路設計在單端輸出型D類放大 器外，亦將第一及第二差分放大器（2〇22)納入二階回饋系 統中，而此有效消除非線性元件消除，而令整個D類放大 器全線性化’而相對得到更好的總諧波失真加雜訊比 (THD+N)效能《再者，全差分電路架構的單端輸出型D類 放大器能提高電源紋波抑制比（p〇wer supply rejecti〇n rati〇n，PSRR) ' 共模拒斥比（common mode rejection)及抗雜 訊串音（crosstalk noise rejection)。 再請參閱第三圖所示，係為本發明單端輸出型D類放 大器（10a)的第二較佳實施例，其大多結構與第一較佳實施 例相同’惟該半橋電路（5〇)的高側開關組與低側開關組再進 一步分成二組第一及第二子半橋電路（5〇a5〇b)，其中第一 子半橋電路（50a)的高/低側開關數量多於第二子半橋電路 (50b)的高/低側開關數量，其中第一及第二子半橋電路 (50a，50b)的串聯節點係連接至d類放大器的單輸出端 (Do)。其中該第一子半橋電路（50a)的高/低側開關數量為第 二子半橋電路（50b)的高/低侧開關數量的3至5倍。 再者，本實施例的邏輯電路（4〇a)增加產生驅動第一子 9 13537201353720 VI. Description of the invention: August 18, pp. 18 曰Revision replacement page | Technical Field of the Invention The present invention relates to a single-ended transmission type D amplifier, and more particularly to a single-ended output type D of a double feedback differential loop. Amplifier. [Prior Art] In general, the amplifier circuit of the output stage includes amplifiers of Class A, Class B, Class AB, and Class D. The early common ones are ab amplifiers, but the semiconductor process is mature and has a lower level. Class D amplifiers that consume power are becoming more common. The biggest difference between a class D amplifier and a class AB amplifier is that the output pulse width modulation signal pushes the inductive load instead of being driven by a linear signal; wherein the pulse width modulation signal includes an acoustic signal and a pulse width modulation switching signal. Wave signal. Since the class D amplifier outputs a pulse width modulation signal, the switches of the output stage switching circuit are switched from a high impedance to a very low impedance, and the on-time is short, so that the on-current flows through the on-resistance time is relatively shortened, and is more than the Ab-type amplifier. Efficiency and consume less power. Referring to FIG. 5, it is a single-ended output type D amplifier (70) having an open circuit. The class D amplifier (70) includes a gain amplifier (71) and a PWM modulator (72). An oscillator (73), a logic circuit (74) and a half bridge circuit (75), wherein the gain amplifier (71) input terminal (vi) is connected to an external analog sound signal, and the external analog sound signal is given After amplification, as shown in the seventh figure, the amplified audio signal (v) is outputted by the corresponding PWM modulator (72) according to the oscillation signal (S2) output by the oscillator, and the pulse width modulation signal (P, N) is used. The logic circuit (74) controls the half bridge according to the pulse width modulation signal 3 1353720. The replacement page circuit (75) is opened and closed according to the circuit of the half bridge circuit, because the half bridge circuit is connected to the external inductive load (6〇). The inductive load (60) restores the sound signal. Since the oscillator signal output frequency of the oscillator is high, an audio signal of 20 Hz to 2 kHz is used as an example, and the oscillating signal used in combination is 350 kHz. Referring to the sixth figure, the PWM modulator (72) adds the amplified audio signal to the high-frequency oscillation signal for pulse width modulation of the pulse width modulation signal, so that the amplified sound signal can be included ( The noise (N1) in S1) is pushed to the high frequency band. Since the noise (N1) is shifted to the higher frequency band and the sound data (S1) is kept in the low frequency band, the class D amplifier (70) is output to Before the inductive load (60), the high frequency noise (N1) can be filtered out by the characteristic (81) of the low pass filter (8 〇). Since the single-ended output type D amplifier (70) can shift the noise to the high frequency band by the modulation technique, it must be combined with a high-order low-pass filter (80) to filter the noise in the 咼 band. The overall size of the circuit using a single-ended output type D amplifier cannot be miniaturized. Furthermore, since the gain amplifier (71) and the PWM modulator (72) each use an amplifier component, the noise floor of the amplifier itself is a kind of dynamic noise, so when an audio signal is input to the gain When the amplifier (71) is used, the dynamic noise is incorporated into the amplified audio signal, resulting in a poor total harmonic distortion plus noise ratio (THD+N) and signal distortion ratio (SDNR) of the final output signal. It is based on the 'single-ended output type D-type amplification l§(70 a) which has a closed feedback loop. Please refer to the eighth figure, which includes: A signal amplifier (71)' contains an analogy Input (乂丨) for analog audio signal input; a comparator (72), one input is connected to the signal amplifier (71) 4 1353720 August 18, 100 correction output page of the output 'other An input terminal is connected to a vibrator (73), and the amplified audio signal is compared with the oscillation signal to output a pulse width modulation signal; a logic circuit (74) is connected to the comparator (72) The output terminal outputs a driving signal according to the pulse width modulation signal; the half bridge circuit (75) is composed of an upper side switching circuit (751) and a lower side switching circuit (752), wherein the upper side and the lower side switching circuit (751, The control terminal of 752) is connected to the output end of the logic circuit (74) to receive the driving signal and to determine the opening and closing of the upper and lower switching circuits (7 5 1, 7 5 2 ), and the half bridge circuit ( 75) upper switch circuit (751) and lower switch circuit (752) The series node is the output of the class D amplifier (D〇), so it can be connected by an inductive load; and the first order feedback circuit (711) is connected to the series node of the half bridge circuit (75) and the signal amplifier (71) Analog input (Vi). The class D amplifier (70a) includes a first-order feedback circuit (71) for amplifying the gain amplifier itself, noise, reference voltage noise, gain/bandwidth product limitation, and feedback output signal of the nonlinear value of the triangular wave generator. The non-linear terms are eliminated. However, the first-order feedback loop combines the sound signals by a single signal amplifier and amplifies them, so the overall open loop gain is rather limited. SUMMARY OF THE INVENTION In view of the above problems, the main object of the present invention is to provide a single-ended output type sigma amplifier with dual feedback differential loops, which can provide a better noise distortion signal than 0 ' for the above purpose. The main technical means is to make the single-ended output 5 1353720 on August 18, 100. The single-ended wheel-out terminal connection of the modified-type D-type amplifier is modified & an inverter 7^ provides 3 differential output signal terminals; wherein the D The class amplifier comprises a gain adjustment circuit, a first order product, a comparator, a logic circuit and a half bridge circuit; wherein the second order integrator comprises: - the first differential amplifier comprises a positive input end An input terminal, a reverse differential wheel output terminal, and a forward differential output terminal, wherein the forward input terminal is coupled to the gain adjustment circuit ' to adjust a gain of the first differential amplifier; a first RC circuit Connected between the differential output signal terminal of the class D amplifier and the forward and reverse input terminals of the first differential amplifier II to form two sets of first order integration circuits; a second differential amplifier includes a forward input terminal, an inverting input terminal, wherein the forward input terminal is coupled to a forward differential output of the first differential amplifier, and the reverse turn input is coupled to a reverse of the first differential amplifier The differential output terminal and the second second RC circuit are respectively connected between the differential output signal terminal of the class D amplifier and the forward and reverse input terminals of the second differential amplifier to form two sets of second order integration circuits. Since the single-ended output type D amplifier has only a single output power supply inductive load connection, the present invention connects the inverter to the single output terminal, so that the sigma amplifier provides a set of differential output signal terminals, and can design a fully differential The circuit 'and a second-order integrator form a second-order feedback circuit to help the nonlinear components such as the first and second differential amplifiers to be attenuated more quickly, and to provide higher high-frequency attenuation values and improve overall noise. Distortion noise ratio; Furthermore, the differential output signal of the class D amplifier of the present invention can be more finely corrected after the secondary gain 6 1353720 is corrected on the replacement page of August 18, 100. In summary, the present invention not only integrates the fully differential circuit in the single-ended output type D amplifier, but also incorporates the first and second differential amplifiers into the second-order feedback system, thereby effectively eliminating the elimination of the nonlinear components, and Class D amplifiers are fully linearized' and relatively better total harmonic distortion plus noise ratio (THD+N) performance. The second object of the present invention is to provide a single-ended output type D amplifier capable of greatly reducing electromagnetic interference, that is, the high side switch group and the low side switch group of the above half bridge switch circuit are further divided into two groups of first and second sub-half a bridge circuit, wherein the number of high/low side switches of the first sub-half bridge circuit is greater than the number of high/low side switches of the second sub-half bridge circuit, wherein the event nodes of the first and second sub-half bridge circuits are connected to Single output of a Class D amplifier. The logic circuit outputs four sets of pulse width modulation signals to the half bridge circuit of the present invention, wherein the driving mode of the second sub half bridge circuit is unchanged, but the logic circuit generates a pulse width modulation for driving the first sub-half bridge circuit The logical operation type of the variable signal is: ="2_ Especially; corpse 1 = 'where X and Ν2 are the values of the differential signal of the differential output signal and the triangular wave signal. According to the logic calculation formula, when the differential output terminal of the class D amplifier has no output, χ*Ν2 will be completely the same, so that the pulseless width modulation signal is output to the first sub-car wipe m, which is in the ox bridge circuit. That is, the first sub-bridge with a large number of switches can say that the D-dry circuit does not operate when there is no signal output; and when the D-type amplifier has a signal output - ^ ^ a ^ the height of the first sub-peak bridge circuit / One of the low-side switch groups has an action .θ , and another operation, which can effectively reduce the switching of the half-bridge circuit and the output switch slew rate, which can reduce the overall D. The ΕΜί value of the class amplifier. 7 1353720 [Embodiment] 100 years of August 18 曰 correction replacement page May, as shown in the first figure, is a single-ended output type D amplifier (1〇) of the dual feedback differential loop of the present invention. The circuit block diagram includes a gain adjustment circuit (11), a second-order integrator, two comparators (3〇, 31), a logic circuit (40), a half bridge circuit (50), and an inverter (24). The half bridge circuit (50) comprises a high-side switch group (51) and a low-side switch group (52) connected in series, and the series node is a single-output (D〇) of the class D amplifier; The single-ended output terminal (D〇) of the single-ended output type (Do) is connected to the inverter (24) to provide a set of differential output signal terminals (D〇+D〇_). The second-order integrator includes: a first differential amplifier (20) comprising a forward input terminal, an inverting input terminal (-), a reverse differential output terminal (+), and a forward differential output. End (-), wherein the forward input terminal (+) is connected to the gain adjustment circuit (11)' to adjust the gain of the first differential amplifier (20); the second first RC circuit (21) is connected respectively To the differential output signal terminal (Do +, D0-) and the forward and reverse wheel terminals (+, -) of the first differential amplifier (2〇) constitute two sets of first-order integration circuits; The two differential amplifier (22) includes a forward input terminal (+) and an inverting input terminal (-)', wherein the forward input terminal (+) is connected to the forward direction of the first differential amplifier (20) a differential output terminal (+) connected to the opposite differential output terminal (_) of the first differential amplifier (20); and two second RC circuits (23) connected to the differential Two sets of second-order integration circuits are formed between the turn-off signal terminals (Do+, D0-) and the forward and reverse input terminals of the second differential amplifier (22) . The present invention connects the inverter (24) to the single output terminal (D〇), so that the single 8 1353720 modified on August 18, 100, replaces the page-end output type D amplifier (1〇) to provide t sets of differential output signals. ^ <Dd+'D0 ;)» constitutes a fully differential circuit, and with the second-order integrator, the C-order_circuit' helps the nonlinear components such as the noise of the first and second differential amplifiers (20, 22) themselves to be more Fast attenuation, as shown in the second figure and can provide a more abrupt high-frequency attenuation value, improve the overall noise distortion noise ratio (SDNR) 'again' the present invention 〇 class amplifier (1 〇) differential output signal (Do +, D0-) can be more finely corrected after the second gain processing; therefore, the present invention not only designs the fully differential circuit in the single-ended output type D amplifier, but also the first and second differential amplifiers (2〇) 22) Incorporate into the second-order feedback system, which effectively eliminates the elimination of nonlinear components, and makes the entire Class D amplifier fully linearized' and relatively better total harmonic distortion plus noise ratio (THD+N) performance. Single-Ended Output Class D Amplifier with Fully Differential Circuit Architecture Improves Power Supply Wave suppression ratio (p〇wer supply rejecti〇n rati〇n, PSRR) 'common mode rejection ratio (common mode rejection) and anti-crosstalk miscellaneous information (crosstalk noise rejection). Referring to FIG. 3 again, it is a second preferred embodiment of the single-ended output type D amplifier (10a) of the present invention, and most of the structures are the same as those of the first preferred embodiment. The high side switch group and the low side switch group of the 〇) are further divided into two sets of first and second sub-half bridge circuits (5〇a5〇b), wherein the high/low side switches of the first sub-half bridge circuit (50a) The number is higher than the number of high/low side switches of the second sub-half bridge circuit (50b), wherein the series nodes of the first and second sub-half bridge circuits (50a, 50b) are connected to the single output of the class d amplifier (Do ). The number of high/low side switches of the first sub-half bridge circuit (50a) is 3 to 5 times the number of high/low side switches of the second sub-half bridge circuit (50b). Furthermore, the logic circuit (4〇a) of the embodiment increases the drive to generate the first sub 9 1353720
I 100年8月1日修正替換頁I 半橋電路（50a)二組之脈寬調變訊號之邏輯運算式，係分別 為m = m-x反n = x_m，其中X及N2為差分輪出訊號端之 差分訊號與三角波訊號比較後的數值。 請配合第四A圖所示，由於雙反饋差分迴路設計，當d 類放大器（10)輸出大訊號時，本發明的二組比較器（3〇, 31) 會取得差分訊號（V-，V+) ’並分別與三角波訊號（S2)進行比 較，以輸出第二子半橋電路（50b)的二組脈寬調變訊號 (N2，P2)及一組參考脈寬調變訊號（X)。當邏輯電路（4〇)接收 到此N2，P2兩組脈寬調變訊號後會直接輸出至第二子半橋 電路（50b)’再依據參考脈寬調變訊號（X)及其中一組脈寬調 變訊號（N2)帶入上述邏輯運算式，輸出第一子半橋電路的二 組脈寬調變訊號（N1，P1)。誠如本圖所示，當d類放大器（i〇b) 有訊號輸出時，第一子半橋電路（50a)的高侧開關組及低側 開關組僅其中一組有動作。 再如第四B圖所示，當D類放大器（1〇b)單輸出端（D〇) 無輸出時，X及N2會完全相同，使得無脈寬調變訊號輸出 至第一子半橋電路（50a)，即N1呈低電位而P1呈高電位， 令第一子半橋電路（50a)的高側開關及低側開關均關閉不導 通。因此，本發明即能讓開關數量多的第一子半橋電路（5〇a) 在無訊號輸出時不作動，而在D類放大器（1〇a)有訊號輸出 時，第一子半橋電路（5〇a)的高側開關組及低側開關組僅其 中組有動作；是以，能有效降低半橋電路的切換損失及 輸出刀換迴轉率（outPut switch slew rate)，可降低整體d類 放大器的EMI值。 以上所述僅是本發明的較佳實施例而已，並非對本發 1353720 一 100年8月18日修正替拖百 明做任何形式上的限制，雜妙·士改:— -- 雖，，、、' 本發明已以較佳實施例揭露 如亡’然而並非用以限定本發明，任何熟悉本專業的技術 人員’在不脫離本發明技術方案的範圍内，當可利用上述 揭示的技術内容作出些許更動或修飾為等同變化的等效實 施例’但凡是未脫離本發明技術方案的内纟依據本發明 的技術實質對以上實施例所作的任何簡單修改、#同變化 與修飾，均仍屬於本發明技術方案的範圍内。 【圖式簡單說明】 第一圖：係本發明第一較佳實施例的電路方塊圖。 第二圖：係第一圖輸出放大聲音訊號之頻域圖。 第二圖·係本發明第一較佳實施例的電路方塊圖。 第四A、B圖：第三圖的波形圖。 第五圖：係一種開迴路的單端輸出型D類放大器電路 方塊圖。 第六圖：係第五圖輸出放大聲音訊號之頻域圖。 第七圖：係第五圖的波形圖。 第八圖：係一種閉迴路的單端輸出型D類放大器電路 方塊圖》 【主要元件符號說明】 (10)(10a)D類放大器 （11)增益調整電路 (20)第一差分放大器 （21)第一 RC電路 (22)第二差分放大器 （23)第二RC電路 1353720 100年8月18曰修正替換頁 (30)比較器 (31)比較器 (32)三角波產生器 (40)(40a)邏輯電路 (50)半橋電路 (50a)第二子半橋電路 (50b)第一子半橋電路 (51)高側開關組 (52)低側開關組 (60)電感性負載 (70)(70a)D類放大器 (701)差分放大器 (71)增益放大器 (72)PWM調變器 (73)振盪器 (74)邏輯電路 (75)半橋開關 (751)高側開關組 (752)低侧開關組 (80)低通濾波器 12I. August 1, 100 Correction Replacement Page I The half-bridge circuit (50a) of the two sets of pulse width modulation signal logic, respectively, m = mx anti-n = x_m, where X and N2 are differential round-trip signals The value of the difference signal between the terminal and the triangular wave signal. Please cooperate with the fourth A diagram. Due to the dual feedback differential loop design, when the class D amplifier (10) outputs a large signal, the two sets of comparators (3〇, 31) of the present invention will obtain a differential signal (V-, V+). ] ' and compare with the triangular wave signal (S2) to output two sets of pulse width modulation signals (N2, P2) of the second sub-half bridge circuit (50b) and a set of reference pulse width modulation signals (X). When the logic circuit (4〇) receives the N2, P2 two sets of pulse width modulation signals, it will directly output to the second sub-half bridge circuit (50b) and then according to the reference pulse width modulation signal (X) and one of the groups. The pulse width modulation signal (N2) is brought into the above logic operation formula, and outputs two sets of pulse width modulation signals (N1, P1) of the first sub-half bridge circuit. As shown in this figure, when the class d amplifier (i〇b) has a signal output, only one of the high side switch group and the low side switch group of the first sub-half bridge circuit (50a) has an action. As shown in Figure 4B, when the single-output (D〇) of the class D amplifier (1〇b) has no output, X and N2 will be identical, so that no pulse width modulation signal is output to the first sub-half bridge. The circuit (50a), that is, N1 is at a low potential and P1 is at a high potential, so that the high side switch and the low side switch of the first sub-half bridge circuit (50a) are both turned off and not turned on. Therefore, the present invention enables the first sub-half bridge circuit (5〇a) having a large number of switches to be inactive when no signal is output, and the first sub-half bridge when the class D amplifier (1〇a) has a signal output. The high-side switch group and the low-side switch group of the circuit (5〇a) have only a group of actions; that is, the switching loss of the half-bridge circuit and the output switch slew rate can be effectively reduced, thereby reducing the overall The EMI value of the class d amplifier. The above description is only a preferred embodiment of the present invention, and is not intended to impose any form limitation on the modification of the stipulation of the stipulation of the stipulation of the stipulation of the stipulation of the stipulation of the stipulation of the stipulation of the stipulation of the stipulation of the stipulation of The present invention has been disclosed in the preferred embodiments, but is not intended to limit the invention. Any skilled person in the art can make use of the technical contents disclosed above without departing from the scope of the present invention. </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Within the scope of the inventive solution. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram of a first preferred embodiment of the present invention. The second picture is the frequency domain diagram of the first picture output amplified sound signal. Figure 2 is a block diagram of a circuit of a first preferred embodiment of the present invention. Figure 4A, B: Waveform of the third figure. Figure 5: Block diagram of a single-ended output type D amplifier circuit with open circuit. Figure 6: The frequency map of the amplified audio signal in the fifth diagram. Figure 7: The waveform diagram of the fifth diagram. Figure 8: Block diagram of a closed-loop single-ended output type D amplifier circuit [Explanation of main components] (10) (10a) Class D amplifier (11) Gain adjustment circuit (20) First differential amplifier (21) ) First RC circuit (22) Second differential amplifier (23) Second RC circuit 1353720 100 August 18 曰 Correction replacement page (30) Comparator (31) Comparator (32) Triangle wave generator (40) (40a Logic circuit (50) Half bridge circuit (50a) Second sub-half bridge circuit (50b) First sub-half bridge circuit (51) High-side switch group (52) Low-side switch group (60) Inductive load (70) (70a) Class D Amplifier (701) Differential Amplifier (71) Gain Amplifier (72) PWM Modulator (73) Oscillator (74) Logic Circuit (75) Half Bridge Switch (751) High Side Switch Group (752) Low Side switch block (80) low pass filter 12