TWI352946B - Display panel and flat panel display - Google Patents

Description

Howling 946

: 3⁄4 No.: TW2759PA IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a flat-panel display and a voltage-axis flat-panel display with a resolution. η----[Previous technique] Increasing the _ shadow riding scale low hardware cost riding face to raise the competitiveness of the important subject. The device that promotes the analysis of financial value: _ Drives the drive output and display memory of 1C, so that the cost is increased. [The content of the invention] = This: The purpose of the invention is to provide a display panel and The display panel with the invention and the flat display system with the same can have the riding degree and smoothness of the four sides, and the display effect. At the same time, in accordance with the purpose of the present invention, a flat panel display comprising a gold matrix, a data driver and a biasing device is provided. Data Drives Package :: Multiple Blocks of Second Element. The second element of each column is located adjacent to each other; and between two: two: the resource driver is used to output a plurality of data signals to the first element: two sets: to be respectively coupled to the second element. Each biasing device is used to poll the data signal according to the adjacent two reading signals to the second-column in the second column. Each of the biasing systems includes: a first load: a knife - a second load component - a load component and a second load component - end to the poor charge driver - for receiving the corresponding two adjacent data signals :Information 6 1352946,

Sanda number: TW2759PA *· ' Signal. The other end of the second load component is coupled to the other end of the first load component for outputting the corresponding bias data signal. According to another object of the present invention, a display panel is provided comprising: a substrate, a halogen matrix, and a plurality of biasing means. The halogen matrix is disposed on the substrate. The halogen matrix system includes a plurality of columns of the first element and a plurality of columns of the second element. The first element of each column receives the data signal, and the second element of each column is located between the first two elements in the adjacent two columns. A plurality of biasing devices are also disposed on the substrate and are respectively connected to the second pixels of each column. Each biasing device is configured to output a bias data signal to the second element in the first column of the corresponding two blocks according to the adjacent two data signals φ. Each biasing device includes a first load element and a second load element. The first component of the load component is configured to receive one of the corresponding two adjacent data signals. One end of the second load component is configured to receive another data signal corresponding to the two adjacent data signals. The other end of the second load component is coupled to the other end of the first load component for outputting a corresponding bias voltage. Information signal. The above-mentioned objects, features, and advantages of the present invention will become more apparent from the following description of the preferred embodiments. 'Using the principle of the voltage division of the load element to achieve the improvement of the kneading resolution and the smoothing of the kneading surface. Referring to FIG. 1A, a block diagram of a planar display circuit in accordance with a preferred embodiment of the present invention is shown. The flat panel display 1 is, for example, a (960 (RGB) * 640) voltage-driven flat panel display including a data driver 106, a scan driver 1 8 and a display panel 109. And the display panel 1〇9 is a package 7 1352946 .

The . 达达号: TW2759PA includes a substrate (Substrate) 109a, biasing devices 112(1) to 112(480), and a reference matrix 114. The pixel matrix 114 includes 481 blocks of the first pixels Cl(l)~ci(481;) and 480 columns of the second elements C2(l)~C2(480). The second halogen C2 is between the adjacent first pixels C1 of the two blocks. Each of the first halogen elements ci includes a first red halogen CR1, a first green pixel CG1, and a first blue pixel CB1, and each of the first halogen C2 also includes a second red halogen CR2 and a second green halogen. CG2 and the second blue halogen CB2. ~~ • In the embodiment, the flat panel display 100 has 481 columns of the first pixel C1 and 480 columns of the second pixel C2 as an example for convenience of explanation. Although the total number of pixels in the matrix of the matrix 112 is 961, the actual resolution of the flat panel display is approximately 960 pixels. It is of course also possible to use the second element C2 of the 481 —---C1 and 479 columns to achieve the desired resolution of 96 〇 * 64 。. The data driver 106 is configured to output 481 sets of data signals SD(1) to SD(481) to drive the first pixels C1(1) to C1(481), respectively. Data signal SD(i)~ • SD(481) is a voltage signal. Each data signal SD includes red, green and blue data Bfl numbers SDR, SDG and SDB to drive the corresponding red, green and blue lights respectively. CR, CG and CB. The biasing device 112(j) (j = 480) is responsible for the data signals SD(j) and SD(j + l) of the first and second elements C1(j) and Cl(j + 1) And according to the output bias data signal SB (j) to the second element C2 (j). The sweep driver 108 is configured to output 640 scan signals s(l)~S(640) in sequence to enable the first pixels Cl(i)~Cl(481) and the second halogen C2(1) C2 in each column. (48〇) to 1352946,

- Sanda number: TW2759PA Receives the output of the poor material driver 106, respectively, the Shenke 4 magazine Beike signal SD (1) ~ SDC481) and the biasing device 112 (1) ~ 112 (48ίη ^ mountain, (48U) output bias The data signals SB(1) to SB(480). In addition, as shown in FIG. 1B, each biasing device 112(1) further includes a red biasing unit (10) (1), a green biasing unit (10) (1), and a blue biasing unit. Π 2 Β (1) for Receive two adjacent red, green, and blue data signals SDR(1) and SDR(j + I), SDG(j) and SDG(j + 1), and (4) (1) and SDB(8), respectively, and output red, green, and blue biases accordingly. Press the data signal • Which (1), Na (1), and SBB (1) to the corresponding second red, green, and blue halogen CR2 (j), CG2 (j), and CB2 (j). Among them, the red, green and blue partial units 112R, 112G and 112B have similar circuit structures and operating modes. The following is a description of the biasing device 112 (j) n-color bias material U2R (1), and the circuit structure and operation mode of the other green biasing unit 112G (j) and the blue biasing unit 112B ( j) can be analogy. Please refer to FIG. 2, which is a circuit block diagram of the red bias unit 112R (J·) in FIG. 1B. Red bias unit 112R(j) includes load elements 202a(j) and 202b(j). The load elements 2〇2a(J·) and 2〇2b(J·) are preferably Thin Film Transistors (TFTs), and in this embodiment, N-type gold oxide half (N-type) Metal Oxide Semiconductor, NMOS) field effect transistor as an example. The drains Da and Db of the load elements (transistors) 2〇2a(j) and 202b(j) are coupled to the data driver 106 for receiving the red data signals SDR(j) and SDR(j+1), respectively. The source Sa of the load element (transistor) 2〇2a(j) is coupled to the negative 1352946.

Sanford No.: TW2759PA. The source Sb of the carrier (transistor) 202b(j) is formed to form an output node NT. The operation signal SG' is, for example, a DC voltage signal 15V, which is input to the gates Ga and Gb of the load elements (transistors) 202a(j) and 202b(j) to turn on the load elements (transistors) 202a(j) and 202b. (j), biasing the potentials of the red data signals SDR(j) and SDR(j+1) by the rounding node NT to output the red bias data signal SBR(j) to the second element C2(j).

According to the voltage division principle, the voltage level of the red bias data signal SBR(]·) is interpolated between one of the red data signals SDR(j) and SDR(j + l) voltage levels. In fact, the voltage value of the bias data signal SBR (SBG or SBB) is determined by the equivalent impedance of the load elements (transistors) 202a(j) and 202b(j). Therefore, the load elements (transistors) 2〇2a(j) and 202b(j) can be changed by adjusting the channel width and length ratios of the load elements (transistors) 2〇2a(J·) and 2〇2b(j). The impedance value, and then adjust the voltage value of the bias data signal. The voltage values of the bias data signals SBR(j), SBG(j) or SBB(j) are preferably data signals SDR(j) and SDR(j+1), SDG(j) and SDG(j + l). ) or the intermediate value of SDB(j) and SDB( j + 1). Since the brightness of the image displayed by adjacent red (green or blue) pixels must have a continuous relationship, the two adjacent components are used by two load elements (transistors) 2〇2&〇) and 2〇2b(j). The bias data signal SB(j) generated by the voltage division of the signals SD(1) and SD(j + 1) will drive the second element C2 (D provides the first-halogen C1(j) and C1(j + 1) The red (green or blue) image of the party's degree enables the flat panel display (10) to simultaneously improve the resolution and smooth the surface. In addition, the above-mentioned operation woven SG can also be a kind of voltage-seeking signal. 1352946,

' · Sanda number: TW2759PA ' For example, alternately providing GV and two voltage levels can reduce the stress effect (Stress Effect) of load components (transistors) 2G2a ( j) and 2G2b (; j) The effect of the boundary voltage value to improve the life of the load components (1) and (1). Moreover, the load elements 2〇2a(j) and 202b(j) of the biasing skirt 112 may also use, for example, a gift element or other load-carrying element having a biasing function. As long as the adjacent two pure video bits can be divided to provide a bias data signal corresponding to the second pixel, the resolution of the display can be provided without departing from the technical scope of the present invention. • The data driver 1〇6 in this embodiment is a data driver including a 480*3 channel. The scan driver 1〇8 is a scan driver including a 64-inch channel. The halogen matrix 1U is composed of 960 (RGB) * 640 elements, and the volume of the body is 480 * 640 * 16 bits (Bit). Therefore, the resolution of the flat panel display can be increased by a factor of 2 without increasing the memory volume. Similarly, it is also possible to reduce the required memory capacity without increasing the resolution. half. Refer to Figure 3 for the month, which shows the analog timing diagram of the Smart Simulation Program with Integrated Circuit Emphasis 'Smart Spice' in the red-biased data signal of Figure 2 The aiming time is 20 microseconds (# sec). The flat panel display has a frame rate of 60 Hz and a broom time of 26 sec. This embodiment simulates a 26 microsecond scan time of a flat panel display with a shorter 2 sec microsecond scan time. The aspect ratio (W/L) of the load elements (transistors) 2〇2a(j·) and 2〇2b(j) are both 2000/5. The operation signal SG is a DC voltage of 15 volts. 1352946

:Development number: TW2759PA • Red data signals SDR(j) and SDR(j + 1) are voltage values every 2〇. In the time 〇"%0 to 1〇〇"sec, red changes from SDR(j) to 1 volt, 2 volts, 3 volts, 4 #,, 'X color information, 4 volts, $ Your strong data signal SDR (jH) is 〇 volt, ^ 仇特. Red 0 volts. The red bias data signal SBR (』·) is sequentially volts, volts, 2 volts, 3. 5 Volt, 2.3 volts., ' 3. 2 The simulation results show that the red biasing unit consisting of two aspect ratio (W/L) phases (transistor lion (1) fiber (1) == can provide normal Driving the second red pixel 邙 2 (]) J) signal fi)) ^ red bias unit 112R (D output red signal SBR (j) is substantially equal to the red data signal SDR (j) & When the aspect ratios of the load components 202a(j) and 202b(j) are 1000/5 and 2000/5 respectively, the operation signal SG is still a DC voltage of 15V. Red data signals SDR(j) and SDR(j + l) Change the voltage value every 2Msec. Similarly, from the computer simulation result in Figure 4, the red bias data signal generated by the red bias single το 112R(j) is still in phase. Neighbor two red information SDR (j) and SDRU + 1) between the levels, but not exactly the middle of the latter two. However, it can effectively achieve the effect of smoothing the display screen and improving the resolution of the display. Figure 5 shows the second The red bias data signal SBR(j) of the figure is the Smart Spice analog timing chart when the operation signal SG is the AC voltage signal of each half cycle of the high and low level. The sixth figure shows the red bias data signal SBK of the second figure. (j) At the intersection of the operation signal SG at the high and low levels of 3/4 and 1/4 cycle respectively

12 1352946 .

- Three-face number: Smart Spice analog timing chart for TW2759PA flow voltage signal. The red data says that SDR(j) and SDR(j + Ι) still change the voltage every 200 // sec. It can be seen from FIG. 5 and FIG. 6 that the red bias unit 112R(j·) can still generate a bias data signal between the adjacent two red data signals SDR(j) and SDR(_j+1). SBR (j) voltage value. Therefore, it is also possible to achieve the effect of smoothing the surface and improving the resolution of the display. The operation signal SG using the AC voltage can solve the problem that the stress effect causes a shortened life of the bias unit. The flat-panel display disclosed in the embodiment has a simple structure and a biasing device for inserting another data signal according to two adjacent data signals, thereby effectively improving the resolution of the flat display without increasing the memory capacity. The smoothing effect of the facet, or the effective reduction of the required memory volume without increasing the resolution, and thereby reducing the manufacturing cost of the display, solves the problem of the complicated structure and cost of the conventional flat display. According to the conventional computer shown in Figs. 7A and 7B and the same computer simulation surface of the present invention, it is assumed that the original display body is 128 (RGB) * 128, and the number of channels of the data driver is 64 柁, so in the conventional ♦ In the computer simulation plane of the flat display, one data line displays two data lines to generate the required 128 (RGB) * 128 resolution, as shown in Fig. 7A: The pressure device 112 is adjacent to the two data lines i to obtain new data line data. The simulation display result is as shown in Fig. 7B, and the display effect of the resolution and smoothing is obviously seen. In view of the above, the present invention is disclosed in a preferred embodiment as described above, but it is not intended to limit the invention, and any person skilled in the art can make various kinds without departing from the scope of the invention. Change and retouch, so the invention ^ ^

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Sanda number: TW2759PA Included in the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Circuit block diagram. Figure. The brother "", 曰不不弟1B diagram red bias unit (10) (1) circuit block diagram red bias data _ ()) one of the spice simulation timing diagram. Figure 4 is an analog timing diagram of another Smart spice of the red bias data signal SBR(j) not shown in Figure 2. (4) Draw the red bias data signal sbr (d in the second picture). The Smart Spice analog timing chart when operating the AC voltage signals of the low-level one-half cycle. diT: Figure 6 shows q Signal SG is the red bias signal of the high and low maps. SBR(1) is the Sman spice analog timing diagram when operating # Γ respectively for 3/4 and 1/4 cycle AC voltage signals. Figure 7A and 7r & Computer Simulation The figure shows the tradition and the surface of the invention.

- Sanda number: TW2759PA. [Description of main component symbols] 100: Flat panel display 102: Data line 104 • Broom line 106 • Lean drive driver 108: Broom driver 109 • Display panel 109a: Substrate 112 (1) ~ 112 (480): biasing devices 112R (j), 112G (j), 112B (j): red, green, blue bias - · early 114: halogen matrix

Cl(l)~Cl(481): first halogen CR1(]·), CGl(j), CBl(j): first red, green, blue halogen C2(l)~C2(480): Second halogen CR2 (j), CG2 (j), CB2 (j): second red, green, blue halogen SD (1) ~ SD (481): data signal SDR (j), SDG (j) , SDB (] ·): red, green, blue data signal SB (1) ~ SB (480): bias signal SBR (j), SBG (j), SBB (j): red, green, blue Pressure data signals 202a(j), 202b(j): load elements Da, Db: no poles Ga, Gb: gates 15 1352946.

' . Sanda number: TW2759PA ' · Sa, Sb : source SG : operation signal NT : node

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Claims (1)

1352946 . • Revised replacement page on July 12 of the following year, the scope of patent application: 1. A flat panel display comprising: a substrate; a Pixel Matrix disposed on the substrate, the pixel - The matrix includes a plurality of first pixels and a plurality of second pixels, wherein each of the blocks is located between the first two adjacent columns; a data driver for outputting a plurality of data And the plurality of biasing devices are disposed on the substrate, and are respectively coupled to the second pixels of the columns, wherein the biasing devices are configured to be adjacent to each other The two data signals output a bias data signal to the second pixel in the first column of the corresponding two columns, wherein each of the biasing devices comprises: a first load component, one end of the first load component The data driver is coupled to the data driver for receiving one of the two adjacent data signals; and a second load component, the one end of the second load component is coupled to the data driver for receiving the corresponding Two adjacent data The other end of the signal is coupled to the other end of the first load element for outputting the corresponding bias signal. 2. The flat panel display as described in claim 1 is a Voltage Driven flat panel display. 3. The flat panel display of claim 1, wherein the first load component and the second load component are a first thin film transistor (TFT) and a second thin film transistor, respectively. . </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Receiving corresponding two adjacent data signals respectively, wherein an output end of the first transistor is coupled to the second thin film transistor, and the control terminal of the second-crystal transistor and the second thin film transistor are The control terminal is connected to the operating voltage. 5. The flat panel display according to claim 4, wherein the operating voltage is -DC voltage, and each of the first (four) receiving portions of the first thin film transistor and the second In the thin film electric can, the operation is as follows: The voltage system described in item 4 of the patent application is - Hyun. Among them, the seventh paragraph, such as the scope of patent application! The flat panel display unit and the second load component are both a resistive component &amp; as claimed in the patent scope! In the flat panel display, the first element includes a first red halogen, a first, and each of the five colored pixels, each of the second pixels comprising a second red halogen, and two: The second blue-blue and the second blue halogen, the data driver is _, red, the red-red element, and outputs a green data signal to the first:) a blue data signal to the first a blue book +, each "eight-denier and red-transfer unit, - green bias unit and - blue bias unit bias f-unit: the first-load element and the second load element are received; two colors Two adjacent red (four) signals are outputted according to the red red bias 2, the second red halogen, the first negative drain 5_ of the green bias unit, and the corresponding two load components are received corresponding to the adjacent two green Information:, =, and the first Bellow signal and according to the rotation of a 1.529496, July 12, 100 correction replacement page green bias data signal to the corresponding second green element, the blue bias unit § 苐 苐 a load component and the second load component receive corresponding two adjacent blue data signals A blue-biased data signal is outputted to the corresponding second blue pixel. 9. The flat-panel display of claim 1, wherein each of the bias data signals is substantially The flat display of the two adjacent data signal levels, wherein the number of the first pixels of the first pixel is similar to the second element. 11. A display panel comprising: a substrate; a Pixel Matrix disposed on the substrate, the pixel matrix comprising a plurality of pixels in a plurality of columns and a second pixel in the plurality of pixels The first element receives a data signal, and each of the second elements is located between two adjacent first pixels; and a plurality of biasing devices are disposed on the substrate. Each of the biasing devices is coupled to the second data element of the two columns, and the biasing device is configured to output a bias data signal according to the adjacent two data signals to the first pixel of the corresponding two shelves. Two pixels, wherein each of the biasing devices comprises: a load component, one end of the first load component is configured to receive one of the corresponding two adjacent data signals; and a second load component, the end of the load component is configured to receive the corresponding The other two adjacent data signals, the data signal 'the other end of the second load component is coupled to the other end of the first load component, for outputting the corresponding 1352946 • * July 12 revision replacement page The display device of the invention, wherein the first load element and the second load element are respectively a first thin film transistor (Thin Film Transistor 'TFT). And a second thin film transistor. The display panel of claim 12, wherein one input end of the first thin film transistor and one input end of the second thin film transistor respectively receive corresponding two adjacent data signals, the first An output end of the thin film transistor is coupled to an output end of the second thin film transistor, and one of the control ends of the first thin film transistor and one of the control ends of the second thin film transistor are coupled to an operating voltage. 14. The display panel of claim a, wherein the operating voltage is a DC voltage, and when each of the biasing devices receives the corresponding data §fl5, corresponding to the first Both the thin film transistor and the second thin film electromorphic system are in a conducting state. The display panel of claim 13, wherein the operating voltage is an alternating voltage. 16. The display panel of claim U, wherein the first load element and the second load element are each a resistive element. The display panel of claim 11, wherein each of the first elements comprises a first red halogen, a first green halogen and a first blue halogen, each of which The second pixel includes a second red halogen, a second green halogen, and a second blue halogen. The first red, the first green, and the first blue crystal respectively receive a red data. a signal, a green data signal and a blue data signal, each of the biasing devices comprising a red biasing unit, a green biasing unit and a blue eccentric unit and the first load of the red biasing unit Component and 20 1352946 The second load component receives the corresponding request - 丨 _ 7 shirt correction replacement page out - red bias data signal to _ I red # material signal and according to the transmission unit of the first - load component and material Color pixel, the green bias two green data signals and according to the output 'green two: connect: the corresponding adjacent junction - recognize a &gt; support the bias bias signal to the corresponding words,,,,,,,, The first load component of the color control bias unit and the ^2^:: receiving Corresponding two adjacent blue data signals are outputted according to a color bias data signal to the corresponding second blue book element. Color 18. The display panel according to the scope of claim U, == The material signal level is essentially the corresponding two adjacent data signals. twenty one