1352355 九、發明說明： 【發明所屬之技術領域】 本案是關於一種讀取非揮發性記憶體的方法，特別 是關於一種在電源開通階段讀取非揮發性記憶體中資料 的方法。 ' 【先前技術】 非揮發性記憶體為一種將電源關掉也能繼續保存所 圮憶貧料的半導體元件。非揮發性記憶體包括幕罩唯讀 记憶體(Mask ROM)、可程式唯讀記憶體(pR〇M)、可抹 除可程式唯讀記憶體(EPROM)或電性可抹除可程式唯讀 記憶體(EEPROM)。快閃記憶體(Flash mem〇ry)可視為$ 性可抹除可程式唯讀記憶體的一種。 非揮發性記憶體的控制器可參考一參考電壓， =-帶^考電壓，以在—字元線中產生—控制信號 的準位，來對非揮發性記憶體實施程式化、抹除、驗噔 ^讀取的操作。帶隙參考電壓為—與溫度無關的參考^ 壓，例如，其電麼大小在1.25伏特附近。 由於製程與不同的晶片t會使帶隙參考電壓產生變 異，故在晶圓分類的階段需要修正帶隙參考電壓。一種 =方法為利用―參考暫存器以選擇適合 得帶隙參考電壓為正確。 使 由於非揮發性記憶體中的資料是根據帶隙參考雷厭 =加=程式化、抹除、驗證或讀取；因此，在讀取操作 、，设置所要感測記憶胞所對應字元線的操作電壓，、使 5 是在程式化與抹除狀態的中間，如此， 即可達成可靠的讀取操作。 如此 „通階段讀取一非揮發性記憶體的—先 :揭路於美國專利公開案US2⑻細1377A1中= 域#愔栌銼六士 為二域記憶體，而其中第二區 的資‘ 訊；依序讀取三健域記憶體中 H ’並__先私的三觸應 對以實施驗證。 只了寸作比 然而’利用保險絲記憶體儲存組態資訊，並在電 所觀⑽的正雜，需魏外增加保險 絲1體脸制，造賴__性敎。險 °月參閱第一圖，其為習用非揮發性記憶體在電源開 通階段之電源電壓隨著時間的變化圖。如圖所示，從 源電壓馳加轉揮發性記，隨至電源電㈣達電源開 ，重置凡成電壓的電壓範圍，對應於電源開通重置階 奴，在經過電源開通重置階段後，電源電壓依然在上升 中，且電壓在上升過程中也許有不穩定的變動現象。 ▲，了加速載入非揮發性記憶體中已預先程式化好的 、:’且態貝a到資訊暫存器中’於是在電源電壓開始超過電 源開通重置完成電壓後，就開始讀取非揮發性記憶體中 的组態資訊並加以驗證，以便存入資訊暫存器中。由於 電源電壓的上升與擾動現象，所讀取的組態資訊會有錯 誤的潛在風險。 請參閱第二圖，其為習用非揮發性記憶體系統的讀 取操作衫方塊圖。在第二财，非揮發性記憶體系統 賴3卜—料電録生器32及 扣，性記億體31中儲存資料 考暫產生器32包括儲存一修正碼3211的-參 in射修正碼3211預設為-内定值；參考 提供生—參考_ VRT並將其 帶隙參考_:生器二吝的參考電麗產生器32為-考電壓。生器’其所產生的參考電壓為-帶隙參 5己憶體控制器33接收參考電壓V咖，並藉由參考電 非揮發性記憶體31中的㈣311，以獲得讀 凊參㈣三圖’其為f用電關通階段讀取一 =記憶體巾資料的示意流程圖。所要讀取的該資料為 办子於例如，一快閃記憶體陣列中的組態資訊；而一 >考電麗產生n巾的—參考暫存器已預先存有一内定 值。在步驟搬巾，當一電源開始接通時，非揮發性記 憶體所施加-電源電壓從零開始上升，同時進入電源開 通，置階段；當電源電壓開始超過—電源開通重置完成 電壓時，電源開通重置階段結束，且電源開通 憶體讀取開始β 在步驟404中，參考電壓產生器根據内定值產生一 參考電壓，並將其提供給一記憶體控制器。在讀取過程 中，以位址為順序讀取非揮發性記憶體中的該資料，此 處設定一目前位址編號ADDR，其為可變的；而共有q 4址中的該資料需要續取，且從位址〇(ADDr=〇)開始 ^序讀取。所讀取的該資料需要驗證其正確性，而立中 二種驗證的方法是先賴Q錄址巾料另存於非 ，發性記憶體中的Q個對應位址而成為備份資料，且設 ^該資料與所對應的該備份資料之間對應有相反的位元 =。另外’設定-成功次數PCNT，其為可變的且表示 目刖成功讀取的次數，並預設為〇。 在步驟406 + ’記憶體控制器藉由參考電壓讀取該 ^個位址中對應於目前位址的—第—子資料，且獲得一 果，其中第一子資料為非揮發性記憶體中該 触’、的個。同理接著，記憶體控制器在非揮發性記惊 體中的-對餘址藉岭考讀取_份資料二 第-子備份資料，且獲得—第二讀取結果， 備份資料對應於第一子資料。 、 千 在步驟侧中，比較第一讀取結果與第二讀取 =取結果與第二讀取結果為互補時，所得的:果證 …果為真，當第一讀取結果與第二讀取結果不 時’結果為假。當驗證結果為真時，孰步驟41〇 ; ^ 證結果為假時，回到步驟406 〇 田 在步驟410中，將成功次數PCNT加1，以成為— 成功次數，且將新成功次數再存為成功次數PCNT。 在步驟412中，檢查成功次數PCNT是否達 定次數P ’其中預定次數p表示該資料巾的每—子= 所欲的成功讀取次數；當成功次數pcNT等於p時，= 到預疋次數P為真，於是進入步驟4M;當成功次數吻τ 1352355 小於P時，達到預定次數P為假，於是回到步驟楊。 *在步驟414巾，將‘該資料中驗證結果為真實的正確 讀取結果m崎存H ;其中-種#訊暫存器為一 靜態隨機存取記憶體。 在步驟416巾’檢查下一位址是否超過所要讀取的 位址；當目前健編號ADDR等於p時，超過所要讀取 的位址為真，於是進人步驟㈣；#目前健編號addr 小於p時，超過所要讀取的位址為假，於是進入步驟418。 在步驟418巾，將目前位址編號ADDR加卜以成 為一新目前位址編號，且將新目前位址編號再存為目前 位址編號ADDR ;再者，將成功次數pCNT重設為〇且 回到步驟406。 在步驟420中，將資訊暫存器中已暫存的資料傳送 至需要資料的一周邊裝置。 在上述的讀取流程中，為了保證所讀出的資料為正 確，而設有步驟406、步驟408、步驟410與步驟412的 一錯誤位元檢查階段，以確保所讀取的組態資訊為可靠。 無論如何，由於參考暫存器中的内定值並非最終的 修正碼，此未修正的帶隙參考電壓可能偏離目標值(例如 1.25)太多，導致在電源電壓到達最終的穩定準位時，錯 誤位元檢查階段可能還沒有結束。 因此’需要提供一個電源開通階段能準確地讀取非 揮發性記憶體中組態資訊的方法。 【發明内容】 9 1352355 本案之一目的為提出一種讀取一非揮發性記憶體中 資料的方法，用以達成電源開通階段有效與準確地讀取 非揮發性記憶體中組態資訊的功效。 本案之一構想為提出一種讀取一非揮發性記憶體中 資料的方法，包括下列步驟：藉由一參考電壓讀取該資 料，當該讀取步驟具有一失敗結果時，計算一失敗次數； 及，當失敗次數達到一第一預定次數時，調整參考電壓。 本案之另一構想為提出一種讀取一非揮發性記憶體 中資料的方法，包括下列步驟：藉由一參考電壓讀取該 _貝料，及，當該讀取步驟具有一失敗結果時，調整參考 電壓。 【實施方式】 為了敘述清楚本案所提的方法，下面列舉數個較佳 實施例加以說明： 請參閱第四圖，其為本案所提讀取一非揮發性記憶 體中資料的第一示意流程圖。在步驟502中，適用於開 1讀取的情況有兩種；第一種情況是在一電源開通階 ^亦即，當非揮發性記憶體所施加的一電源電壓超過 電源開通重置完成電壓時，讀取該資料的流程開始； 第二種情況是在一穩定狀態，亦即，當非揮發性記^體 所施加的電源電壓是正常且穩定時，讀取該資料的^程 開始。 在步驟504中，設定一失敗次數ECNT，其為可變 的且表示目前失敗讀取的次數，並預設為〇。 10 在步驟506中，藉由一第一參考電壓讀取非揮發性 記憶體中的該資料，所讀取的該資料，例如，為組態資 訊；而該第一參考電壓，例如，為與溫度無關的一帶隙 參考電壓。將所讀取的該資料加以驗證且獲得一驗證結 果。 在步驟508中，檢查驗證結果；當驗證結果為假時， 步驟506具有一失敗結果，於是進入步驟510。 在步驟510中，計算失敗次數ECNT，亦即，將失 敗次數ECNT加1，以成為一新失敗次數，且將新失敗 次數再存為失敗次數ECNT。 在步驟512中，檢查失敗次數ECNT是否達到一預 定次數E;當失敗次數ECNT等於E時，達到預定次數E 為真，於是進入步驟514;當失敗次數ECNT小於E時， 達到預定次數E為假，於是回到步驟506。 在步驟514中，調整第一參考電壓為一第二參考電 壓。 在步驟516中，將失敗次數ECNT重設為0且回到 步驟506。 請參閱第五圖，其為本案所提讀取一非揮發性記憶 體中資料的第二示意流程圖。在步驟602中，適用於開 始讀取的情況有兩種；第一種情況是在一電源開通階 段，亦即，當非揮發性記憶體所施加的一電源電壓超過 一電源開通重置完成電壓時，讀取該資料的流程開始； 第二種情況是在一穩定狀態，亦即，當非揮發性記憶體 所施加的電源電壓是正常且穩定時，讀取該資料的流程 丄力2355 開始。 在步驟604中，藉由一第一參考電壓讀取 魏體中的該㈣；將所讀取的該資料加以驗證^ 一驗證結果。 D 谩侍 在步驟606中，檢查驗證結果；當驗證結果為假 步驟604具有-失敗結果，於是進入步驟_。又崎’ 在步驟608中，調整第一參考電壓為一第二參 壓；接著，回到步驟604。 ^電 =參閱第六圖’其為本案所提讀取—非揮發性記修 體中貝料的第三示意流程圖。在步驟7〇2中，適用於％ =讀取的情況有兩種；第—種情況是在—電源開通: 又亦即，當非揮發性記憶體所施加的一電源電壓 -電源開通重置完成電壓時，讀取該資料的流程開始° 第二種情狀在-穩定狀態，亦即，t非揮發性記^ 所施加的魏縣是正常且敎時，讀取該資料的ς 開始。 1不至 在步驟704中，在一參考電壓產生器中的—參考 存器中的一數碼BCODE是可調整的且具有一内定值〇臀 參考電壓產生器根據數碼BC〇DE產生一參考電壓，並 將其提供給一記憶體控制器。在讀取過程中，以位址為 順序讀取非揮發性記憶體中的該資料，此處設定一目前 位址編號ADDR，其為可變的；而共有q個位址中的診 資料需要讀取’且從位址〇(ADDR=〇)開始依序讀取。^ 讀取的該資料需要驗證其正確性，而其中一種驗證的方 法是先將該Q個位址中的該資料另存於非揮發性記憶體 12 1352355 中的Q個對應概而成騎份資料，且設定該資料盘所 對應的該備份資料之間對應有相反的位元準位。、科， 設定-成功:緣腦τ，其射_且衫目前成功讀取 的次數，並預設為G;設定-失敗次㈣㈣，其為可變 的且表示目前失敗讀取的次數，並預設為〇。 在步驟706巾，記憶體控制器藉由參考電壓讀取該 Q個位址帽應於目前位址的—第—子㈣，且獲得一 第-讀取結果D1A ’其中第—子#料為轉發性記憶體 中該資料的-個。同理接著，記憶體控制器在非揮發性 s己憶體17的-對應位址藉纟參考電壓讀取該備份資料中 的一第厂子備伤資料’且獲得~第二讀取結果DIB，其 中第一子備份資料對應於第一子資料。 、 在步驟708中，比較第一讀取結果D1A與第二讀取 結果DIB ;當第一讀取結果DlA與第二讀取結果DlB 為互補時，所得的驗證結果為真；當第一讀取結果D1A 與第二讀取結果DIB不是互補時，結果為假。當驗證結 果為真時，進入步驟718 ;當驗證結果為假時，進入步驟 710。 在步驟710中，將失敗次數ECNT加丨，以成為一 新失敗次數，且將新失敗次數再存為失敗次數ECNT。 在步驟712中，檢查失敗次數£(：]^11是否達到一預 定次數E，其中預定次數E表示該資料中的每一子資料 失敗讀取的臨界次數；當失敗次數ECNT等於E時，達 到預定次數E為真，於是進入步驟714;當失敗次數ECNT 小於E時，達到預疋次數E為假，於是回到步驟706。 13 1352355 調整 器根 記憶 在步驟714 t，將數碼BC〇DE加卜以成為一 值，且將調整值再存為數碼BC〇DE。參考電壓產 據數碼BCODE產生-新參考電壓，並將其提供汰 體控制器，且將新參考電麗改名為參考電屋。、、° 在步驟716中，將成功次數PCNT重設為〇且 敗次數ECNT重設為〇 ;接著，回到步驟观。將失 在步驟718中，將成功次數扣沿加1，以成為 成功次數’且賴成功缝再存城功缝Pd 在步驟720中’檢查成功次數PCNT是否達到 定次數P，其中預定次數P表示該資料中的每-子資料 所欲的成功讀取次數；當成功次數pCNT等於p時，逵 到預定次數P為真，於是進入步驟722，其中預定次數p 不小於預定次數E ;當成功次數PCNT小於p時， 預定次數P為假，於是回到步驟7〇6。 當成功次數PCNT小於p且再次於步驟7〇6中， 憶體控制H藉由參考電壓讀取該Q個位址中對應 乂 位址的第—子資料’域得—第三讀取結果mI ;、同二 接著，記憶體控制器在非揮發性記憶體中的對應位址藉 由參考電壓讀取該備份資料中的第—子備份資料，且獲 得一第四讀取結果D2B。 & 在步驟722中，將該資料中驗證結果為真實的正確 讀取結果寫入一資訊暫存器。1352355 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a method of reading non-volatile memory, and more particularly to a method of reading data in a non-volatile memory during a power-on phase. [Prior Art] Non-volatile memory is a semiconductor component that can continue to store the poor material when the power is turned off. Non-volatile memory includes mask ROM (Mask ROM), programmable read-only memory (pR〇M), erasable programmable read-only memory (EPROM), or electrically erasable programmable Read only memory (EEPROM). Flash mem〇ry can be viewed as a type of sexually erasable programmable read-only memory. The controller of the non-volatile memory can refer to a reference voltage, =- with a voltage to generate a control signal level in the word line, to program, erase, and erase the non-volatile memory. Check the operation of the ^ reading. The bandgap reference voltage is a temperature-independent reference voltage, for example, whose magnitude is around 1.25 volts. Since the process and the different wafers t will cause the bandgap reference voltage to vary, the bandgap reference voltage needs to be corrected at the wafer sorting stage. One = method is to use the “reference register” to select the appropriate bandgap reference voltage. The data in the non-volatile memory is stylized, erased, verified, or read according to the bandgap reference. Therefore, in the read operation, the word line corresponding to the sensed memory cell is set. The operating voltage is such that 5 is in the middle of the stylized and erased states, so that a reliable read operation can be achieved. So, the first stage of reading a non-volatile memory - first: the United States Patent Publication US2 (8) fine 1377A1 = domain #愔栌锉六士 is a two-domain memory, and the second area of the information The three-touch response of H' and __ privately in the three-dimensional memory is sequentially read to perform verification. Only the inch is used, however, the configuration information is stored by the fuse memory, and the positive view of the device (10) is performed. Miscellaneous, need to increase the fuse outside the fuse body 1 body face, rely on __ sex. Risk ° month refer to the first picture, which is the conventional supply of non-volatile memory in the power-on phase of the power supply voltage as a function of time. As shown in the figure, from the source voltage to the volatility record, as the power supply (four) reaches the power supply, resets the voltage range of the voltage, corresponding to the power supply reset reset slave, after the power-on reset phase, The power supply voltage is still rising, and the voltage may be unstable during the rising process. ▲, Accelerated loading non-volatile memory has been pre-programmed, 'and state a to information temporary storage In the device, then the power supply voltage begins to exceed the power supply. After resetting the voltage, the configuration information in the non-volatile memory is read and verified for storage in the information register. The configuration information is read due to the rise and disturbance of the power supply voltage. There is a potential risk of error. Please refer to the second figure, which is a block diagram of the reading operation of the conventional non-volatile memory system. In the second fiscal, the non-volatile memory system relies on the material recording device. 32 and buckle, the sex storage unit 31 stores the data test temporary generator 32 including a correction code 3211 - the reference inject correction code 3211 is preset to - the default value; the reference provides the raw - reference _ VRT and its band gap Reference_: The reference device 32 of the generator diode is a test voltage. The reference voltage generated by the generator is - the band gap parameter 5 the memory controller 33 receives the reference voltage V coffee, and by reference (4) 311 in the electrically non-volatile memory 31, to obtain a reading 凊 ( (4) three diagrams, which is a schematic flow chart for reading a = memory towel data during the electrical shutdown phase of f. The data to be read is a For example, a configuration information in a flash memory array; and a > The battery has been pre-stored with a default value. In the step of moving the towel, when a power supply starts to be turned on, the non-volatile memory is applied - the power supply voltage rises from zero, and the power is turned on. When the power supply voltage begins to exceed the power-on reset complete voltage, the power-on reset phase ends, and the power-on memory begins reading β. In step 404, the reference voltage generator generates a reference voltage according to the default value. And providing it to a memory controller. During the reading process, the data in the non-volatile memory is read in the order of the address, where a current address number ADDR is set, which is variable. The data in the shared q 4 address needs to be renewed, and the data is read from the address 〇 (ADDr=〇). The data read needs to verify its correctness, and the method of verifying the two is First, the Q address book is stored in the non-issued memory, and the Q corresponding addresses are used as backup data, and the corresponding data and the corresponding backup data have opposite bits =. In addition, the 'set-number of successes PCNT, which is variable and indicates the number of successful readings, is preset to 〇. In step 406, the 'memory controller reads the first-sub-data corresponding to the current address in the address by the reference voltage, and obtains a result, wherein the first sub-data is in non-volatile memory. The one that touches '. Similarly, the memory controller in the non-volatile signature body - the remaining address of the ridge test read _ data two first-sub backup data, and obtain - the second read result, the backup data corresponds to the first A sub-data. In the step side, when comparing the first reading result with the second reading=taking result and the second reading result being complementary, the obtained result is: the fruit is true, when the first reading result is the second The result is false from time to time. When the verification result is true, step 41〇; ^ When the result of the verification is false, return to step 406. In the step 410, Putian increments the number of successes PCNT by 1 to become the number of successes, and saves the number of new successes. The number of successes is PCNT. In step 412, it is checked whether the number of successes PCNT reaches a certain number of times P', wherein the predetermined number of times p represents the number of successful readings per sub-substitute of the data towel; when the number of successes pcNT is equal to p, = the number of pre-twisting times P To be true, then proceed to step 4M; when the number of success kisses τ 1352355 is less than P, the predetermined number of times P is false, and then returns to step Yang. * In step 414, the result of the verification in the data is true. The correct reading result is m. In the case, the -# register is a static random access memory. In step 416, the towel 'checks whether the next address exceeds the address to be read; when the current health number ADDR is equal to p, the address beyond the address to be read is true, so the entry step (4); #current health number addr is less than When p, the address to be read is exceeded, and then proceeds to step 418. In step 418, the current address number ADDR is added to become a new current address number, and the new current address number is saved as the current address number ADDR; further, the success number pCNT is reset to 〇 and Go back to step 406. In step 420, the temporarily stored data in the information register is transferred to a peripheral device that requires the data. In the above-mentioned reading process, in order to ensure that the read data is correct, an error bit checking phase of step 406, step 408, step 410 and step 412 is provided to ensure that the read configuration information is reliable. In any case, since the default value in the reference register is not the final correction code, this uncorrected bandgap reference voltage may deviate too much from the target value (eg 1.25), resulting in an error when the supply voltage reaches the final stable level. The bit check phase may not be over yet. Therefore, it is necessary to provide a method for accurately reading the configuration information in the non-volatile memory during the power-on phase. SUMMARY OF THE INVENTION 9 1352355 One object of the present invention is to provide a method for reading data in a non-volatile memory to achieve effective and accurate reading of configuration information in non-volatile memory during the power-on phase. One aspect of the present invention is to provide a method for reading data in a non-volatile memory, comprising the steps of: reading the data by a reference voltage, and calculating a number of failures when the reading step has a failure result; And, when the number of failures reaches a first predetermined number of times, the reference voltage is adjusted. Another idea of the present invention is to provide a method for reading data in a non-volatile memory, comprising the steps of: reading the _ bead by a reference voltage, and when the reading step has a failure result, Adjust the reference voltage. [Embodiment] In order to clarify the method proposed in the present invention, several preferred embodiments are described below. Please refer to the fourth figure, which is the first schematic flow of reading data in a non-volatile memory. Figure. In step 502, there are two cases applicable to the open 1 reading; the first case is when a power supply is turned on, that is, when a power supply voltage applied by the non-volatile memory exceeds the power-on reset completion voltage The process of reading the data begins; the second case is a steady state, that is, when the power supply voltage applied by the non-volatile memory is normal and stable, the process of reading the data begins. In step 504, a number of failures ECNT is set, which is variable and represents the number of times the current failed read, and is preset to 〇. In step 506, the data in the non-volatile memory is read by a first reference voltage, and the read data is, for example, configuration information; and the first reference voltage is, for example, Temperature-independent bandgap reference voltage. The data read is verified and a verification result is obtained. In step 508, the verification result is checked; when the verification result is false, step 506 has a failure result, and then proceeds to step 510. In step 510, the number of failures ECNT is calculated, i.e., the number of failures ECNT is incremented by one to become a new number of failures, and the number of new failures is again stored as the number of failures ECNT. In step 512, it is checked whether the number of failures ECNT reaches a predetermined number of times E; when the number of failures ECNT is equal to E, the predetermined number of times E is true, then proceeds to step 514; when the number of failures ECNT is less than E, the predetermined number of times E is false Then, return to step 506. In step 514, the first reference voltage is adjusted to a second reference voltage. In step 516, the number of failures ECNT is reset to zero and returns to step 506. Please refer to the fifth figure, which is a second schematic flow chart for reading data in a non-volatile memory. In step 602, there are two cases suitable for starting reading; the first case is a power-on phase, that is, when a power supply voltage applied by the non-volatile memory exceeds a power-on reset completion voltage When the process of reading the data begins, the second case is a steady state, that is, when the power supply voltage applied by the non-volatile memory is normal and stable, the process of reading the data is started at 2355. . In step 604, the (4) in the body is read by a first reference voltage; and the read data is verified to verify the result. D 谩 In step 606, the verification result is checked; when the verification result is false, step 604 has a - failure result, and then proceeds to step _. In step 608, the first reference voltage is adjusted to a second voltage; then, returning to step 604. ^Electricity = Refer to the sixth diagram, which is a third schematic flow chart of the beaker in the non-volatile recording body. In step 7〇2, there are two cases for %=reading; the first case is—power-on: that is, when a non-volatile memory is applied to a power supply voltage-power-on reset When the voltage is completed, the flow of reading the data begins. The second situation is in the steady state, that is, when the Wei County, which is applied by the non-volatile memory, is normal and 敎, the reading of the data begins. 1 not in step 704, a digital BCODE in the reference buffer in a reference voltage generator is adjustable and has a default value. The hip reference voltage generator generates a reference voltage according to the digital BC 〇 DE, And provide it to a memory controller. During the reading process, the data in the non-volatile memory is read in the order of the address, where a current address number ADDR is set, which is variable; and a total of q addresses need to be diagnosed. Read ' and read sequentially from address 〇 (ADDR=〇). ^ The data read needs to be verified for correctness. One of the verification methods is to save the data in the Q addresses to the Q corresponding to the non-volatile memory 12 1352355. And setting the backup data corresponding to the data disk corresponding to the opposite bit level. , Section, Set-Success: The cerebral τ, its _ and the number of times the shirt is currently successfully read, and preset to G; set-fail times (four) (four), which is variable and indicates the number of failed reads, and The default is 〇. In step 706, the memory controller reads the Q address caps by reference voltage to the current address - the first sub-four, and obtains a first-read result D1A 'where the first-sub-material is One of the data in the forward memory. Similarly, the memory controller reads a first factory sub-injury data in the backup data by using the reference voltage of the non-volatile suffix 17 - and obtains the second read result DIB. The first sub-backup data corresponds to the first sub-data. In step 708, the first read result D1A and the second read result DIB are compared; when the first read result D1A and the second read result DlB are complementary, the obtained verification result is true; when the first read When the result D1A is not complementary to the second read result DIB, the result is false. When the verification result is true, the process proceeds to step 718; when the verification result is false, the process proceeds to step 710. In step 710, the number of failures ECNT is incremented to become a new number of failures, and the number of new failures is again stored as the number of failures ECNT. In step 712, it is checked whether the number of failures £(:]^11 reaches a predetermined number of times E, wherein the predetermined number of times E represents a critical number of times each sub-data in the data fails to be read; when the number of failures ECNT is equal to E, The predetermined number of times E is true, then proceeds to step 714; when the number of failures ECNT is less than E, the number of pre-emption times E is false, and then returns to step 706. 13 1352355 The adjuster root memory is added in step 714 t, the digital BC 〇 DE is added Bu will become a value, and the adjustment value will be saved as digital BC〇DE. The reference voltage is generated according to the digital BCODE-new reference voltage, and it is provided to the body controller, and the new reference battery is renamed as the reference house. In step 716, the number of successes PCNT is reset to 〇 and the number of failures ECNT is reset to 〇; then, returning to step view 718. In step 718, the number of successes is increased by one to become The number of successes 'and the successful sewing re-storage power Pd in step 720 'checks the success number of times PCNT reaches a fixed number of times P, wherein the predetermined number of times P represents the number of successful readings per sub-data in the data; The number of successes pCNT is equal to p When the predetermined number of times P is true, then the process proceeds to step 722, wherein the predetermined number of times p is not less than the predetermined number of times E; when the number of successes PCNT is less than p, the predetermined number of times P is false, and then returns to step 7〇6. PCNT is less than p and again in step 7〇6, the memory control H reads the first sub-data of the corresponding address in the Q addresses by the reference voltage—the third reading result mI; Secondly, the memory controller reads the first sub-backup data in the backup data by the reference voltage in the corresponding address in the non-volatile memory, and obtains a fourth read result D2B. & In the data, the verification result in the data is true and the correct reading result is written into an information register.
在步驟724 + ’檢查下一位址是否超過所要讀取的 位址；當目前位址編號ADDR等於p時，超過所要讀取 的位址為真，於是進入步驟728 ;當目前位址編號ADDR 1352355 小於p時，超過所要讀取的位址為假，於是進入步驟726。 在步驟726中，將目前位址編號ADDR加j，以成 為一新目前位址編號，且將新目前位址編號再存為目前 位址編號ADDR ;再者，將成功次數PCNT重設為〇且 將失敗次數ECNT重設為〇 ;接著，回到步驟706。 在步驟728中，將資訊暫存器中已暫存的資料傳送 至需要資料的一周邊裝置。 唯，以上所述者僅為本案之較佳實施例，舉凡熟悉 本案技藝之人士，在爰依本案精神所作之等效修飾^ 化，皆應涵蓋於以下之申請專利範圍内。 本案得藉由下列圖式之詳細說明，俾得更深入之瞭 解： ’、 【圖式簡單說明】 第一圖：其為習用非揮發性記憶體在電源開通階段之電 源電壓隨著時間的變化圖； 第二圖：其為f用非揮發性記憶體系制讀取操作示意 方塊圖； " 第二圖.其為制電關通階段讀取—非揮發性記憶體 中資料的示意流程圖； 第四圖.本案所提讀取一非揮發性記憶體中資料的第一 不意流程圖； 第五圖.本案所提項取一非揮發性記憶體中資料的第二 不意流程圖；及 第六圖：本案所提讀取一非揮發性記憶體中資料的第三 1352355 示意流程圖。 【主要元件符號說明】 30 :非揮發性記憶體系統 31 :非揮發性記憶體 311 :資料 32 :參考電壓產生器 321 :參考暫存器 3211 :修正碼 33 :記憶體控制器 Vref :參考電壓 331 :讀取結果 ADDR:目前位址編號 Q:位址總數 PCNT :成功次數 ECNT :失敗次數 P、E :預定次數 BCODE :數碼 D1A、DIB、D2A、D2B :讀取結果In step 724 + 'Check if the next address exceeds the address to be read; when the current address number ADDR is equal to p, the address beyond the address to be read is true, then proceeds to step 728; when the current address number is ADDR When 1352355 is less than p, the address that exceeds the address to be read is false, and then proceeds to step 726. In step 726, the current address number ADDR is added to j to become a new current address number, and the new current address number is saved as the current address number ADDR; further, the success number PCNT is reset to 〇 And the number of failures ECNT is reset to 〇; then, return to step 706. In step 728, the temporarily stored data in the information register is transferred to a peripheral device that requires the data. The above descriptions are only the preferred embodiments of the present invention. Those who are familiar with the art of the present invention should be included in the scope of the following patents in the spirit of the present invention. The case can be further explained by the detailed description of the following figures: ', [Simple description of the diagram] The first picture: it is the variation of the power supply voltage of the conventional non-volatile memory during the power-on phase. Figure 2: Figure 2 is a block diagram of the read operation of the non-volatile memory system; "Second figure. It is the schematic diagram of the reading in the power-off phase - the flow of data in non-volatile memory The fourth figure. The first unintentional flow chart for reading the data in a non-volatile memory in this case; the fifth picture. The second unintentional flow chart of the data in the non-volatile memory in the case mentioned in the present case; Figure 6 is a schematic flow chart of the third 1352355 for reading data in a non-volatile memory. [Main component symbol description] 30 : Non-volatile memory system 31 : Non-volatile memory 311 : Data 32 : Reference voltage generator 321 : Reference register 3211 : Correction code 33 : Memory controller Vref : Reference voltage 331: Read result ADDR: current address number Q: total number of addresses PCNT: number of successes ECNT: number of failures P, E: predetermined number of times BCODE: digital D1A, DIB, D2A, D2B: reading result