TWI351732B - Method of forming semiconductor isolation structur - Google Patents

Method of forming semiconductor isolation structur Download PDF

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TWI351732B
TWI351732B TW96140941A TW96140941A TWI351732B TW I351732 B TWI351732 B TW I351732B TW 96140941 A TW96140941 A TW 96140941A TW 96140941 A TW96140941 A TW 96140941A TW I351732 B TWI351732 B TW I351732B
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layer
substrate
dielectric layer
isolation structure
forming
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TW96140941A
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Chinese (zh)
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TW200919629A (en
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Shing Yih Shih
Po Yi Li
Chih Huang Wu
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Nanya Technology Corp
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1351732 九、發明說明: 【發明所屬之技術領域】 j明係關於:種半導體隔離結構的形成方法,特別是關於 八有/冓渠之半導體隔離結構的形成方法。 、 【先前技術】 以作半導體_結構之技術至対兩種,—種為區域石夕 乳化法(LOCGS) ’另-種錢_(STI)餘。區域魏化法 展的麟,其係先叫幕敍絲輯,雜再以高溫加 …基板以軸使魏化層_各主_域。由㈣域魏化法 氧化層很容易向外擴張而縮小主動區域面積,所以,隨 权麟,之後發展岭__妨便逐漸取 然而在淺_製程中’溝渠填__會隨著元件尺寸的縮 =、,而越來越因難,因此需要開發新的技術或填洞材料,以聚石夕 見烧旋塗玻璃(p〇lySilazane S0G)材料,可以達到很好的填洞效 果’但其仍有很多整合性的問題有待克服。舉例而言,如圖i所 不’-般淺隔離製祕以預先形細案化罩幕⑴作遮蔽進行钱 ^成溝渠H’賴喊溫錄化法方式於罩幕和表面形成 氧化層’再填入聚石夕氮烧旋塗玻璃⑽細丨泣咖犯⑺材料然 後=經固化(curing)程序後’最後進行平坦化(CMp)介電層12於 溝^ 11中為使介電層12與基板13高度相同,通常會回餘掉 部分之介電層12。依據實作結果,回蝕掉一部分之介電層12 後’麵的介電層12絲面於#近罩幕1G之難處會呈現凹陷 的結構(如箭頭所指之處)。這樣的結構又稱為斷皮(divot)。在後 進而造 種新穎的方法來改善習知 的多晶魏金屬層可能會填入此斷皮處, 成不正常的辦魏。因此 Κ 之淺隔離製程。 【發明内容】 :學試劑處理步驟,在後續回峨可= 推習知問題產生为因,_ a μ # 熱氧化方她之矽氧疋罩幕1〇之側壁表面上經高溫 子益㈣h ^氧物分子(如® 2A所示)與介電層12之分 刻的鍵結,導致兩者之界面的結構較為脆弱。當触 時’此界面結構的侧速報快,所以才會有斷皮 發明,發Μ之^法可以改善斷象的原理 ,被認為是本 如开Μ οτΓί劑可以使罩幕10表面上石夕氧化物分子親水化,例 12 i Μ ▲(如圖2Β所示)。經由此化學試劑處理步驟,介電層 Μ丨、*⑥1G之側壁可形成良好的鍵結’而使兩者之界面結構的 、、;ς與’丨電層12之蝕刻速率一致,斷皮現象即可獲得改善。 &,Τα^施例,本發明係提供一種半導體隔離結構的形成方 様匕3提供-基板;形成一圖案化犧牲層於基板上;以圖案化 祕3作為雜侧基板⑽成—溝渠;形成—襯底氧化層共形 覆,溝渠;以一化學試劑處理基板;以一介電層填充溝渠以形 '半‘體Ρπ離結構;及射彳介電層以使介電層之頂表面低於圖案 化犧牲層之頂表面。 13517321351732 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method for forming a semiconductor isolation structure, and more particularly to a method for forming a semiconductor isolation structure of an octagonal/drain. [Prior Art] As a semiconductor-structure technology, there are two kinds of techniques, namely, the regional eve emulsification method (LOCGS) ‘the other money _(STI). The lining of the regional Weihua method is called the syllabary series, and the high-temperature addition of the substrate is used to make the Weihua layer _ each main _ domain. The oxide layer of the (four) domain Weihua method is easy to expand outward and reduce the active area. Therefore, with Quanlin, the development of the ridge will gradually take place. However, in the shallow process, the 'ditch fill__ will shrink with the size of the component. =,, and more and more difficult, so it is necessary to develop new technology or fill the hole material, to use the stone to see the spin-coated glass (p〇lySilazane S0G) material, can achieve a good hole filling effect 'but it still There are many integration issues to be overcome. For example, as shown in Figure i, the shallow isolation system uses a pre-formed mask (1) as a mask to carry out the money. The water is formed into a trench. Refill the polyglycol sinter spin coating glass (10) fine weeping coffee (7) material and then = after the curing process 'final flattening (CMp) dielectric layer 12 in the trench 11 to make the dielectric layer 12 is the same height as the substrate 13, and usually a portion of the dielectric layer 12 is left back. According to the results of the implementation, the etch back of a portion of the dielectric layer 12 after the surface of the dielectric layer 12 has a concave structure (as indicated by the arrow) at the difficulty of the near-surface mask 1G. Such a structure is also known as a divot. Later, a novel method to improve the conventional polycrystalline Wei metal layer may be filled into the broken skin to become an abnormal Wei. Therefore, the shallow isolation process. [Summary of the Invention]: The reagent processing step can be used in the subsequent reaction to determine the cause of the problem, _ a μ #热氧化方, her 矽 矽 疋 疋 〇 〇 〇 〇 侧壁 侧壁 高温 高温 高温 高温 高温 高温 高温The bonding of the oxygen molecules (as shown in ® 2A) to the dielectric layer 12 results in a weaker interface between the two. When the touch time 'the side speed of this interface structure is reported fast, so there will be a broken skin invention, the method of hairpin can improve the principle of the broken image, it is considered that this is as open as the οτΓ 剂 agent can make the surface of the mask 10 The oxide molecule is hydrophilized, Example 12 i Μ ▲ (as shown in Figure 2Β). Through the chemical reagent treatment step, the sidewalls of the dielectric layer *, *61G can form a good bond ′, and the interface structure of the two layers is the same as that of the 丨 丨 丨 , , , You can get improvement. And the invention provides a semiconductor isolation structure forming a substrate 3 to provide a substrate; forming a patterned sacrificial layer on the substrate; and patterning the secret 3 as a hetero side substrate (10) into a trench; Forming a substrate oxide layer conformal, trench; treating the substrate with a chemical reagent; filling the trench with a dielectric layer to form a 'half' body Ρ π structure; and emitting a dielectric layer to make the top surface of the dielectric layer Below the top surface of the patterned sacrificial layer. 1351732

於另一實施例,本發明提供一種半導體隔離結構的形成方 法’包含提供一基板;形成一圖案化敗化層於基板上;以圖案化 氮化層作為遮蔽形成一溝渠於基板中;以一化學試劑處理圖案化 氮化層;以一介電層填充溝渠,以形成半導體隔離結構;及蝕刻 介電層以使介電層之頂表面低於圖案化氮化層之頂表面。 X 【實施方式】 以下將參考所附圖式示範本發明之較佳實施例。所附圖式中 相似元件係採用相同的元件符號。應注意為清楚呈現本發明,所 附圖式中之各it件並非按照實物之比例繪製,而且為避^模糊本 發明之内容,以下說明亦省略習知之零組件、相關材料、及其相 關處理技術。 ' 圖3至圖10顯示本發明之一第一實施例的製程流程剖面 圖。如圖3所述’提供-基板310並形成一圖案化犧牲層32〇於 基板則上。泰板310可為半導體元件製程中可形成溝渠的任何 基板’例如-雜板。圖案化犧牲層32〇可覆蓋主動區域係用 來定義後續所要形成之隔離溝_位^較麵言,圖案化犧牲 層320可包含-墊氧化層321及一氮化層322 ;塾氧化層32ι的 厚度約300埃,而塾氮化層322的厚度約麵至漏埃之間。 圖案化犧牲層320可藉由化學氣相沉積法及適當之微純 杳宕成。 1351732 310有向選擇性的钱刻方法來完成此步驟。較佳而言,此步驟係 使用乾式蝕刻以避免溝渠410向外擴開。溝渠410的深度視需求 而疋,通常越深隔離效果越好,但也會同時增加後續填溝的困難 度。 、 接著,如圖5所示,形成一襯底氧化層510共形地覆蓋溝渠 41〇。襯底氧化層510的形成目的在於修補形成溝渠41〇之蝕刻 所造成的損傷。較佳而言,襯底氧化層51〇的形成可藉由熱爐管 尚溫氧化方式,其厚度較佳約5〇埃至100埃之間。襯底氧化層 510之表面分子結構可參見圖2A。應注意,在此實施例中墊氮 化層322之側壁322a的表層形成在化學結構與襯底氧化層51〇 一樣的結構,在此結構中,其表層氧原子沒有多餘的鍵結空間。 由過去的技術資料中可得知,此時若填入介電層(如聚矽氮烧), 其附著力較差。 襯底氧化層510形成之後,將基板31〇浸泡於一化學試劑 中’可以將襯底氧化層510之表面化學結構變化成如圖6所示之 親水化表層610。在此結構中,其表層氧原子有可再鍵結的空間, 可以與介電層(如聚矽氮烧)鍵結而產生較佳的附著力。此化學試 劑可由任何可使襯底氧化層51〇親水化的化學成份來組成。較佳 而言’此化學試劑為一水性溶液;成分可選自以下所組成之群 組· NH4〇H、邮2、秘〇4及HC卜更佳而言,此化學試劑可為 混合HC卜氏〇2及氏〇 (比例為! : 4 : 5〇);混合朋4〇11、H2〇2 及=0(比例為1 : 4 : 2〇);或是混合氏3〇4與H2〇2的水溶液, 其/辰度比例可為16 : 1。浸泡時間一般而言約數分鐘左右即可。 親水化表層610之表面分子結構可參考圖2B。應注意,親水化 1351732 表層610係覆蓋墊氮化層322之侧壁322a。 接著’如圖7所示,填充一介電層710於溝渠410中以形成 隔離結構。介電層710的材質較佳為填洞能力良好的一旋塗玻 璃。更佳而言’介電層710可為極易與〇H基反應的旋塗玻璃, 如此介電層710即可與墊氧化層322之側壁322a上的襯底氧化 層610形成良好的鍵結。本實施例係使用包含(SiH2NH2)n之分 子結構的聚矽氮烷(Polysilazane)旋塗玻璃。應注意以旋塗玻璃作 為)|電層710,其在旋塗之後,通常需要再進行一道濕氧環境下 的硬化製程。 斤填充好介電層710之後’可利用習知之化學機械研磨技術將 塾氮化層322上方之多餘的介電層71〇、襯底氧化層51〇、及親 水化表層610去除。可以墊氮化層322作為此步驟的研磨終止 層。研磨後之結構如圖8所示。繼研磨步驟之後,可選擇性地進 行-回火步驟將介電層71G緊實化。回火可在含氮氧及水氣的 環境下於熱爐管中進行。 接著,執行一蝕刻介電層71〇的步驟,使介電層71〇的頂表 面與基板310之頂表面大致同高,或略低於基板31〇之頂表面。 可使用相對於圖案化犧牲層320及基板310,對介電層71〇有高 選擇性的綱方法來完成此步驟。較佳而言,此步驟係使用濕^ ,刻」其藥水J含氫氟酸或磷酸等成份。此步驟完成之結構㈣ 八戶1不m由於,過如®6所述之化學試麟理步驟, 二白層710與塾氧化層322之側壁322a上的襯底氧化層6】〇已 义好的鍵結,如圖8所示。所以,在執行圖9所示之侧步驟 13,51732 時’斷皮現象即可獲得改善❶ 然後,如圖10所示,可再逸^ 一 犧牲層32〇整體去除。此步驟可採 ^久刻步敎將圖案化 不會對基板3狀表面造成知之各種濕糊’其以 以上所述僅為本發明之較佳實施、In another embodiment, the present invention provides a method for forming a semiconductor isolation structure, which includes providing a substrate, forming a patterned defeat layer on the substrate, and patterning the nitride layer as a mask to form a trench in the substrate; The chemical agent treats the patterned nitride layer; the trench is filled with a dielectric layer to form a semiconductor isolation structure; and the dielectric layer is etched such that the top surface of the dielectric layer is lower than the top surface of the patterned nitride layer. X [Embodiment] Hereinafter, preferred embodiments of the present invention will be exemplified with reference to the accompanying drawings. Like components in the drawings have the same component symbols. It should be noted that in order to clearly illustrate the present invention, each of the components in the drawings is not drawn to the actual scale, and in order to avoid obscuring the contents of the present invention, the following description also omits the known components, related materials, and related processes. technology. 3 to 10 are cross-sectional views showing the process flow of a first embodiment of the present invention. The substrate 310 is provided as shown in Fig. 3 and a patterned sacrificial layer 32 is formed on the substrate. The Thai board 310 can be any substrate that can form a trench in a semiconductor component process, such as a miscellaneous board. The patterned sacrificial layer 32 〇 can cover the active region to define a subsequent isolation trench to be formed. The patterned sacrificial layer 320 can include a pad oxide layer 321 and a nitride layer 322; The thickness of the tantalum nitride layer 322 is approximately between the surface and the drain. The patterned sacrificial layer 320 can be formed by chemical vapor deposition and appropriate micro-pure. 1351732 310 has a selective money engraving method to complete this step. Preferably, this step uses dry etching to prevent the trench 410 from expanding outward. The depth of the trench 410 is ambiguous depending on the demand. Generally, the deeper the isolation effect, the better, but it also increases the difficulty of subsequent trench filling. Next, as shown in FIG. 5, a substrate oxide layer 510 is formed to conformally cover the trench 41. The substrate oxide layer 510 is formed to repair the damage caused by the etching of the trenches 41. Preferably, the substrate oxide layer 51 is formed by a thermal oxidation of the hot tube, preferably between about 5 angstroms and 100 angstroms thick. The surface molecular structure of the substrate oxide layer 510 can be seen in Figure 2A. It should be noted that the surface layer of the sidewall 322a of the pad nitride layer 322 in this embodiment is formed in the same structure as the substrate oxide layer 51, in which the surface oxygen atoms have no excess bonding space. It can be known from the past technical data that if a dielectric layer (such as polyfluorene) is filled in at this time, the adhesion is poor. After the substrate oxide layer 510 is formed, the substrate 31 is immersed in a chemical reagent. The surface chemical structure of the substrate oxide layer 510 can be changed to the hydrophilized surface layer 610 as shown in FIG. In this structure, the surface oxygen atoms have a re-bondable space, which can be bonded to a dielectric layer (such as polyfluorene) to produce better adhesion. This chemical agent can be composed of any chemical component which can hydrophilize the substrate oxide layer 51. Preferably, the chemical reagent is an aqueous solution; the component may be selected from the group consisting of NH4〇H, Post 2, Peru 4 and HC. Preferably, the chemical reagent may be a mixed HC. 〇2 and 〇 (proportion! : 4 : 5〇); mixed friends 4〇11, H2〇2 and =0 (ratio 1: 4: 2〇); or mixed 3〇4 and H2〇 The aqueous solution of 2 may have a ratio of 16:1. The soaking time is generally about a few minutes. The surface molecular structure of the hydrophilized surface layer 610 can be referred to FIG. 2B. It should be noted that the hydrophilized 1351732 skin layer 610 covers the sidewall 322a of the pad nitride layer 322. Next, as shown in FIG. 7, a dielectric layer 710 is filled in the trench 410 to form an isolation structure. The material of the dielectric layer 710 is preferably a spin-on glass having a good hole filling ability. More preferably, the dielectric layer 710 can be a spin-on glass that is highly reactive with the 〇H group, such that the dielectric layer 710 can form a good bond with the substrate oxide layer 610 on the sidewall 322a of the pad oxide layer 322. . This example uses a polysilazane spin-coated glass containing a molecular structure of (SiH2NH2)n. It should be noted that spin-on glass is used as the electrical layer 710, which typically requires a hardening process in a wet oxygen environment after spin coating. After filling the dielectric layer 710, the excess dielectric layer 71, the substrate oxide layer 51, and the hydrophilic surface layer 610 over the tantalum nitride layer 322 can be removed by conventional chemical mechanical polishing techniques. The nitride layer 322 can be padded as the polishing stop layer of this step. The structure after grinding is as shown in FIG. Following the grinding step, the dielectric layer 71G can be compacted by a selective tempering step. The tempering can be carried out in a hot furnace tube in an environment containing nitrogen and oxygen. Next, a step of etching the dielectric layer 71 is performed such that the top surface of the dielectric layer 71 is substantially the same as the top surface of the substrate 310 or slightly lower than the top surface of the substrate 31. This step can be accomplished using a method that is highly selective to the dielectric layer 71 with respect to the patterned sacrificial layer 320 and the substrate 310. Preferably, this step uses wet, engraving, and the syrup J contains components such as hydrofluoric acid or phosphoric acid. The structure completed in this step (4) Eight households are not due to the chemical test steps as described in ® 6, the two white layers 710 and the oxide layer of the substrate on the side wall 322a of the tantalum oxide layer 322 are as good as The key knot is shown in Figure 8. Therefore, an improvement can be obtained when the side step 13,51732 shown in Fig. 9 is performed, and then, as shown in Fig. 10, the sacrificial layer 32 can be removed as a whole. This step can be carried out for a long time, and the patterning will not cause various wet pastes on the surface of the substrate 3, which is only a preferred embodiment of the present invention.

,專利細,·凡其絲麟本 效改變或修飾,均應包含在下述之申請專·_。4之等 【囫式簡單說明】 圖1為以習知方法職淺溝魏騎構的剖面圖。 圖2Α為習知之罩幕表面分子結構示意圖。 圖2Β, patents are fine, and the changes or modifications of the sirolimus should be included in the following application. 4, etc. [Simplified explanation of the 囫 type] Fig. 1 is a cross-sectional view of the Weichao erecting structure by the conventional method. 2 is a schematic view showing the molecular structure of a conventional mask surface. Figure 2Β

【主要元件符號說明】 10 罩幕 12 介電層 310 基板 321 墊氧化層 322a側壁 510 襯底氧化層 710 介電層 11 溝渠 13 基板 320 圖案化犧牲層 322 墊氮化層 410 溝渠 610 親水化表層[Main component symbol description] 10 mask 12 dielectric layer 310 substrate 321 pad oxide layer 322a sidewall 510 substrate oxide layer 710 dielectric layer 11 trench 13 substrate 320 patterned sacrificial layer 322 pad nitride layer 410 trench 610 hydrophilized surface layer

Claims (1)

/52 /52 案號:96140941 100年6月7日修正-替換頁 +、申請專利範圍: 一種半導體隔離結構的形成方法,包含: 提供一基板; 形成一圖案化犧牲層於該基板上; 以該圖案化犧牲層作為遮蔽敍刻該基板以形成一溝渠; 形成一襯底氧化層共形地覆蓋該溝渠; 1-化學試触職基板,其巾該化學試舰概 層的表面親水化; ~ 之 頂表面 以;丨電層填充該溝渠以形成該半導體隔離結構丨及 餘刻該介電層以使該介電層之頂表面低於該圖案化犧牲層 2. 導體隔離結構的形成方法’其中該圖案 3. =2::=:離結構的形成方法’其㈣成該 5* 其中該化學 •11, 1351732 λ- 索號· 96140941 年6月7曰修正_替換頁 所述^半導體隔離結構的形成方^中^^ 捕係選自以下項目所組成之群組: 二中舰予 及 Ηα。 4〇ίί、h2〇2、h2so4 法,其中該介電 8' , 9· 如 坡1所述之半導體隔離結構的形成方法,其中今㈣ 哨為聚砂氣烧(p〇lySllazane)。 〃中碗塗 10. 如請求項彳 學機械研磨^之半導體隔離結構的形成方法’更包含一化 ^驟使該介電層與該圖案化犧牲層共平面。 -12-/52 /52 Case No.: 96140941 Modified on June 7, 100 - Replacement Page +, Patent Application Range: A method of forming a semiconductor isolation structure, comprising: providing a substrate; forming a patterned sacrificial layer on the substrate; The patterned sacrificial layer is used as a mask to engrave the substrate to form a trench; a substrate oxide layer is formed to conformally cover the trench; and a chemical test touch substrate is hydrophilized on the surface of the chemical test ship layer; The top surface is filled with a germanium layer to form the semiconductor isolation structure and the dielectric layer is left such that the top surface of the dielectric layer is lower than the patterned sacrificial layer 2. The method for forming the conductor isolation structure 'Where the pattern is 3. = 2::=: from the formation method of the structure' (4) into the 5* where the chemical•11, 1351732 λ- 索号·96140941 June 7曰 Amendment_Replacement page described ^Semiconductor The formation of the isolation structure is selected from the group consisting of: the second ship and the Ηα. 4〇ίί, h2〇2, h2so4 method, wherein the dielectric 8', 9· is a method for forming a semiconductor isolation structure as described in Slope 1, wherein the current (4) whistle is a p〇lySllazane. The bowl coating of the crucible 10. The method of forming the semiconductor isolation structure of the mechanical polishing apparatus is further included to make the dielectric layer coplanar with the patterned sacrificial layer. -12-
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106997845A (en) * 2016-01-19 2017-08-01 财团法人工业技术研究院 Flexible substrate repairing structure, manufacturing method and detection repairing method
TWI674045B (en) * 2016-01-19 2019-10-01 財團法人工業技術研究院 Flexible substrate with repair structure, manufacturing method thereof and method of inspection and repair of flexible substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106997845A (en) * 2016-01-19 2017-08-01 财团法人工业技术研究院 Flexible substrate repairing structure, manufacturing method and detection repairing method
TWI674045B (en) * 2016-01-19 2019-10-01 財團法人工業技術研究院 Flexible substrate with repair structure, manufacturing method thereof and method of inspection and repair of flexible substrate

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