TWI348097B - System, apparatus and method for predicating various types of accesses to a memory and for managing predications associated with a cache memory - Google Patents
System, apparatus and method for predicating various types of accesses to a memory and for managing predications associated with a cache memoryInfo
- Publication number
- TWI348097B TWI348097B TW094128055A TW94128055A TWI348097B TW I348097 B TWI348097 B TW I348097B TW 094128055 A TW094128055 A TW 094128055A TW 94128055 A TW94128055 A TW 94128055A TW I348097 B TWI348097 B TW I348097B
- Authority
- TW
- Taiwan
- Prior art keywords
- memory
- predications
- predicating
- accesses
- managing
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
- G06F9/3832—Value prediction for operands; operand history buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Debugging And Monitoring (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/920,682 US7461211B2 (en) | 2004-08-17 | 2004-08-17 | System, apparatus and method for generating nonsequential predictions to access a memory |
US10/920,995 US7260686B2 (en) | 2004-08-17 | 2004-08-17 | System, apparatus and method for performing look-ahead lookup on predictive information in a cache memory |
US10/920,610 US7441087B2 (en) | 2004-08-17 | 2004-08-17 | System, apparatus and method for issuing predictions from an inventory to access a memory |
US10/921,026 US7206902B2 (en) | 2004-08-17 | 2004-08-17 | System, apparatus and method for predicting accesses to a memory |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200619937A TW200619937A (en) | 2006-06-16 |
TWI348097B true TWI348097B (en) | 2011-09-01 |
Family
ID=36142947
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094128055A TWI348097B (en) | 2004-08-17 | 2005-08-17 | System, apparatus and method for predicating various types of accesses to a memory and for managing predications associated with a cache memory |
Country Status (4)
Country | Link |
---|---|
JP (1) | JP5059609B2 (zh) |
KR (1) | KR100987832B1 (zh) |
TW (1) | TWI348097B (zh) |
WO (1) | WO2006038991A2 (zh) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7636813B2 (en) * | 2006-05-22 | 2009-12-22 | International Business Machines Corporation | Systems and methods for providing remote pre-fetch buffers |
JP6252348B2 (ja) * | 2014-05-14 | 2017-12-27 | 富士通株式会社 | 演算処理装置および演算処理装置の制御方法 |
WO2016097809A1 (en) | 2014-12-14 | 2016-06-23 | Via Alliance Semiconductor Co., Ltd. | Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type |
KR101757098B1 (ko) * | 2014-12-14 | 2017-07-26 | 비아 얼라이언스 세미컨덕터 씨오., 엘티디. | 메모리 액세스에 의한 효용성 기반 공격성 레벨 프리패칭 |
JP2017072929A (ja) | 2015-10-06 | 2017-04-13 | 富士通株式会社 | データ管理プログラム、データ管理装置、およびデータ管理方法 |
US10509726B2 (en) | 2015-12-20 | 2019-12-17 | Intel Corporation | Instructions and logic for load-indices-and-prefetch-scatters operations |
US20170177349A1 (en) * | 2015-12-21 | 2017-06-22 | Intel Corporation | Instructions and Logic for Load-Indices-and-Prefetch-Gathers Operations |
US10579531B2 (en) * | 2017-08-30 | 2020-03-03 | Oracle International Corporation | Multi-line data prefetching using dynamic prefetch depth |
US11281589B2 (en) | 2018-08-30 | 2022-03-22 | Micron Technology, Inc. | Asynchronous forward caching memory systems and methods |
KR102142498B1 (ko) * | 2018-10-05 | 2020-08-10 | 성균관대학교산학협력단 | Gpu 커널 정적 분석을 통해 gpu 프리패치를 수행하기 위한 gpu 메모리 제어장치 및 제어방법 |
KR102238383B1 (ko) * | 2019-10-30 | 2021-04-09 | 주식회사 엠투아이코퍼레이션 | 통신 최적화기능이 내장된 hmi |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06103169A (ja) * | 1992-09-18 | 1994-04-15 | Nec Corp | 中央演算処理装置のリードデータプリフェッチ機構 |
US5426764A (en) * | 1993-08-24 | 1995-06-20 | Ryan; Charles P. | Cache miss prediction apparatus with priority encoder for multiple prediction matches and method therefor |
US5561782A (en) | 1994-06-30 | 1996-10-01 | Intel Corporation | Pipelined cache system having low effective latency for nonsequential accesses |
US5623608A (en) * | 1994-11-14 | 1997-04-22 | International Business Machines Corporation | Method and apparatus for adaptive circular predictive buffer management |
JP3741945B2 (ja) * | 1999-09-30 | 2006-02-01 | 富士通株式会社 | 命令フェッチ制御装置 |
US6789171B2 (en) * | 2002-05-31 | 2004-09-07 | Veritas Operating Corporation | Computer system implementing a multi-threaded stride prediction read ahead algorithm |
-
2005
- 2005-08-16 JP JP2007527950A patent/JP5059609B2/ja active Active
- 2005-08-16 WO PCT/US2005/029135 patent/WO2006038991A2/en active Application Filing
- 2005-08-16 KR KR1020077003839A patent/KR100987832B1/ko active IP Right Grant
- 2005-08-17 TW TW094128055A patent/TWI348097B/zh active
Also Published As
Publication number | Publication date |
---|---|
TW200619937A (en) | 2006-06-16 |
KR100987832B1 (ko) | 2010-10-13 |
WO2006038991A2 (en) | 2006-04-13 |
JP5059609B2 (ja) | 2012-10-24 |
WO2006038991A3 (en) | 2006-08-03 |
KR20070050443A (ko) | 2007-05-15 |
JP2008510258A (ja) | 2008-04-03 |
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