TWI346366B - Method for manufacturing substrate of semiconductor package and structure thereof - Google Patents

Method for manufacturing substrate of semiconductor package and structure thereof

Info

Publication number
TWI346366B
TWI346366B TW096119857A TW96119857A TWI346366B TW I346366 B TWI346366 B TW I346366B TW 096119857 A TW096119857 A TW 096119857A TW 96119857 A TW96119857 A TW 96119857A TW I346366 B TWI346366 B TW I346366B
Authority
TW
Taiwan
Prior art keywords
semiconductor package
manufacturing substrate
substrate
manufacturing
package
Prior art date
Application number
TW096119857A
Other languages
Chinese (zh)
Other versions
TW200849421A (en
Inventor
Chien Hao Wang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW096119857A priority Critical patent/TWI346366B/en
Publication of TW200849421A publication Critical patent/TW200849421A/en
Application granted granted Critical
Publication of TWI346366B publication Critical patent/TWI346366B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
TW096119857A 2007-06-01 2007-06-01 Method for manufacturing substrate of semiconductor package and structure thereof TWI346366B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW096119857A TWI346366B (en) 2007-06-01 2007-06-01 Method for manufacturing substrate of semiconductor package and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096119857A TWI346366B (en) 2007-06-01 2007-06-01 Method for manufacturing substrate of semiconductor package and structure thereof

Publications (2)

Publication Number Publication Date
TW200849421A TW200849421A (en) 2008-12-16
TWI346366B true TWI346366B (en) 2011-08-01

Family

ID=44824152

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096119857A TWI346366B (en) 2007-06-01 2007-06-01 Method for manufacturing substrate of semiconductor package and structure thereof

Country Status (1)

Country Link
TW (1) TWI346366B (en)

Also Published As

Publication number Publication date
TW200849421A (en) 2008-12-16

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees