TWI345783B - Nonvolatile memory cells, monolithic three dimensional memory arrays and methods for programming such memory arrays - Google Patents

Description

IX. Description of the Invention: [Technical Field] The present invention relates to a rewritable non-volatile memory array in which each unit includes a diode in series and an impedance switching element. [Prior Art] The σ person is known to be an impedance switching material that can be reversibly converted between a 咼 impedance state and a low impedance state. These two stable impedance states make these materials an attractive option for use in rewritable non-volatile suffix arrays, however, due to interference hazards between cells, high no-leakage currents, and numerous manufacturing The challenge is that it is very difficult to form large, high-density arrays of such cells. Therefore, there is a need for a large rewritable non-volatile memory array that uses resistive switching elements that are not difficult to fabricate and that are reliably programmed. SUMMARY OF THE INVENTION The present invention is defined by the following claims, and should not be construed as limiting the scope of the claims. In general, the present invention is directed to a non-volatile memory unit comprising a diode and an impedance switching material. A first aspect of the present invention provides a non-volatile memory cell including a monopole body and an impedance switching element including a resistivity switching metal oxide or nitride compound, the metal oxide Or the nitride compound comprises only one metal, wherein the diode and the impedance switching element are part of the memory unit. Another aspect of the invention provides a plurality of non-volatile memory cells, 119762.doc 1345783 X y Alx〇y, Mgx〇y, Cox〇y, Crx〇y, v Zrx〇y, BxNy, and illusion. X y nx〇y, 情:: Another good embodiment of the month I provides a method for forming an overall three-dimensional stealth array '豸 method includes ^ ^ ^ ^ a. a) on a substrate shape = brother a money body layer, the first memory layer being formed by comprising the following steps: 1) forming a first plurality of diodes ...) forming a first-to-complex: anti-object switching element 'the elements comprising selected from: Called 〇:, Nbx〇y, 叫, 财, (4), 叫, 吁, etc. [TxVx〇y, ZnX〇y, Zrx〇y, BxNA A] XNy, where each of the polar bodies In the equal impedance switching element, at least one second memory layer is formed on the first memory layer and on the substrate. A related embodiment provides a means for forming an overall three-dimensional memory array. The method includes the steps of: forming a plurality of substantially planar 2, substantially coplanar conductors - the first of which on the substrate - Height and at first: extending upward; forming a second plurality of substantially parallel, substantially coplanar. a body: extending at a second height at a first height and extending in a second direction different from the first direction; forming a first plurality of impedance switching elements, such as a cow, and the like, comprising a group selected from the group consisting of The material · 〇 〇 ' soup x 〇 y, is, Hfx 〇 y, Α χ 、, called, c. , _:, x〇y Znx〇y, Zrx〇y, BxNy, and A]xNy; forming a first plurality of diodes that cause the first diodes and the first impedance switching element systems Forming a first diode on the second conductor at a first height and at a second height; and forming a third conductor on the second conductor. H9762.doc 1345783 first memory unit, each basket of memory unit contains: - a bottom conductor formed on the substrate, · ^zhe low, etc., 6 Haidi - bottom conductor contains a layer of Ming And δδ gold or copper, the - impedance switching (four), and - the diode formed on the first bottom conductor; and π) integrally formed on the first memory layer at least one second memory layer. 』This (4) m sample provides a method for staging the § memory unit in the memory material column, the basin is now #达...... The memory unit contains a metal oxide or a nitride compound, and the resistivity is changed. The metal oxide or nitrided & material comprises exactly one type of genus, and the method includes: changing the resistivity switching layer from the first resistivity state to the memory cell, wherein:: broadening the resistivity The state of the first buttoned resistivity state stores the data state of the memory soap 7C. The method of the present invention provides a method for using a memory cell in a sense array, and the W 11 has a hidden body a ^ 10,000 method in which the memory cell comprises: a total oxide or a nitride compound - resistivity Switching layer, the gold; oxygen: the compound or the compound compound comprises exactly one metal; and a diode comprising the bulk material, the resistivity is + day, the method comprises: i) the first. Xuan Erji electrical series matching element, 1 1 g stylized pulse is applied to the memory single: the third 程式-stylized pulse: a) detectably change the resistivity switching first resistance ^ Μ can be made Changing the polycrystalline semiconductor material: resistivity state and detectably changing the polycrystalline semiconductor: layer = rate state; and ii) reading the memory single brother - resistance - resistivity state for storing data and two:: resistivity switching The fourth of the layers and the second electric of the semiconductor material 119762.doc * 〇. 1345783 The resistivity state is used to store the data. Each of the aspects and embodiments of the invention described herein may be used by car alone or in combination with each other. Preferred aspects and embodiments will now be described with reference to the accompanying drawings. f Implementation] A variety of materials exhibit reversible resistivity switching performance. Such materials include chalcogenides, carbon polymers, ore and some metal oxides and nitrides. With

Body ##includes only metal-based oxides and nitrides that exhibit reliable resistivity switching properties, such as PagniaA s〇tnick, in his heart

Switching in Electroformed Metal-Insulator-Metal Device" (Phys. Stat. Sol (4), ll 65 (i988)). The group includes, for example, Nix〇y, Nb, Tix〇y, Hfx〇y, Alx〇y, Mg, C〇xOy CrxOy, Vx〇y, Znx〇y, Zrx〇y, BxNy, and AlxNy, wherein乂 and 7 between 〇 and 1. Examples are stoichiometric compounds NiO, Nb2〇5,

Ti02, Hf02, ai2〇3, Mg〇, c〇〇, Cr〇2, v〇, Zn〇,

Zr〇, BN and AIN' can also be used as non-stoichiometric compounds. A layer of one of these materials can be formed in an initial state (e.g., a relatively low resistivity state). After a sufficient voltage is applied, the material switches to a stable high resistivity state. This resistivity is switched to be reversible; subsequent application of a suitable current or voltage can be used to return the resistivity switching material to a stable low resistivity state. This conversion can be repeated a lot: owe. For some materials, the initial state is high resistivity and not low p and resistant. t This discussion is about "reciprocal resistivity switching" when "electric m rate switching material, "resistivity switching metal oxide or nitride", "impedance switching switching group 7L piece" or similar terms 119762.doc 丄 material. 2: Resistivity switching material is therefore used for non-volatile memory array 4. For example, the resistivity state can correspond to the data "〇", the resistivity state corresponds to the data T... Some materials in the material can have more than two kinds of 雷--H resistivity states. In some cases, some materials can (4) reach any data state in a plurality of data states. The resistivity between the high-resistance resistivity states of the memory cell is made V. The difference between the low-resistance and the low-yield sheep must be large enough to be detected. j°° is in the material of the resistivity state. The resistivity should be at least three times the resistivity of the material at a low electrical p-rate. When this discussion is about resistivity switching poems, "resistivity switching metal oxides or nitrides, Body element" or similar , It will be understood that between the 'low-impedance and high-impedance or low-resistivity state or the high-resistivity state: at least three times. However, there are many obstacles to the use of material resistivity switching in large non-volatile memory arrays. Forming a plurality of memory cells in a possible configuration (each memory cell is as shown in FIG. 1), comprising: - _ impedance switching memory component 2 (including one of specified f resistivity switching materials) It is placed between conductors in an array of intersections (for example, between the top conductor 4 and the bottom conductor 6). The impedance switching memory element 2 is programmed by palladium applying a voltage between the top conductor 4 and the bottom conductor 6. In a large array of cells such as A, where the cross-point array g is already set, many cells will be addressed by the same top or bottom conductor. When a relatively large voltage or current is required, there is a danger: with the address to be addressed: 119762.doc -12· 1345783 The memory cells with a top or bottom conductor will be exposed to sufficient voltage or current at them. Undesirable impedance switching occurs in the half-selected unit. Depending on the biasing mechanism used, excessive steam leakage current across unselected cells can also be a concern. In the present invention, the diodes are paired with a resistivity switching material to form a gamma rewritten non-volatile memory cell that can be formed and programmed in a large, south density array. This array can be reliably fabricated and programmed using the methods described herein. While many embodiments are possible and will describe an illustrative selection, one simple form of memory cell formed in accordance with the present invention is not shown in FIG. The unit comprises a bottom conductor 2A comprising a conductive material', e.g., a re-synthesized semiconductor material, a conductive stellite or preferably a metal (e.g., tungsten, sulphur or copper). A top conductor 4 is formed thereon, and the top turn conductor may have the same material as the bottom conductor. The crossbar top conductor and the bottom conductor preferably extend in different directions: for example, they may be vertical. The conductors may include a conductive barrier layer or an adhesive layer as needed. Made in series - the body 3〇 and the impedance switching element! 18 is disposed between the top conductor and the bottom conductor 200. Other layers (e.g., barrier layers) may also be included between the conductors 200 and 400. The impedance switching element 118 transitions from a low impedance state to a high impedance state, or from a state to a low impedance state, after a voltage is applied across the impedance switching element (1) or a current is applied through the impedance switching element 118. The transition from low impedance to high impedance is reversible: The diode 30 acts as a - unidirectional, which conducts current more easily in one direction than in the other direction 119762.doc 1345783. In the forward direction, the critical "on" voltage, the diode 30 conducts little or no current. By using an appropriate biasing mechanism, when individual cells are selected for programming, the adjacent cells 2 diodes can be used to electrically isolate the impedance switching components of their cells and thus • prevent unintentional stylization as long as it crosses the The voltage of the selected or half-selected cell does not exceed the turn-on voltage of the one-pole (when applied in the forward direction) or the voltage of the reverse collapse (when applied in the reverse direction). • A plurality of such top and bottom conductors having intervening diodes and impedance switching elements can be fabricated to form a first memory layer, a portion of which is shown in FIG. In a preferred embodiment, additional memory layers can be stacked on the first memory layer to form a very dense overall three-dimensional memory array. The memory array is formed by a deposition and growth layer on a substrate (e.g., a single crystal substrate). The support circuitry is advantageously formed in the substrate below the memory array. An advantageous method for the manufacture of a dense, non-volatile, one-time, programmable, and refractory array that can be reliably fabricated is taught in U.S. Patent Application Serial No. 10/326,470, the entire disclosure of which is incorporated herein by reference. This has been incorporated herein by reference. RELATED MEMORY Arrays and their use and methods of manufacture are taught in U.S. Patent Application Serial No. 10/955,549 to "Nonvolatile Memory Cell Without a

"Dielectric Antifuse Having High-and Low-Impedance States" (applied September 29, 2004, and hereinafter, 549 application); U.S. Patent Application Serial No. 11/15,824 "N〇nv 〇iatiie Memory Cell Comprising a Reduced Height Vertical 119762.doc • 14 - 1345783

Diode" (applied at December 17, 2004 and hereinafter referred to as Application No. 824); and U.S. Patent Application Serial No. 1/954,577, "Junction Diode Comprising Varying Semiconductor Compositions" (in 2004) In the September 29 application and the 577 application below, all applications are owned by the assignee of the present application and incorporated herein by reference. The method taught will be used to fabricate a memory array in accordance with the present invention.

Manufacturing Options In general, the preferred embodiment of the resistor includes a number of important rate of change (iv) characteristics of the material and the manner in which the memory unit is intended to be used to determine which embodiment is the most advantageous embodiment.

Non-directional versus directional switching: _ In general, the earlier specified impedance switching metal oxides and nitrides exhibit two general types of switching performance. Referring to Figure 4, the UV graph 'in the eighth region of the graph, some of these materials are initially in a low resistivity state. It is not difficult to cause current to flow until the first electric house % is reached for the applied voltage. At the electrical", the resistivity switching material transitions to the high resistivity state shown in region B and reduces the current. At a certain higher threshold, the material switches back to the initial low resistivity state, and Increase the current. The arrow indicates the order in which the state changes. This conversion is repeatable. For these materials, the direction of the bias is good; ^ sound i . m M JIL ^ ,, , these materials will be called no direction The voltage can be referred to as the reset voltage, and the voltage can be referred to as the set voltage. In addition, other resistivity switching materials as shown in & and 讣 will now be referred to as directionality. Directionality f PH + i η Γ The raw resistivity switching material can also be formed as shown in Figure 5a lZ9762.doc -J5. Electricity: Γ二: Low impedance state. It is not difficult to apply: flow until reaching the first-electrical V, (reset electricity) The electro-mechanical resistivity switching material is switched to the region of the graph Β and converted back to the low resistivity-like resistivity switching material—the heart must be applied—the reverse voltage. As shown in Figure 5b, the directional resistivity Switch material in the area: anti-object to critical reverse power plant TM constant voltage) Here, the electric == electric: rate switching material returns to the low resistivity state. The arrow indicates that the state is prolonged. (Some materials are initially formed in a high resistivity state. The switching performance is: the same, · for simplicity Only one initial state is described. f is preferred in the embodiment, the non-directional resistivity switching material can be paired with the substantially early-polar body. One of the diodes is the pin two shown in FIG. Preferably, the pi-η diode is formed of a semiconductor material (eg, Shi Xi) and includes a two-bottom heavily doped region 12 having a first conductivity type; a 1 intrinsic region 14 'not intentionally And a top heavily doped region VIII having a second conductivity type opposite to the first conductivity type. In the diode of Figure 6, the bottom region 12 is n-type and the top region 16 is Ρ-type ; #需要' can reverse the polarity. A domain _ is not intentionally (four) =: 〖In many manufacturing processes, the defects in the essence of deposition cause the material to behave as if it is light _. In some implementations In an example, it is preferable to noisy this area. After applying a voltage, the pole This is shown by [4] in Figure 8. At very low voltages, little or no current flows. At the threshold voltage V3 (the turn-on voltage of the diode), the diode begins]] 9762 .d〇c -16- 1^45783 Conductive and significant forward current flow. When the diode is placed under a low and moderate reverse voltage (as in region D of Figure 8), little or no current flows; The diode acts as a check valve. However, after applying a very high amount of reverse dust, the diode will collapse through the party process and a reverse current will begin to flow. This event can be destructive to the diode. Sex (although ideally it will not). Recall that there is no directional impedance: the set voltage and reset voltage of the material need only one direction of current. Therefore, one of the diodes of Figure 6 can be successfully used. The directional impedance switching materials are paired. However: As illustrated in the graphs of Figures 5a and 5bgV, the directional resistivity switching material must be exposed to both positive and negative electrical hunger for successful switching. The low resistivity_high resistivity transition shown in Figure 5b requires a reverse electrical catch (at electrical centistoke 2). The reverse current is only achieved in the early dipole in the reverse collapsed electrical blanket (electrode: 4 of Figure 8), which is typically relatively high, e.g., at least 9 volts. The directional resistivity switching material may therefore not be advantageously paired with the unidirectional diode. In fact, these materials can be paired with reversible non-ohmic devices (i.e., devices that allow any current in the direction). One such device is a Zener diode. An exemplary Zener diode is shown in FIG. It will be appreciated that the diode has a first heavily doped region 12 of the first conductivity type and a second heavily doped region 16 of the opposite conductivity type. The polarity can be reversed. There is no essential region in the Zener diode of Figure 7; in some embodiments, there may be a very thin essential region. Figure 9 shows the I V plot of the Zener diode. 5 Hai Zener diodes under forward bias, such as p-small diode II9762.doc, it has a turn-on MV3®, however, under reverse dust, one reaches the threshold voltage V4, Zener II The polar body will allow a reverse current to flow in the Zener diode. The magnitude of the critical reverse voltage V4 is substantially lower than the value of the unidirectional diode. This requires a moderately controlled reverse. The current is converted from a high resistivity to a low resistivity energy, as described earlier and as shown in the figure (at the electric dust %). Therefore, in the embodiment of the invention in which the material resistivity switching material is used, the Zener diode is preferably two. (In fact, the difference between p-i_n diodes and Hr) with very small intrinsic regions is false 'but can be used by those skilled in the art but the material does not require both forward and reverse directions. The current, the circuit, and the resistivity switching in the direction of the direction. For some circuit configurations, it may be advantageous to have the Zener diodes paired. ...directional resistivity switching materials and

As used herein, the term "semiconductor device with a junction diode π with seven pieces of P-characteristics, θ eight non-ohmic conduction material", has two terminal electrodes, and is made of semiconductors, at the electrode The bovine conductor material consists of a contact-type semi-conducting type of semi-conducting electrode at the (four)° example 俨 导 导 材料 material and η-type semiconductor material ρ·η - = body and "diode (such as Zener diode) And ρ ρ - specializes in the small η diode in the intrinsic body, in which the Φ Φ semiconductor material is inserted between the ρ-type abundance body material and the !! type semiconductor material. P, the cattle lead high current demand: for the weight The 吱 rate switching material allows the rate to switch materials while in a non-directional group of electricity in some materials: the transition to a low resistivity state, for J * to be relatively relatively far from the gate of the electric W. For this material IJ9762. Doc 1345783 It is preferred that the diode be a tantalum or niobium alloy which provides a higher current at a given voltage than helium.

Rare metal contacts and low temperature fabrication: It has been observed that when the resistivity switching material is sandwiched between rare metal contacts that can be formed, for example, from Ir, pt, _Au, some of the metal oxides mentioned earlier The resistance of the material and the nitride (4) is easier to change and the example of the element according to the invention (where rare metal contacts are used) is shown in i1G. The resistivity switching element 11 8 is between the rare metal layers 11 7 and 11 9 . However, the use of rare metals presents a challenge. When exposed to high temperatures, rare metals tend to diffuse rapidly and can damage other parts of the equipment. For example, in the figure, the rare metal layer 1]7 is adjacent to the semiconductor body 30. Rare metals diffuse widely in the dipole

Will damage device performance. When the resistivity switching element is formed between, the processing temperature can advantageously be minimized. The diode may be a stone, a bismuth or a bismuth-tellurium alloy. In contrast, niobium crystallizes at a lower temperature, and as the niobium content of the niobium-niobium alloy increases, the crystallization temperature decreases. When a rare metal contact is used, a diode formed of tantalum or niobium alloy may be preferred. Polycrystalline germanium (in this discussion, polycrystalline germanium (p〇lycrystaUine silic〇n) will be called polycrystalline germanium (pca out (10)), while polycrystalline germanium (four) will look like germanium) will be called polycrystalline germanium (corpse/less) The deposition and crystallization temperatures are relatively high in (iv) ruthenium.), and the use of polycrystalline germanium diodes which are conventionally formed to be incompatible with certain metals having relatively low melting points are reproduced. For example, when exposed to about 475. (At the above temperatures, the aluminum wire begins to soften and be extruded. For this reason, in many embodiments, 47, 549, and H9762.doc 1345783, the use of tungsten is preferred in the conductor because Tungsten wiring can withstand relatively long temperatures. However, if a tantalum or niobium alloy is used, the lower deposition temperature and crystallization temperature can be allowed to be used in conductors (for example, in conductors 200 and 400 of Figure 10) or even Steel. These metals have low sheet resistance and are therefore generally preferred (if heat balance permits their use), but can be used instead of cranes or some other conductive material. When low temperatures are favored, Herner et al. Any teaching, US Patent Application No. 11/125,606 "Density Nonv〇iatUe Mem〇ry Array l (4)

The manner in which Temperature Comprising Semi〇〇nductor Diodes'^^ is incorporated herein and is related to low temperature manufacturing may be applicable. Conductivity and Isolation: It has been described 'to make stylization possible in large arrays, including diodes in each memory cell to provide electrical isolation between adjacent cells. Some resistivity switching materials sink in a high resistivity state, while other resistivity switching materials are deposited in a low resistivity state. Generally. For the resistivity switching material deposited in the south resistivity state, the transition to the low resistivity state is localized. For example, referring to FIG. 11a' hypothesis - a memory cell (shown in cross-section) a portion conductor 200 on the page from the bottom of the R ^ 狎 right, the diode 3 〇; formed in a high resistivity state The resistivity switching material layer...; and an extension " two rod-shaped top conductors_. In this case, the resistivity switching material; 曰 has been formed as a blanket layer. As long as the resistivity switches the material layer to high voltage: the heart is high enough 'layer 118 will not provide the conductor 4〇. The non-desired conductive resistivity switching material layer 118, which is shorted to the adjacent or polar body to the adjacent diode, is exposed to a high power and is switched to a low voltage. 19762.doc -20. /60 Resistivity state In the meantime, the area directly adjacent to the diode of layer 118 will be converted; for example, + ★』 • to 5, after stylization, the shaded area of layer 118 will be low resistivity' Unshaded areas will maintain high resistivity. The shaded areas are resistivity switching elements disposed within the continuous layer 118 of resistivity switching material. :, • depending on the reading voltage, set voltage and weight of a certain resistivity switching material, the high resistivity state of the resistivity switching material is too conductive for reliable isolation, and when formed in “continuous In the layer (as in Figure (1)) it will tend to short the adjacent conductor or diode. For different resistivity switching materials, it can provide the desired: a) the resistivity switching material 118 is unpatterned, as in the device of Figure Ua; or... patterned resistivity switching material 118 and top Conductor or bottom conductor, as shown in the device (shown in perspective); or c) patterned resistivity switching material 丨丨8 and diode 30, as in the apparatus of Figures 2 and 1 . When the memory element is formed of a resistivity switching material formed in a low resistivity state, it must be switched from the resistivity of the adjacent cells to avoid forming an undesirable conductive path therebetween. For example, in the '5, 49 application, and in the U.S. Patent Application Serial No. 1 1/148, No. 530, "Nonvolatile Memory Cell Operating by

Increasing Order in Polycrystalline Semiconductor Material, as described in detail in the ' s Application ' 530 application, the disclosure of In the case of a semiconductor diode, it is expected that in some embodiments, the polycrystal of the diode will be formed in an initial high resistivity state and will be applied after a sufficient voltage of 119762.doc -21 · 1345783 is applied. It is permanently switched to the low resistivity state. Therefore, referring to the unit of Fig. 2, when the unit is initially formed, both the pole (4) and the reversible impedance switching element 118 are formed in a high resistivity state. - After the stylized electricity, the 'diode 3' polycrystalline stone and the resistivity switching element m will be switched to their low resistivity state. In general, the conversion of the diode 30 is permanent, The conversion of the resistivity switching element 118 is reversible, and it is necessary to perform the initial conversion of the polycrystals of the diodes from high resistivity to low resistivity in factory conditions, and effectively "pretreatment" Or, Η(10)er, US Patent Application No. 1/954,5, nickname "Memory Cel] Comprising a Semiconductor Junction Diode ^rystalhzed Adjacent t.a Silicide" (on 2()() 4 September μ日申凊, hereinafter, the application of 5, 10, which was assigned to the article by reference.) Method for polycrystalline semiconductor diodes in a low resistivity state. (iv) The semiconductor material of a diode (usually a stone near a lithium layer (for example, TiSi2) crystallizes. The layer provides an _ ordered crystal template during the Shi Ximei crystal, thereby producing a high gentleman S-weight μ day and a pole body as the formed car father has less crystal defects. This technique can be used in the present invention. If the diode is germanium, the germanium diode is crystallized adjacent to the germanium layer (4) core 2), and the germanide layer will be provided with germanium - a crystallographic template similar to the one formed. Low resistivity, which does not require the "stylization of a low impedance path through which it passes," Step. One Programmable Memory Unit · Two-State J19762.doc -22- 1345783 has been described in the embodiment of the present invention (when used as a rewritable memory unit): paired with the impedance switching element The two poles can also be used in the example: to form a sub-programmable memory unit. For a record that can be switched between a lower resistivity state and a higher resistivity state For resistivity switching binary metal oxides or nitrides, resetting from a lower resistivity to a higher resistivity state may prove to be a more difficult switching. (It will be understood that in this discussion, "oxidation ^ I =: T * Ni0 or non-stoichiometric compounds). Although the actual switching is not a good one, it seems that it is necessary to apply a certain voltage across the resistivity switching layer to cause it to switch. If the material is set to a very low resistivity and the remote material is highly conductive, it may be difficult to build enough dust to cause switching. More difficult switching can be avoided by using the memory unit of the present invention as a one-time programmable single 兀'. This usually simplifies the stylized circuit. ... a preferred resistivity switching material (nickel oxide) is non-directional, which means that it is switched by a positive or negative voltage applied. However, in some embodiments, 'discovered' when paired with a diode, the resetting of the oxide layer ^ is most difficult to achieve by a diode under reverse bias. An additional transistor may be provided in the substrate to provide a negative voltage to reverse bias the diode. These transistors consume board space to make the device more expensive, and the formation of such a crystal can add extraneous complexity. Therefore, in embodiments where reverse bias I is required for resetting, the use of a cell as a write-once unit and avoiding resetting can avoid the difficulty of generating a negative voltage. „ In the simplest way of using the memory unit including the diode and the resistivity switching layer according to the present invention as a private δ hexamed body early, the single Π 9762.doc • 23 - 1345783 yuan Has two values (unprogrammed and stylized) that correspond to two different read currents through the cell. The set voltage will depend on the material, layer thickness, material: characteristics, and other factors used for the impedance switching component. The change. Increasing the pulse time reduces the voltage required to set the material from high impedance to low impedance. The set voltage can vary from (eg, volts to 10 volts).

For comparison: if the diode is formed of polycrystalline germanium, the polycrystalline germanium crystallized adjacent to a germanide having a lattice structure in a certain direction (which provides a good crystal template for germanium) will produce lower defects and Low resistivity polyliths; and only crystals adjacent to materials with poor lattice matching, such as titanium carbide, will result in higher defect, higher resistivity polysilicon. If the diode is formed by a polycrystalline fragment having a local impedance, it is necessary to apply a suitable programmable electrode across the diode to convert the polycrystalline stone to a low resistivity state, thereby leaving A diode with good rectifying properties.

Furthermore, it has been found that in certain embodiments, for certain resistivity switching metal oxides or nitrides formed in an initial high resistivity state, a shaping pulse may be required to achieve self-resistivity to low resistivity. The first switch. This shaped pulse may require a higher voltage than the subsequent low or I low resistivity switching. For example, ancient, A — μ ^ . In a one-shot test, the shaping pulse was about 8 5 9 volts, and the subsequent set pulse was about 6.5-7 volts. For example, in U.S. Patent Application Serial No. 11/287,452, et al., ReVerSib,; Metal 〇xide 〇r (Yu Nian called for application on the 23rd, 452 for the following case and in the form of bow | As described in this article, adding a JI9762.doc •24-1345783^ genus to _το metal oxide or nitride can reduce the setting power and re-power i: J· can reduce the amplitude of the shaping pulse or eliminate the pair The need for the entire forming pulse. Generally, the metal atomic metal additive in the layer is between about 0.01% and about 5% of the metal oxide or nitride. Preferred metals for the metal additive are selected from the group consisting of manganese, nickel, ruthenium, osmium, titanium, and ruthenium. The following groups: Record, Ming, Gallium, Indium, Giving, Group, Magnesium, Chromium, Syria, Butterfly, and

Therefore, many options may be used for the impedance switching element and the diode should consider the effect of pairing the impedance switching element with the diode. A primary programmable memory cell comprising a binary metal oxide or nitride. If a binary metal oxide or nitride is formed in a high resistivity state to a resistivity or a low resistivity polysilicon, and the diode is formed of a low defect, low resistivity polycrystalline material, the binary metal oxide can be formed by Or the nitride is switched to a set state to achieve a conversion of the memory cell to a stylized state in which a high current flows at the read voltage. However, if the diode is formed of a high-defect, high-resistivity polycrystal, the polysilicon of the diode must also undergo a stylized voltage of the memory cell to behave as if it were formatted, allowing the applied read. High current at voltage. Depending on the disorder-order conversion of the polycrystalline germanium and the relative voltage required for the high-low resistivity conversion of the binary metal oxide or nitride, a low-deficient polycrystalline litura is used (near the appropriate Shi Xi The crystallized polycrystalline spine may be preferred. If a larger shaped pulse is required for forming a single-element metal oxide or nitride in a high resistivity state, another alternative is to yoke in a pre-119762.doc -25 - ^45783 step in the factory. The shaping pulse. The high voltage of the γ pulse can be self-external. The P supply 'and therefore does not need to be available for re-execution at the bias, then the female ancestors are picked up. The right side needs to be reversed, because I: can also apply a reset pulse in the other-pre-processing step. When the memory array is ready for the most heavy-duty stickers, the first element is in the heavy-state. And it can be simplified by the lower, this way, s+ 疋 。. The circuit on the day and the day does not need to provide high voltage forming and & + voltage, which simplifies the circuit requirements. ...pulse or negative

If a pre-forming forming pulse and a reset pulse are applied to the workpiece, the larger voltage required for forming the pulse is converted to the low resistivity of the high-defect polycrystalline germanium. ^ _ 牡 This month, there is no disadvantage of using non-chemical, defective diodes, and the extra-private complexity of arranging the stencil layer can be avoided. This method is used to program the memory unit in the fp-checked 丨 丨 忑 忑 忑 忑 忑 忑 忑 忑 忑 。 。 。 The memory cell comprises a resistivity switching layer of a metal oxide or a nitride compound, the metal oxide or nitride compound comprising exactly one metal, and the method comprises: switching the resistivity layer from the first resistivity The state changes to a second stylized resistivity state to program the memory cell, wherein the second stylized resistivity state stores the data state of the memory cell. The memory array includes circuitry for programming and reading the memory cells, and the circuitry is adapted to program the memory cells only once. The memory array is a one-time programmable array. - Sub-programmable, multiple states In another embodiment, it may be practical to have a binary metal oxide or nitride paired with a diode formed of a high defect polysilicon. The two states (initialized low resistivity state) of the polysilicon constituting the 119762.doc •26- 1345783 diode can be used to store data, density.

For example, suppose that a diode formed by a high-defect polycrystalline polycrystalline stone (not crystallized adjacent to a suitable alexandry) is paired with a nickel oxide layer, and the two are electrically connected in series to the top conductor and the bottom conductor. between. Nickel oxide is formed in a high resistivity state, requiring a shaping pulse to achieve the first conversion from high resistivity to low resistivity. It is assumed that the diode requires 8 volts of stylized electric dust to produce the disordered-ordered transition described in the '530 application, thereby converting the polysilicon to a higher resistivity state. The step-by-step assumption assumes that the voltage required for the oxidation of the pulse is 10 volts. (It will be understood that the voltage given here is only an example. The voltage will change as the characteristics of the device and other factors change.

Data status ~00 ' 10 polycrystalline state high resistivity switching layer state reset stylized unprogrammed +2 V reading Lei Jie 1 X 10'ισ^ΪΓ low resistivity reset +8 V 1 X 104 Ampere 1 X 10'5 Ampere 11 Low Resistivity Setting +11 V Table 1

The south resistivity state and the program thereby increasing the memory cell, such as the formed memory cell, have a high resistivity nickel oxide and a diode having a high resistivity polysilicon. Table i below summarizes the three data states that can be achieved by this memory. For this example, 'it also includes the stylization required to achieve each state and an example read current expected to be used for each data state at the applied + 2 volt read voltage: no applied program In the case of the voltage, if the formed memory is in the first data state, the first data state is referred to as the chirp state for convenience. The application of +8 volts is sufficient to convert the polycrystal of the diode to the low resistivity from the high voltage 119762.doc -27. However, it is lower than the voltage required for the shaping pulse, so that the nickel oxide is at its initial High resistivity state; this data state will be referred to as _10'. Applying +11 volts to the unit in the initial, 〇〇 state is sufficient to achieve both the disordered-ordered conversion of the polysilicon and the setting of the nickel oxide to a low resistivity state. The status of this profile will be referred to as, 丨丨, status. In another embodiment, a shaped pulse or only a small = pulse may be required and the set voltage may be less than the voltage required to switch the polysilicon. In this case, the achievable data status is summarized in Table 2:

As formed, the memory cell is in a state in which both polycrystalline and oxidized are high resistivity. Applying +6 volts to set up the silk recording, but it is not enough to switch the polysilicon, so that the unit is in the or state. Apply 8 volts: eve s day 11 and oxidize both, so that the two are in a low resistivity state corresponding to the .11, data state. , in any of the embodiments, once the unit is in, ", state, , : by re-freeing nickel oxide to achieve the fourth data state, in which the polymorph of the diode is in a low resistivity state and oxidized The recording is in a reset state. This state will be %'s '10, state, and in embodiments where reverse bias is required for resetting', this state is applied by a - negative reset pulse (such as -4 volts) This is achieved by the unit in the 'U' state. In summary, the memory just described can be programmed by the method ] 9762.doc -28- unit, 6 hai method contains: — unit, where the _ Cheng _ ~ Stylized pulse applied to the first layer of the memory layer: 丄 :: a) Valuable change of the resistivity of the second resistivity of the material cut j ... or) can be changed to change the polycrystalline semiconductor material - Resistivity state and can detect the resistance of the thousand-knife layer. 1., change the second electric of the polycrystalline semiconductor material.... The memory unit is used, and the resistivity state is used for the brother of the flat knife. The rate state is used for one of the second resistance data states of the health data = polycrystalline semiconductor material. The cell is adapted to store three or more impedance levels up to the resistivity referred to to switch the binary oxide or nitride only to a stable resistivity state of about =. In some embodiments, depending on the species. The memory cell of the array formed by Gome can be stored in two or more of three, four or more different testable resistivities by oxidizing the metal: Data status, for example, three = 'four or more data states. The circuit can be sensed and decoded to reliably detect different data states that can be detected. These embodiments are rewritable or For example, it is assumed that the resistivity switch metal oxide or nitride is a oxidized bromine (it will be understood that 'any of the other specified materials can be used'), which has been formed in a high resistivity state. To the circle 12' as formed, the oxidation record is in the lowest resistivity state, which is shown on the curve labeled 00. Nickel oxide can be placed in more than two states that can detect different resistivity. For example, '-memory Body unit (as shown in Figure 2) The memory unit) can have four different states, Ϊ J9762.doc -29- 1345783, each of the 雄 兹 +, ^ in a applied reading voltage (for example, about 2 volts) - the current range comes In this real wealth, in the highest resistivity state, when crossing 2 + 2 volts of memory, less than (four) nanoamperes of current flow;

In any of the 01 states, at 2 volts, the current will be between about 100 millimeters and _ nanoamperes. In the 1G, state, at 2 volts, the grip will be between about 1 microamperes and 3 microamperes. In the lowest resistivity state: state, the current at 2 volts will be greater than 9 microamperes. It will be understood that other values may be appropriate depending on the supply of such current ranges and the reading of the electrical components and the characteristics of the device. In this example, the &'s pulse has an electrical enthalpy between about 8 volts and about volts and the reset is between about 3 volts and about 6 volts. In an embodiment comprising an oxidation record paired with a P+n diode, a reciprocal electromigration is applied in the reverse bias. However, depending on the material used and the configuration of the memory unit, the reverse bias can be used to reset the unit. Referring to Figure 12, the state is formed by the unit. To program the unit to 01-shaped f', a set power of 8 volts can be applied, for example. For all set pulses, a current limiter is preferably included in the circuit. The unit was read at 2 volts after the set pulse was applied. If the current at 2 volts is at 01, the state: in the range, between (about 100 nanoamperes and about 300 nanoamperes), then 4 units are programmed. If the current is too low (for example, nanoamperes), J applies an additional set pulse (as appropriate at a higher set voltage) and reads the unit at 2 volts. This process is repeated until the current through the memory bank 7L is within the correct range of 2 volts. H9762.doc -30- 1345783 After the stylized pulse is applied, the I stream can alternatively be, 〇i, state: above the target perimeter; for example, it can be a full nanoamperes. In this case there are two options; it can be applied to return the oxidation record to, 〇〇, the shape reset pulse 'then then another set pulse can be applied, or a reset pulse can be added to increase slightly The resistivity of the nickel oxide layer, which is privately transferred to the range of 〇1. This process is repeated until the current through the memory cell is within the correct range of 2 volts.

Using a similar method to place the memory cell in a state, or state, for example, the set voltage of s '9.5 volts may be sufficient to place the memory cell in the .10' state, and the 1G volt setting (4) may be Program the memory unit to the status of the data. The memory unit is preferably used as a rewritable memory unit. However, it may be preferable to omit the dielectric crystal capable of applying a reverse bias to save space in the substrate, and to program the unit only under forward bias. This memory array can be rewritable if a reverse bias is not required to reset the unit. However, if a reverse bias is required for resetting, this memory array can be used as a disposable array. In this case, care must be taken to never set the cell to a state in which it has a current higher than the desired current of the expected data state (lower resistivity of the nickel oxide layer). An intentionally low set voltage can be applied to gradually reduce the resistivity of the nickel oxide layer and raise the current to an acceptable range, thereby avoiding exceeding the desired range, since in this case, without reverse biasing' This spike cannot be corrected. As in the previous embodiment, the advantages or disadvantages of forming a low-defect polycrystalline germanium diode by crystallizing polycrystalline germanium adjacent to a suitable litony compound should be considered. 119762.doc •31 · 1345783 Two vibrating field forming pulse, the voltage of the forming pulse can be enough to change the ancient defect A resistivity polycrystal (4) to a lower resistance n & _ n stomach condition, using low defect 'stone Xihua polycrystalline stone can not provide advantages. If a pulse or a small forming pulse is not required, then the second preferred humus formed by the low defect, low resistivity polysilicon (adjacent to the appropriate hydrazine) must apply a pretreatment step (such as a The shaping pulse) can advantageously be carried out in the factory. In this case, 'high power is not on the die. 'First Manufacturing Example' provides a detailed example of the manufacture of an overall three-dimensional memory array formed in accordance with the preferred embodiment of the present invention. For the sake of clarity, 'will include a lot: the field'. These details include steps, materials, and process conditions. It will be understood that the examples are non-limiting examples and that such details may be modified, omitted, or supplemented, while the results are within the scope of the invention. In general, the (10) request, the '5 office request, the 824 request, and the still-speaking case teach the memory array that does not contain the memory unit, where each unit is a programmable unit. The unit is in a high impedance state; 'after applying a stylized power', the unit is permanently switched to a low impedance state. In particular, coffee, 549, 824, 577, and other incorporations, the teachings of the June case and patents may be related to the formation of the memory according to the present invention, and secondly, 'will not include incorporation The application and the patent office will understand that the teachings of such claims or patents are exclusive. 119762.doc •32· 1345783 Go to Figure 13a. The formation of the memory begins with the substrate 1〇〇. The substrate may be any semiconducting substrate known in the art, such as a single crystal 矽' ιν-ιν compound (such as 矽 锗 or 矽 锗 锗 carbon), an mv compound, and a worm crystal on the substrate. Layer or any other semi-conductive material. The substrate may include an integrated circuit fabricated therein. The insulating layer 102 is formed on the substrate 1A. The insulating layer 1〇2 may be a hafnium oxide, a tantalum nitride, a hafnium dielectric film, a Si_C_〇_H film or any other suitable material. The first conductor 200 is formed on the substrate 1A and the insulator 1〇2. An adhesion layer HM may be included between the insulating layer f 102 and the conductive layer 106 to help the conductive layer 106 adhere. A preferred material for the adhesive layer 1 4 is titanium nitride, but other materials may be used or may be omitted. The adhesive layer 104 can be deposited by any conventional method (e.g., by sputtering). The thickness of the adhesive layer 104 can vary from about 2 angstroms to about 5 angstroms, and preferably between about 100 angstroms and about 4 angstroms, preferably about 2 angstroms. Note that the 'thickness' in this description will indicate the vertical thickness measured in a direction perpendicular to the substrate 1〇〇. The layer to be deposited is a conductive layer 1〇6. The conductive layer ι 6 may comprise any conductive material known in the art, such as a doped semiconductor, such as a metal of a crane or a conductive metal lithium; in a preferred embodiment, the conductive layer is the thickness of the aluminum conductive layer 106. It may depend in part on the desired sheet resistance and thus may be any thickness that provides the desired sheet resistance. In one embodiment, the thickness of the conductive layer 106 can vary from about 5 angstroms to about angstroms, preferably from about 1000 angstroms to about 2 angstroms, and most preferably about i2 GGb n9762.doc -33 - 1345783 An additional layer uo (preferably nitride) is deposited on the conductive layer ι6. The basin may have a thickness that is comparable to the thickness of the upper layer. The photo-lithography step will be executed to pattern the layer 1〇6 and the gasification layer 10 [Ming's high reflectivity makes it difficult to directly perform photolithography on the crucible. The titanium nitride layer (4) is used as an anti-reflection--all layers that have been deposited to form a conductive track, and any suitable masking and surname process will be used to pattern and engrave the layers to form a substantially parallel, generally large layer. The coplanar conductor 200 (shown in cross-section in Figure 13a, in one embodiment, depositing photoresist) is patterned by photolithography and the layers are patterned, and then using standard process techniques (such as "ashing.," to remove the photoresist' and to strip the remaining polymer formed during the period in the liquid solvent (such as those formulated by EKC). Next, the dielectric material 108 is deposited on the conductive track and between the conductive tracks 2). The material 108 can be any known electrically insulating material, such as yttrium niobium oxide or hafnium oxynitride. In a preferred embodiment, yttrium oxide is used as the dielectric material 1 〇 8. Any known process such as chemical vapor deposition (cvd) or (e.g., high density plasma CVD (HDPCVD)) can be used to deposit the oxidized stone. Finally, the excess dielectric material 1〇8 on top of the conductive track 200 is removed, thereby exposing the top of the conductive strip separated by the dielectric material 108, leaving a large body flat surface 1G9° as shown in Figure 13a. The resulting structure. This shift of the dielectric overfill used to form the flat surface 1〇9 can be performed by any of the processes (such as etch back or chemical mechanical polishing (CMP)). The use of conductivity-enhancing dopants or contaminants found in the U.S. application JJ9762.doc • 34·3 of Raghuram et al. can be advantageously used. In a preferred embodiment, the semiconductor pillar package is spliced to the surface. The polar body comprises a top heavily doped region of the bottom-heavy-doped region of the first conductivity type of the first conductivity type. The top-conducting intermediate region is the essence of the first or second conductivity type = ._ between the domains or the lightly doped regions. Here, in the r example, the bottom heavily doped region 112 is a re-shifting type. In the preferred embodiment, the re-doping region ιΐ2 is deposited and used by any conventional in-situ doping. A dopant such as germanium is doped to the heavy binary region 112. This layer is preferably between about 2 Å and about 8 Å. / Next, the deposition is made into the remainder of the diode. In the case of the sputum, the subsequent flattening step will remove an additional degree of susceptibility from + to U. This can be lost by using the conventional CMP method to perform the planarization step. Thickness of 800 angstroms (this is the average; this amount varies with the wafer. Depending on the material used and the method used, the error can be more or less.) If the flattening method is used to perform flattening For the crystallization step, only about _ angstrom: the gentile can be removed. Depending on the planarization method to be used and the desired final thickness, any conventional method is used to deposit between about 800 angstroms and about 4,000 angstroms. Doped germanium; preferably between about 15 Å and about 25 Å; optimally between about 18 Å and 2200 Å. If desired, it can be lightly doped 锗. Top heavily doped regions 116 will be formed in a later implantation step, but at this time it is not yet present 'and therefore not shown in Figure 13b. Patterning the 锗 just deposited Etching to form the pillars 3. The pillars 3〇〇 should have approximately the same distance and approximately the same width as the underlying conductors 200, so that each pillar 3〇〇 is formed on top of the conductor 2〇〇. H9762.doc -36-1345783 is not available. This removal and planarization of the dielectric overfill can be performed by any process known in the art, such as CMp or etch back. For example, 'can be used The technique described in the application of Ragh et al., 4 pp. The resulting structure is shown in Figure Ub. Turning to Figure 13c, in the preferred embodiment, p-type is used by ion implantation at this time. A dopant (eg, boron or BF 2 ) forms a heavily doped top region ι 6 . The diode described herein has a bottom „type region and a top p-type region. If preferred, the conductivity type can be reversed. If desired, a p-in diode having an n-region on the bottom can be used in a memory layer, and a p-type region diode can be used in the other-memory layer on the bottom. 8. Forming a diode resident in the column 3 by a method comprising: depositing a semiconductor layer stack on the first conductor and the dielectric filler and patterning and patterning the semiconductor layer stack To form a first diode. Next, a layer 121 of conductive barrier material (e.g., nitrided other suitable material) is deposited. The thickness of the sound 12 萄 a 121 may be between about 1 angstrom and about = angstroms, preferably about 2. . Ai. In some embodiments, the layer may be omitted to deposit a metal oxide or nitride resistive switching material layer 11 on the barrier layer 121. Preferably, the layer has an A & between about 50 angstroms and about 400 angstroms, for example between about 100 angstroms and about 2 angstroms. The layer may be any of the material nitrides described earlier: an ancient metal oxide or nitride, the metal oxide or the like; including exactly the metal exhibiting impedance switching properties; preferably selected from the group consisting of Rrf n A1 〇科·仏, Nbx〇y, TixOy, 邱〇, AIx〇y, Mgx〇x〇y, CrX〇y, Vx〇y, ZnxOy ' I19762.doc -38- 2rx0y, BxNy&amp AlxNy. For the sake of simplicity, see 'This discussion will refer to the use of yttrium oxide in the layer". However, the other materials of Konghua recorded that oxygen (4) exhibits a non-directional switching. Any "diode paired with W, but can be H' and thus has a P-^ polar body (if the circuit configuration indicates twisting, „ If the directional impedance switching device is selected, the Zener diode will be a preferred nano-diode and has no nature. In the preferred embodiment, the singularity of the singularity is in the preferred embodiment. It is not thicker than the essential region of about 350 angstroms. Finally, in the preferred embodiment, the barrier layer 123 is deposited on the oxide recording layer 118. The layer 123 is preferably titanium nitride, but may be used instead. Conductive barrier material. The purpose of the barrier layer 123 is to allow for an imminent planarization step on the nickel oxide layer 118. In some embodiments, the layer 12 3 may be omitted. The layers 123, 118 and 121 are fused to form stubs which are ideally located directly on top of the pillars 3 以 formed in the previous pattern and in the etching step. As shown in Figure 13c, some may occur The misalignment can be tolerated and can be reused in the patterning step for patterning the column 3 a mask of enamel. In this example, the layers 1 2 3, 11 8 are patterned in a patterning step different from the ruthenium layers 112 and 114 (and 116 formed in the subsequent ion implantation step). 1 2 1. This is needed to reduce the button height and avoid possible contamination by exposing the oxidized town and the metal I5 early wall layer to a chamber dedicated to the semiconductor surname. However, in other embodiments, Preferably, the layers 123, 118' 121, 116, 114, and 121 are patterned in a single patterning step. In the case of 119762.doc -39-1345783, the ions of the heavily doped layer ΐ6 are formed before the barrier layer 121 is deposited. Alternatively, the heavily doped layer 116 may be doped in situ. In some embodiments, the barrier layer 121 'the nickel oxide layer ι 8 and the barrier layer 123 may precede the diode layers 112, 114 and U6 (and thus Formed below, and may be patterned in the same or a separate patterning step. Next, a conductive material or stack is deposited to form the top conductor 4A. In a preferred embodiment, a titanium nitride barrier layer is subsequently deposited. 12〇, subsequently depositing an aluminum layer 122 and a top titanium nitride barrier layer 124. The top conductor 400 is patterned and etched as described earlier. In this example, in each cell, a diode (of layers 112, 114, and 116) and an impedance switching component (a portion of the nickel oxide layer 118) Between the top conductor 400 and the bottom conductor 2〇〇, the overlying second conductor 400 preferably extends in a direction different from the first conductor 2〇〇, preferably substantially perpendicular to the A conductor 2 〇 (the resulting structure shown in Figure i3c is the bottom or first layer of the memory cell. In an alternative embodiment, the top conductor may comprise copper and may be formed by a damascene process. A detailed description of the fabrication of the top copper conductors in the overall three-dimensional memory array is provided in detail in U.S. Patent Application Serial No. 11/125,606, the entire disclosure of which is incorporated herein to

Array Fabricated at Low Temperature Comprising Semiconductor Diodes" In a preferred embodiment, the first layer of the memory cell is a plurality of non-volatile memory cells including: a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction a first plurality of diodes; a first plurality of reversible impedance switching elements; and a second plurality of substantially parallel 'generally extending in a second direction different from the first direction 119762.doc -40 - 1345783 a conductor, wherein in each of the memory cells, the second of the first diode and the first reversible impedance switching element are arranged in series; one of the first conductor and the second conductor Between the two, and - a plurality of reversible impedance switching elements comprising: selected from the group consisting of: Material: Nlx〇y, Nbx〇y, I, Cai, ai^, C〇:〇; ^〇y 'Vx〇-Z^ forms a first conductor at a south degree and above the first height at a second height at a second height. Or a first conductor, which may form an additional pattern on the first memory layer' to share the conductor between the memory layers; that is, the top: the conductor will serve as the bottom conductor of the next memory layer. An interlayer dielectric is formed on the other first memory layer, the surface of which is: and the second memory reed body is started on the planarized interlayer dielectric. Does not have a common conductor). If the top 'down' is not shared between the memory layers, then the step (10) is not required for these conductors. In this case, the DARC layer can be used instead of the titanium nitride barrier layer to dope I: 2. When the deposited germanium is not well-doped or deposited with a lower temperature using an n-type dopant When it is normally non-low-voice 6 to construct all of the memory layers, the final relatively fine-annealing can be performed (eg, 'binding at a temperature between about 35 ° C and about 4 )) to crystallize Polar body. The actual "column in the column" will be sufficient to maintain a sufficient manufacturing throughput from multiple anneal-quantitative wafers (eg, 100 or 100 wafers). D9762.doc

直J between the memory layers and between the circuits of the substrate towel (iv) the direct interconnection may preferably be formed as a tungsten plug, which may be formed by any conventional method.

= Photomask is used to pattern each layer during photolithography. In each memory - repeat some layers' and the reticle used to form it can be reused. For example, 5, a reticle defining the post 300 of Figure 13c can be reused for each memory layer. Each reticle includes reference marks for proper alignment thereof. When re-used, the reference 11 formed in the second or subsequent use may interfere with the same reference that was formed during the previous use of the same-mask, US Patent Application No. (10)7, Masking f Repeated Overlay and Alignment Marks to Allow Reuse of Photomasks in a Vertical Structure'^ 2005, which is incorporated herein by reference, describes a method for forming an overall two-dimensional memory. A method of avoiding such interference during an array, such as the overall three-dimensional memory array of the present invention. , ^

Many variations of the steps and structures described herein are conceivable and may be required. In order to more fully illustrate the invention, some variations will be described; it will be understood that it is not necessary for those skilled in the art to fully detail every change in the scope of the invention to understand how to make and use one still more A wide range of possible changes. Second Manufacturing Example: Rare Metal Contact Above the Dipole Figure 1A shows an embodiment in which the impedance switching material 118 is sandwiched between the rare metal layers 117 and 119. Preferred rare metals are pt ' pd, k and Au. Layers 117 and 119 can be formed from the same rare metal or different metals. When the impedance switching material is lost between the rare metal layers, the pattern 119762.doc -42 - 1345783 must be patterned and the rare metal layers must be engraved to ensure that it does not provide undesirable conduction between adjacent diodes or conductors. path. A memory layer comprising cells (such as their cells) is shown in cross-section in FIG. In a preferred method for forming such a structure, as described earlier, the bottom conductor 2 is formed. The heavily doped germanium layer 112 and the undoped germanium layer 114 are deposited as described earlier. In a preferred embodiment, ion implantation of the top heavily doped layer ι 6 can be performed on the blanket layer prior to patterning and etching the pillar. A rare metal layer 117 is then deposited, followed by deposition of an impedance switching material 118 and a rare metal layer 119. The rare metal layers 117 and 119 may be from about 2 angstroms to about 500 angstroms, preferably about 2 angstroms. The pillars are patterned and etched at this point such that layers 7, 7, 8 and 9 are included in the pillars and are therefore electrically isolated from each other. Depending on the etchant selected, a first etch step can be performed to etch only layers 119, ι8 and η?, and then these layers are used as a hard mask to etch the remainder of the column. Alternatively, the layers can be first patterned and surnamed 1, 2, 114, and 116, filled with gaps therebetween, and exposed to the top of the columns via planarization. The deposition of layers u < 7, 118 and 119 can be followed by independent patterning and etching of the layers. The gaps are filled as described earlier and a CMp or etch back step is performed to create a substantially planar surface. Next, as described earlier, a top conductor 400 is formed on the planarized surface, and the top conductor 4A includes a titanium nitride layer 12, a layer m, and a titanium nitride layer 124. Alternatively, the top rare metal layer ι 9 can be deposited, patterned, and etched with the top conductor 4 . In another example, the heavily doped layer 116 can be replaced by a local push instead of ion implantation by 119762.doc -43 - 1345783. In the alternative embodiment shown in FIG. 15 under the diode, the impedance switching element 1 is sandwiched between the rare metal layers 117 and 119 in this case. Between the two is formed below the diode.

To form this structure, the bottom conductor 2〇〇 is formed as described earlier. Layers 117, 118 and 119 are deposited on the planarized surface 1〇9 of the conductor 2〇〇 separated by gap filling. The deposition of the heavily doped layer 112 and the undoped layer 114 is patterned as described earlier and the surnames 114, 112, 117 and (as appropriate) 117 are formed to form the pillars 3'. After the gap filling and planarization, the top (four) impurity region i 16 is formed by ion implantation. As in the prior art, the top conductor 4 is formed by depositing a conductive layer (e.g., a nitride layer, a layer 122, and a titanium nitride layer 124), and etching to form a conductor. And patterning. In the case of the gossip, if necessary, it can be independent of the layers 11〇, ι12,

114 and 116 are used to etch and etch layers 117, 118 and 119 instead of etching them in the single-patterning step. In the preferred sound & example described above, the formed object is an overall three-dimensional memory array, preferably sentenced., .... 八.3) a first memory layer formed on the substrate, the first memory The body layer comprises: 匕3. The first plurality of memory cells, 1 each of the first memory, '._° has a hidden body 70 containing a reversible impedance switching element' , 下,, and into the group of materials·· Nix0y'

NbxOy ' Tix〇 % A n 7 x y, AIx〇y, M is called ' c0x0y, Crx0y,

VxOy ' Znx〇 ' 7r 〇 r> vt y X y, X y&A]xNy;&b) is integrally formed in the first

Jl9762.doc -44 - 1345783 - at least one second memory layer on the memory layer. Many other alternative embodiments are envisioned. For example, the rare metal layers 117 and 119 may be omitted in certain embodiments. In this case, the impedance switching material 118 may be patterned with the bottom conductor 2, column 3, or as a continuous layer above the diode or under the diode. - the advantage of the embodiment just described - the advantage is that the use of the fault in the polar body allows the formation of a non-volatile memory cell by the following steps: forming a first guide

a second conductor; forming a reversible impedance switching element; and forming a diode, wherein the diode and the reversible impedance switching element are electrically connected in series between the first conductor and the second conductor, and wherein During the formation of the first conductor and the second conductor, the diode and the switching element, and the crystallization of the diode, the pulse does not exceed about 500 °C. Depending on the deposition and crystallization conditions used (longer crystallization annealing can be performed at lower temperatures), the temperature may not exceed about 350 °C. In an alternative embodiment, the deposition of the semiconductor material can be configured and

The crystallization temperature is such that the maximum temperature does not exceed 475t, 425 it, 4 〇〇 or 375. (: 〇 Fourth manufacturing example: Shi Xihua diode can be preferably formed (specifically, adjacent to a polycrystalline germanium crystallized by a telluride such as titanium telluride or cobalt telluride which can provide a favorable crystal template) Body, thereby forming a relatively low defect, low resistivity polysilicon. Referring to Figure 16a, the bottom conductor 2 can be formed as described earlier. Polycrystalline germanium generally requires a crystallization temperature that is incompatible with copper and aluminum, and thus can withstand high temperatures The material (such as tungsten) can be a preferred conductive material for the bottom conductor 2〇〇 106°

Il9762.doc -45- 1345783, as described in the application of Methodf piasma Etching Transition Metals and Their Compounds" ("Applied on June 11, 2005 and incorporated herein by reference") . The structure at this time is shown in Fig. 16a. Turning to Fig. 16b', in the case where the etched layers 121, Π8 and 123 are used as a hard mask during the etching of the titanium layer 125, the heavily doped p-type region 116 is continuously etched, The intrinsic region 114, the heavily doped n-type region 112, and the barrier layer 11(), thereby forming the pillars 300. A dielectric material ι 8 is deposited over the pillars 300 and between the pillars 300 to fill the gap therebetween. A planarization step (eg, by CMp) removes overfill of dielectric 108 and exposes optional barrier layer 123 (or barrier layer) on top of post 3〇〇 separated by filler 1〇8 If ι 23 is omitted, the nickel oxide layer 118 is exposed. Figure 16b shows the structure at this time. Referring to Fig. 16c, preferably, the top conductor 4 is formed as in the previous embodiment, and the top conductor 4 is a bonding layer 12 of, for example, titanium nitride and a conductive layer 130 of tungsten. An annealing step causes the titanium layer 125 to react with the tantalum region 116 to form titanium telluride. A subsequent higher temperature anneal crystallizes the germanium regions 116, 114 and U2 to form a relatively low defect, low resistivity polysilicon diode. Many variations in the formation of this memory unit are possible. For example, if preferred, the oxide layer 118 and any associated barrier layer 0 can be patterned and replicated in a separate step rather than in the same patterning step of forming the diode. The deuterated diode is noted. In a programmable embodiment in which the resistivity state of the polycrystal of the dipole is used to store the data 119762.doc -47· 1345783 state, it is preferable to form a non-adjacent formation. A polycrystalline germanium diode crystallized by a low-defect polycrystalline germanium. In this case, the bottom conductor 2〇〇 is formed as described above. The column 3 is formed as described in the first embodiment (except that the titanium layer 125 is omitted - in the other embodiment, it reacts with the enthalpy of the diode to form deuterated - titanium). Preferably, the nickel oxide layer 118 and any associated barrier layers are first patterned and etched and then used as a hard mask to etch the germanium regions 116, U4 φ and U2 and the barrier layer 110. Alternatively, the diode layers 116, 114, and 112 may be first patterned and etched, the gap between them filled with a dielectric, and the top of the diode exposed during the planarization step, followed by deposition of the nickel oxide layer 118 and its associated The barrier layer is then patterned and etched in a separate step. As in all embodiments, the first layer of memory cells has been formed. An additional memory layer can be stacked on the first memory layer to form an overall three-dimensional memory array that is preferably formed on the semiconductor substrate. • A single programmable three-dimensional memory array is described in the following patents and patent applications: US Patent No. 6, 〇34,882 "Vertically Stacked Field Programmable Nonvolatile Memory and Method of Fabrication"; Knall et al. American No. 6,420,215 "Three Dimensional Memory Array and

Method of Fabrication"; and Vyvoda et al., U.S. Patent Application Serial No. 10/185,507 "Electrically Isolated Pillars in Active

</ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; The memory array is a memory array in which a plurality of memory layers are formed on a single-substrate such as a wafer without an interposer substrate. A layer of a memory layer is deposited or grown directly on a layer of the existing one or more layers. Conversely, a stacked memory has been constructed by forming a memory layer on a separate substrate and attaching the 'memory layers to the top of each other, as in US Patent No. 5,915,167 &quot;Three dimensi (4) i struct prison Can be removed in combination with the layer of memory. But when the memory layer is initially formed on a separate substrate, the memory is not a true overall three-dimensional memory array. The overall three-dimensional memory array is formed on the substrate. And comprising at least a first memory layer formed at a first height on the substrate and a second memory layer formed at a second temperature different from the side of the edge. Forming three, four, eight or virtually any number of memory layers in the array on the substrate. Detailed fabrication methods have been described herein, but any other method of forming the same structure can be used, The present invention is intended to be limited only by the scope of the present invention. The following claims (including all equivalents) are intended to define the scope of the invention. [FIG. 1 is a perspective view of a possible memory unit having an impedance disposed between conductors. Switching the material. Figure 2 is a perspective view of a rewritable non-volatile memory cell 119762.doc -49· 1345783 formed in accordance with the present invention. Figure 3 is a block containing cells of such cells as shown in Figure 2. Perspective of the memory layer s Figure 4 is a l_V graph showing the low-high and high-low impedance transitions of the non-directional impedance switching material. Figure 5a is an IV graph, The low-to-high impedance conversion of the directional impedance switching material is shown. Figure SbSj-V plot showing the high-low impedance conversion of the directional impedance switching material. Figure 6 is in some embodiments of the invention Fig. 7 is a perspective view of a preferred vertically oriented Zener diode in another embodiment of the present invention. Fig. 8 is a ρ·ί· of the diode of Fig. 6. η: j_v graph of the polar body. Fig. 9 is a ρν graph of the Zener diode of the diode of Fig. 7. Fig. 10 is a perspective view of an embodiment of the present invention, in which the impedance switching material is clamped Between the rare metal layers. Figure 11a is a cross-sectional view illustrating an embodiment of the present invention in which the impedance switching material is unpatterned and etched. Figure 11b is a perspective view of a preferred embodiment of the present invention in which the impedance switching material and the top conductor are patterned and stenciled. Figure 12 is a diagram depicting current versus voltage for four different data states of a memory cell in one embodiment of the invention. Figures 13a-13c are cross-sectional views showing the M9762.doc -50-1345783 stage in the formation of a memory layer of an overall three-dimensional memory array formed in accordance with a preferred embodiment of the present invention. Figure 14 is a cross-sectional view illustrating a portion of an overall three-dimensional memory array formed in accordance with one preferred embodiment of the present invention. Figure 15 is a cross-sectional view illustrating a portion of an overall three-dimensional memory array formed in accordance with various preferred embodiments of the present invention. Figures 16a-16c are cross-sectional views' illustrating stages in the formation of a memory layer of an overall three-dimensional memory array formed in accordance with yet another preferred embodiment of the present invention.

[Main component symbol description] 2 Impedance switching memory component 4 Top conductor 6 Bottom conductor 12 Bottom heavily doped region 14 Intermediate nature region 16 Top heavily doped region

30 Diode 100 Substrate 102 Insulation layer 104 Adhesive layer / Titanium nitride layer 106 Conductive material / Tungsten layer / Conductive layer / Aluminum layer 108 Dielectric material / Dielectric filler / Dielectric 109 Flat surface 110 Barrier layer / Nitrogen Titanium layer 112 锗 layer / bottom heavily doped region / diode layer / heavily doped n-type region 119762.doc 1345783 114 split layer / diode layer / intrinsic region 116 top heavily doped region / diode layer / heavy doping Hetero-p-type region 117 Rare metal layer 118 Resistivity switching element/impedance switching element/nickel oxide layer 119 Rare metal layer 120 Titanium nitride adhesion layer/titanium nitride barrier layer 121 Optional barrier layer/conductive barrier material layer

122 aluminum layer 123 optional top barrier layer 124 top titanium nitride barrier layer 125 titanium layer 130 tungsten conductive layer 200 conductive rail / bottom conductor 300 column 400 top conductor

A area B area D area V, first voltage v2 voltage v3 voltage v4 voltage 119762.doc • 52-

Claims (1)

I34578J 〇96111498 Patent Application - Chinese patent application scope replacement (November 1999) v '10. Patent application scope: 1 · An overall three-dimensional memory array comprising: a) a first memory layer formed on a substrate, the first The memory layer includes: a first plurality of memory cells, wherein each of the first memory layers includes an impedance switching element, and the impedance switching element includes a resistivity switching metal oxide or a nitride compound a layer, the metal oxide or nitride compound having only one metal; and b) at least one second memory layer, /, formed integrally on the first memory layer. The first memory unit such as Hai can store one of a plurality of detectable data states, wherein the plurality of detectable data states includes at least three data states. 2. The overall two-dimensional memory array of claim i, wherein the plurality of detectable data states comprises at least four data profiles. For example, the overall two-dimensional ip of the item 1 is (3⁄4 Λ Λ. The hidden body array, wherein the metal oxide or nitride is selected from the group consisting of _ ^ &lt; group: NixOy, NbxOy, Tix〇y, x 〇y, CrxOy, VxOy, ZnxOy, 3. Hfx〇y 'AlxOy &gt; Mgx〇y . c〇〇4. Zrx〇y, BxNy and AlxNy. The overall three-dimensional memory array of claim 1 Wherein the substrate comprises a single 5. The overall three-dimensional layer of claim 1 further comprises a first plurality of memory arrays, wherein the first memory diode, wherein the first memory layer is 119762-991125.doc 1345783 Each of the memory cells includes one of the first diodes. 6. The overall three-dimensional memory array of claim 5, wherein each memory in the first memory layer is 亓φ, 蟑-Technical lying ^ , ,, 平 7甲甲, - The polar body and the impedance switching element are arranged in series. 7. The overall three-dimensional memory array of claim 6, wherein the first memory layer further comprises: a coplanar a conductor; and a second extending in a second direction different from the first direction a plurality of substantially parallel, substantially total of the first conductors, &quot; a second conductor located in each of the memory cells in the first memory layer, a :: body and the impedance switching component placement Between the first conductors and one of the second conductors. 8. The overall three-dimensional memory array of claim 7, wherein the layer further comprises a first plurality of a column &lt; ° memory in one of the first-conductors, a member of the vertical placement conductor and a second of the second conductors Dedicated to a conductor 9. The overall three-dimensional memory array of claim 7, or the second conductor comprises tungsten. 10. The overall three-dimensional memory _ of claim 7 or the second conductor comprises aluminum. An integral three-dimensional memory array, such as the first two diodes, wherein the first two polar bodies comprise 锗, 矽 or 锗 and / Or one of the alloys. 13. The overall three-dimensional memory array of claim 12, wherein the The diode consists essentially of a tantalum or a semiconductor alloy. The semiconductor alloy is at least 80 atomic percent. 14 methods for stylizing and sensing a memory array. The TM memory unit comprises: a metal oxide. = compound-resistivity switching layer, the metal oxide or nitride compound comprises exactly one metal; and a diode comprising a polycrystalline semiconductor material 'the resistivity switching layer and the diode are electrically connected in series: The method includes: applying a first stylized pulse to the memory unit that competes for the first stylized pulse: a) detectably changing a first resistivity state of the resistivity switching layer; or b Detectably changing a second resistivity state of the multi-day solar semiconductor material, or detectably changing the first resistivity state of the resistivity switching layer and detectably changing the polycrystalline semiconductor The second resistivity state of the material; and the second of the first electrically polycrystalline semiconductor material of the resistivity switching layer and the memory cell is adapted to read the memory bank by 〇(1) Wherein the resistivity state is used to store data and the resistivity state is used to store data, and three or more data states are stored 119762-991125.doc 1345783.15. The method of claim 14 wherein the memory unit Adapted to store four data states. 16. The method of claim 14 wherein the polycrystalline semiconductor material is polycrystalline germanium. 17. The method of claim 14, wherein the diode is a junction diode. 1 8. The method of claim 14, wherein the metal oxide or nitride compound is selected from the group consisting of NixOy, NbxOy, Tix〇y, HfxOy, Alx〇y, Mgx〇y, C°x〇y , CrxOy, VxOy, Znx〇y, ZrxOy, BxNy, and AlxNy. 19. The method of claim 18, wherein the metal oxide or nitride compound is selected from the group consisting of NiO, Nb205, Ti02, Hf02, Al2〇3, MgO, c〇〇, Cr02, VO, ZnO, ZrO , BN and AIN. 119762-991125.doc -4-