TWI345761B - Demultiplexer and the driving method and active display thereof - Google Patents

Description

13.45761

达达编号号: TW2870PA IX. Description of the Invention: [Technical Field] The present invention relates to an active display with a multiplexer, and more particularly to a multiplexer for providing a pre-write voltage to Active display of the child. [Prior Art] Referring to Fig. 1, there is shown a circuit diagram of a conventional multiplexer for an active display. The multiplexer 100 includes transistors TR, TG, and TB. The gates TRG, TGG and TBG of the transistors TR, TG and TB receive the control signals CR, CG and CB, respectively, and the source TRS, TGS and TBS respectively receive the data signal SD1, and the drains TRD, TGD and TBD are respectively Red, green, and blue sub-tenucine (not shown) coupled to the pixel unit of the display. The transistors TR, TG and TB output the data signal SD1 to the drains TRD, TGD and TBD when the control signals CR, CG and CB are enabled, respectively, to drive the red, green and blue sub-tengars respectively. The enable time of the control signals CR, CG and CB is staggered and equal to one third of the scan time of each scan line of the display. However, since the multiplexer 100 outputs the data signals to the red, green, and blue sub-tenucins in only one-third of the scanning time, the input time of each sub-data is shortened from one scanning time. For scanning one third of the time. The data voltage of each sub-study will be shortened due to the shortening of the input time of each sub-study data, so that the data voltage of each sub-form can not be charged or discharged to the voltage to be written, which affects the display effect of the display. But if you take 6 1345761

• Sanda Number: TW2870PA Increasing the size of the Thin Film Transistor (TFT) of the display to increase the charging and discharging speed of the sub-element, will reduce the aperture ratio (Aperture Ratio). Referring to Figure 2, there is shown another circuit diagram of a conventional multiplexer for an active display. The demultiplexer 200 includes eight transistor groups TS1 - TS8 for respectively driving eight sub-tenucins of a display (not shown). The transistor groups TS1 - TS8 receive the control signals DW1 - DW8, respectively, and the transistor group TSn has transistors TAn, TBn and TCn, η = 1 -8. The source TA1S-TA8S of the transistor -1 - ΤΑ8 are coupled to each other to receive the data signal SD2, and the drains TA1D - TA8D of the transistors TA1 - TA8 are respectively coupled to the eight sub-pictures of the plurality of pixel units of the display Prime (not shown). The gates TB1 - TB8 and TCI - TC8 gates TB1G - TB8G and TC1G - TC8G receive reset control signals SCBR1 - SCBR8 and SCCR1 - SCCR8, respectively. The TB1 - TB8 of the transistor and the TB1D- TB8D and TC1D- TC8D of the TCI-TC8 are also respectively coupled to the display of a plurality of 昼素翠元八子素 (not shown). The sources TB1 - TB8 and TCI - TC8 sources TB1S-TB8S and TC1S-TC8S receive the reset voltage SRS. The control signals DW1 - DW8 are mutually staggered, and the control signals DW1 - DW8 and the reset signals SCBR1 - SCBR8 are respectively shifted; the control signals DW1 - DW8 and the reset signals SCCR1 - SCCR8 are also shifted respectively. The reset voltage SRS is, for example, zero potential. The transistors TA1-TA8 input the data signal SD2 into eight sub-tenucins (not shown) when the control signals DW1-DW8 are enabled. Each transistor 7 1345761

Sanda number: TW2870PA TB1-TB8 and TC1-TC8 respectively, when the reset control signals SCBR1-SCBR8 and SCCR1 - SCCR8 are enabled, the reset voltage SRS is input into eight sub-pixels (not shown) to respectively eight The sub-pixel voltage of the individual element (not shown) is preset to the reset voltage SRS, and the effect of shortening the input time of the sub-genuine data of the eight sub-tenucine (not shown) is achieved. However, the conventional multiplexer uses three transistors to respectively drive the individual elements of the active display. Therefore, the conventional multiplexer needs to use a larger number of transistors, and is more complicated. The coupling structure makes the circuit structure of the traditional solution multiplexer complicated and costly. In addition, the conventional demultiplexer can only preset the sub-pixel voltage of the entire column of pixels to a reset voltage. Therefore, the traditional demultiplexer can only be applied to Row Inversion displays with the same voltage polarity for each column of pixels. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an active display with a multiplexer and a control method therefor. The multiplexer of the present invention has the advantages of simple structure and low cost. In addition, the multiplexer of the present invention can be applied to dot inversion and other types of display devices of the pixel voltage reversal type. According to the purpose of the invention, a demultiplexer is proposed. The demultiplexer includes a first drive unit and a second drive unit. The first drive unit includes a first transistor. The first electro-crystalline system has a first drain/source, a second drain/source, and a first gate. The first drain/source of the first transistor is connected to the first sub-element through the first transmission line, the second drain/source is coupled to the data line, and the first gate receives the first control 8 1345761

-' Nickname: TW2870PA • Signal. The first electro-crystal system is configured to turn the poor signal of the data line into the first sub-tend when the first control signal is enabled. The second drive unit includes second, third, and fourth transistors. The second transistor has a third drain/source, a fourth drain/source, and a second gate (four). The third drain/source of the second transistor is coupled to the second sub-element through the second transmission line, the fourth drain/source line f is connected to the data line, and the second gate receives the second control Signal. The second crystal system is used to input the data signal of the data line into the second sub-tend when the second control signal is enabled. The third transistor has a fifth pole/source, a sixth no, a source, and a third gate. The fifth pole/source of the third transistor is lightly connected to the second sub-halogen via the f-two transmission line, and the sixth pole/source is light. The hole number line, and the third gate receives the first set signal. The third transistor system is configured to input the first predetermined voltage into the second sub-element when the first setting signal is enabled. The fourth transistor has a seventh drain/source, an eighth drain/one source, and a fourth gate. The seventh no-pole/source of the fourth transistor is connected to the second sub-element through the first transmission line #, the eighth non-polar/source system is connected to the 帛^ signal line' and the fourth gate is received The second line number. The fourth electro-crystal system is configured to input the second predetermined voltage into the second sub-element when the second set signal is enabled. The P is staggered when the first control signal and the second control signal are enabled, and the enable times of the second control signal, the first setting signal, and the second setting signal are also shifted from each other. Root, another object of the present invention, is to provide a driving method for a display. The method of purchasing the excavator ^ is applied to the silk display 11 towel, and the active eve 2 system includes a stencil line, a halogen array, and a demultiplexer. The halogen array includes a first-small element and a second sub-halogen. Solution multiplexer system 9 1345761

The TW2870PA includes a first driving unit and a second driving unit to drive the first sub-element and the second sub-element. The driving method of the display includes the following steps. First, a first control signal is provided to enable the first transistor of the first driving unit to input the data signal on the data line into the first sub-pixel. Then, when the voltage of the second sub-halogen element is negative, a first setting signal is provided to enable the third transistor of the second driving unit to input the first predetermined voltage into the second sub-element. When the voltage of the second sub-halogen element is positive, a second setting signal is provided to enable the fourth electro-optic body of the second driving unit to input the second predetermined voltage into the second sub-element. Then, a second control signal is provided to enable the second transistor of the second driving unit to input the data signal on the data line into the third sub-tend. Then, repeat the above steps. According to still another object of the present invention, an active display is proposed. The active display includes: a pixel array, a data line, a first signal line, a second signal line, and a demultiplexer. The halogen array has a plurality of halogens, and each of the pixels includes a first daughter element and a second daughter element. The data line is used to output a data signal. The first signal line and the second signal line are used to provide a first predetermined voltage and a second predetermined voltage, respectively. The demultiplexer includes a first drive unit and a second drive unit. The first drive unit includes a first transistor. The first transistor has a first drain/source, a second drain/source, and a first gate. The first drain/source of the first transistor is coupled to the first sub-pixel via a first transmission line, the second drain/source is coupled to the data line, and the first gate receives the first control Signal. The first electro-crystal system is configured to input the data signal on the data line into the first sub-element when the first control signal is enabled. The second drive unit includes first, second, and third transistors. The second transistor has a third 汲 1345761

Three ^^: TW2870PA pole / source, fourth drain / source and second gate. The third drain/source of the second transistor is coupled to the second sub-halogen via the second transmission line, the fourth drain/source system _ to the data line, and the second gate receives the second control signal suddenly. The second electric crystal system is used to input the data line and the data signal into the second sub-tend when the second control signal is enabled. The third transistor has a fifth source, a source, a source, and a third gate. The fifth poleless/source of the third transistor is connected to the second sub-halogen via the second transmission_, the sixth poleless/coupled to the first signal, and the third_health-setting message~ The second crystal system is used for the first-set signal: the second, the second transistor has a seventh=/eight& pole/source and fourth pole. The seventh transistor of the fourth transistor has a fourth-pole transmission line. The fourth transmission line is secreted to the second sub-line, and the second signal line is connected to the second and fourth electric system. The voltage can be input to the second sub element. Elbow brother pre-understands::: wide features, and advantages can be more obvious and easy to understand, such as ί, and with the _ formula, for the detailed description [implementation], the invention of the solution of the multi-guard system using seven crystals And its corresponding news: through the two main players: each of the three elements in the display unit of the radio, the two sub-halogens are pre-charged and pre-discharged to reduce the number of transistors, And the solution multiplexer of the present invention can be used] 1345761

Sanda number: TW2870PA in the active display of Dot Inversion. Referring to Figure 3, there is shown a circuit diagram of a demultiplexer in accordance with a preferred embodiment of the present invention. This embodiment is described by taking a demultiplexer including three drive units as an example. The demultiplexer 300 includes drive units 302, 304, and 306. The driving unit 302 includes a transistor T1, the driving unit 304 includes transistors T2, T3, and T4, respectively, and the driving unit 306 includes the transistors T5, T6, and T7. The transistors Tl - T7 are, for example, N-type Metal Oxide Semiconductor (M0S) transistors, and each of the transistors Tl - T7 includes Drain TlD - T7D and Source TlS-T7S, respectively. , and Gate (Tate) TlG-T7G. The sources T1S, T2S and T5S of the transistors T1, T2 and T5 of the driving units 302, 304 and 306 are coupled to each other to form a signal input terminal 308 of the demultiplexer 300 for receiving the data signal SD. The gates T1G, T2G, and T5G of the transistors T1, T2, and T5 receive control signals SR, SG, and SB, respectively. The transistors T1, T2 and T5 output the data signal SD from the drains T1D, T2D and T5D when the control signals SR, SG and SB are enabled, respectively. The drain T1D is the output end 302a of the driving unit 302. The source T3S of the transistor T3 of the driving unit 304 and the source T4S of the transistor T4 are respectively used to receive the predetermined voltages Vss and Vdd. The gates T3G and T4G of the transistors T3 and T4 receive the setting signals PG1 and PG2, respectively. The transistors T3 and T4 output predetermined voltages Vss and Vdd to the drain T3D and the drain T4D when the setting signals PG1 and PG2 are enabled, respectively. Among them, the bungee T3D, T4D and T2D are coupled to each other to form a drive single 12 1345761

No. 3: 11: Output 304a of TW2870PA element 304. The control signal SG, the setting signals pgi and PG2 are mutually offset. The source T6S of the transistor T6 of the driving unit 306 and the source T7S of the transistor T7 are respectively used to receive the predetermined voltages Vss and Vdd. The gates T6G and T7G of the transistors T6 and T7 receive the set signals PB1 and PB2, respectively. The transistors T6 and T7 output the predetermined voltages Vss and Vdd to the drain T6D and the drain T7D when the setting signals PB1 and PB2 are enabled, respectively. The drains T6D, T7D and T5D are coupled to each other to form an output end 306a of the driving unit 306. The control signal SB and the setting signals PB1 and PB2 are staggered from each other. Next, please refer to FIG. 4 to illustrate the application of the multiplexer 300 disclosed in the embodiment to an active display. Figure 4 is a circuit diagram of an active display having a third graphical multiplexer. The active display 4A includes a data driver 402, a data line 404, a demultiplexer 300, a control device 406, transmission lines 408, 410, and 412, a pixel array 414, a scan driver 416, and a scan line 418. The pixel matrix 414 includes a plurality of pixels 420, and each of the pixels 420 includes sub-cells 422, 424, and 426. The data driver 402 is connected to the input terminal 308 of the demultiplexer 300 via the data line 404, and outputs the data signal Sd to the input terminal 308 via the data line 4〇4. The control device 406 is connected to the demultiplexer 300 via a plurality of signal lines 428, and the control device 406 outputs the control signals SR, SG and SB, the setting signals PGI, PG2, PB1 and PB2 and the predetermined voltage Vdd through the signal line 428. Vss to solution multiplexer 300. The output terminals 302a, 304a, and 306a are connected to the sub-salphone 13 through the transmission lines 408, 410, and 412, respectively.

Sanda number: TW2870PA For example, when pre-discharging the sub-satellite 426, the enabling time of the setting signal pB1 is substantially equal to the enabling time of the control signals SR and SG, and the enabling time of the scanning signal SC The 'control signal pB2' is disabled. In Fig. 5, the operation of precharging and pre-discharging the sub-books 424 and 426 by the setting signals PG2 and PB1 will be described as an example. The predetermined voltages Vss and Vdd are, for example, 〇 volts and 1 volt volts, respectively, and the starting voltages of the singular elements 422, 424, and 426 are 〇 volts. The data signal SD is equal to 0 volts, 10 volts, and 0 volts in the enable time of the control signals SR, SG, and SB, respectively, and the voltage of the common electrode is 5 volts. Therefore, the polarity of the data voltages of the data signals SD written to the sub-cells 422, 424, and 426 are negative polarity, positive polarity, and negative polarity, respectively. When the control § il SR is enabled, the control signal SR will enable the transistor Τ 1 ' to output the data §fl number SD to the infinity Τ 1D. At this time, the data signal sj) is 0 volts, so that the voltage of the drain T1D, that is, the output terminal 302a is 0 volt. The voltage at the output terminal 3〇2a is output to the sub-cell 422 via the transmission line 408, and the sub-element 422 is discharged, so that the sub-cell 422 is maintained at volts. At this time, the data of the sub-pixel 422 is negative. When the data signal SD of the input sub-cell 422 is negative, the data signals sd of the input elements 424 and 426 are positive polarity and negative polarity, respectively. Therefore, when the control signal SR is enabled, the setting signals PG2 and PB1 are also enabled. At this time, the setting signals PG2 and PB1 respectively enable the transistors T4 and T6 to output the predetermined voltages Vdd and Vss to the drain T4D and the drain T6D, respectively. At this time, there is no pole T4D and T6D, that is, the voltage system of the output terminals 304a and 306a 15 1345761

Three nicknames: TW2870PA is 10 volts and G volts respectively. The output terminal 3Q4a and the voltage to be output to the sub-cell 4a via the transmission lines 410 and 412 respectively are pre-charged and pre-charged to the sub-picture t 424 and the current line, respectively, and the data voltage of the sub-element 424 will be The volts began to charge. In particular, the data voltage of the sub-satellite 426 will continue to discharge to 10 volts. The data voltage of the halogen 426 is maintained at volts. Make

When the control signal is enabled, the control signal S (i will enable T2 to turn the data signal SD out to the bungee T2D. At this time, the data message is ίο volt, thus making the bungee T2D, that is, the output The voltage of the terminal 3〇4a° is 10 volts. At this time, the voltage of the output terminal 3〇4a is output to the sub-halogen 424 via the transmission line 41〇, and the sub-halogen 424 is continuously charged. The data voltage will continue to be charged to 10 volts. When the control signal SG is enabled, the setting signal PB1 continues to be enabled 'to enable the transistor T6 to output the predetermined voltage Vss to the drain T6D. At this time, the bungee T6D is also That is, the voltage at the output terminal 306a is 0 volts, and the voltage at the output terminal 306a is output to the sub-satellite 426 via the transmission line 412 to continue pre-discharging the sub-satellite 426. Therefore, the data voltage of the sub-satellite 426 at this time will be Continue to discharge to 0 volts, and the output terminal 302a is open circuit. When the control signal SB is enabled, the control signal SB will enable the transistor T5 to output the data signal SD to the drain T5D. At this time, the data signal SD Is 0 volts, thus making the drain T5D, that is, the voltage system of the output terminal 306a It is 0 volts, and the voltage at the output terminal 306a is output to the sub-halogen 426 via the transmission line 412 to discharge the sub-halogen 426.

Sanda number: TW2870PA and 304a are discontinuous discharge to °V. The output terminal 302a is disclosed in the embodiment, and the PB is separately detached from the setting device 300 through the setting signal.

Constant voltage Vdd and yss. If the voltages of a and 306a are preset to the pre-control signals SG and SB, the four sub-units 424 and 426 are respectively pressed at Vdd and VSS. Thus, the device is pre-charged and pre-discharged to a predetermined power and pre-discharged, so that the sub-book can be exaggerated to pass the pre-charge data voltage level. And the solution to the better sub-pixels and the 426 are better for the sub-pixels of the + 吴 吴 吴 吴 吴 吴 吴 吴 吴 吴 吴 吴 吴 吴 点 点 点 点 点 点 点 点 点 点 轭 轭 轭 轭 轭 轭 轭 轭 轭 轭 轭 轭Setting the signal PG2 and respectively, the output terminals such as the thresholds of the thresholds vhh » v 30 and 306a are preset to the pre-voltages Vdd and Vss as an example, 兮ηη ^ 0ΛΛ ^ J for illustration, however, this embodiment discloses The solution state 300 can also be used to set the output signal PG1 B2 in the frame period of χρια n PD〇'

The voltages of the enterprise, AH, and 306a are preset to the pre-voltages Vss and vdd. The solution of the fourth embodiment of the embodiment is to extend the control time of the control signal SR by the redistribution to extend the control signal SR to the monthly t*, and to moderately shorten the control signal %. The time is such that the control signals SR, SG and SB are still included in the sweeping time of the sweeping cat signal %. = The 'demultiplexer 3GG' will be able to extend/charge and discharge the sub-cells 322 of the pre-charging and discharging operation through the extended control signal SR, so that the sub-satellite 422 is charged and discharged to a better data voltage level. . May is referred to in Figure 6 and is illustrated in accordance with a preferred embodiment of the present invention. 17 1345761

Sanda number: Flow chart of TW2870PA multiplexer drive method. The driving method of the demultiplexer is applied to the active display 400. The multiplexer driving method disclosed in the preferred embodiment includes the following steps. First, in step 602, a control signal SR is provided to enable the transistor T1 of the driving unit 302 to transmit the data signal on the data line 404. SD input sub-pixel 422. Next, in step 604, when the data voltages of the sub-satellites 424 and 426 are positive, the setting signals PG2 and PB2 are provided to respectively enable the transistors T4 and T7 of the driving units 304 and 306 to respectively set the predetermined voltage Vdd. Input sub-pixels 424 and 426; when the data voltages of sub-satellites 424 and 426 are negative, provide setting signals PG1 and PB1 to enable transistors T3 and T6 of driving units 304 and 306, respectively, to respectively set predetermined voltages Vss inputs sub-singers 424 and 426. Then, in step 606, control signals SG and SB are provided to enable transistors T2 and T5 of driving units 304 and 306 to input data signals SD on data lines 404 to sub-units 424 and 426. Thereafter, in step 608, steps 602 through 606 above are repeated. The active display 400 is, for example, an active display including a RGB three sub-pixels, and the sub-cells 422, 424, and 426 are, for example, red, green, and blue sub-pixels. In this embodiment, the active display 400 with the resolution of 480*640 and dot inversion is taken as an example. However, the active display 400 disclosed in the embodiment is not limited to the above resolution and the pixel structure. For example, the active display 400 can also be an active display of sub-pixel voltage line inversion. Active 1345761

Sanda number: TW2870PA The display 400 can also be an active display having a pixel unit structure comprising four or more sub-units. The demultiplexer 300 disclosed in this embodiment may also include four or more driving units to respectively drive the active display 400 having four or more sub-cell structures. The multiplexer 300 disclosed in this embodiment is also not limited to the scan signal SC having an enable time equal to 27//s. The multiplexer 300 disclosed in this embodiment can shorten the scan signal SC and shorten the frame time of the active display 400. In the present embodiment, the operation of pre-charging the sub-halogen 424 and the pre-discharging of the 426 is described as an example. However, the sub-cell 424 is pre-discharged and 426 is pre-charged. Can be based on analogy. Please refer to Fig. 7, which is a timing diagram of another related signal of the active display according to Fig. 4. The enabling times of the control signals SR, SG and SB are substantially equal, and the lengths of the control signals SR, SG and SB are substantially equal to 9//S. In this embodiment, the multiplexer 300 is driven by the modified control signals SR, SG, and SB to achieve better results. However, the multiplexer 300 disclosed in this embodiment can also be used. It operates under the driving conditions of conventional control signals SR, SG and SB having substantially equal enabling times. The active display disclosed in the above embodiments of the present invention pre-charges and pre-discharges two sub-vegetators in an active display through a demultiplexer having seven transistors, The data voltage is pre-charged or pre-discharged to the highest voltage and the lowest voltage. Therefore this 1345761

• Sanda number: TW2870PA • The multiplexer 300 system disclosed in the embodiment can effectively solve the problem that the traditional multiplexer has a complicated structure and high cost, and can only be applied to the display of pixel points and column inversion. . In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

20 1345761 Sanda number: TW2870PA [Simple description of the drawing] Figure 1 shows a circuit diagram conventionally used in the active device. Figure 2 is a circuit diagram showing another conventional use for active work thieves. The fourth diagram of the active multiplexer of the multiplexer in accordance with the preferred embodiment of the present invention is shown in FIG. 4 as a third diagram of the multiplexer circuit diagram. . The μ Ϊ ^ 1 will show the timing diagram of the signal related to the active display in accordance with Figure 4. Figure 6 is a flow chart showing a method of driving a multiplexer in accordance with a preferred embodiment of the present invention. The system is not based on the other related information of the active display in Figure 4.

21 1345761

Sanda number: TW2870PA [Description of main component symbols] 100, 200, 300: Demultiplexer TR, TG, TB, TA1 - TA8, TB1 - TB8, TCI - TC8, T1 - T7: Transistor TRG, TGG, TBG , TA1G-TA8G, TB1G-TB8G, TC1G-TC8G, TIG-T7G: Gate TRD, TGD, TBD, TA1D-TA8D, TB1D-TB8D, TC1D - TC8D, T1D - T7D: Bungee

TRS, TGS, TBS, TA1S-TA8S, TB1S-TB8S, TC1S-TC8S, T1S-T8s: Source CR, CG, CB, DW1 - WD8, SR, SG, SB: Control signals SD1, SD2, SD: Data signal SDR1, SDG1, SDB1: sub-plasma data TS1 - TS8: transistor group SCBR1 - SCBR8, SCCR1 - SCCR8: reset control signal SRS: reset voltage 302, 304, 306: drive unit 302a, 304a, 306a: output 308: input

Vss, Vdd: predetermined voltage PG1, PG2, PB1, PB2: setting signal 400: active display 402: data driver 404: data line 22 1345761

Sanda number: TW2870PA 406: Control device 408, 410, 412: Transmission line 414: Picture array 416: Broom driver 418: Scan line 420: Alizarin 422, 424, 426: Subcell 428: Signal line SC: Broom signal 602 - 608: steps

twenty three

Claims (1)

1345761 Sanda number: TW2870PA X. Patent application scope: 1. An active display comprising: a pixel array having a plurality of pixels, each of which includes a first sub-element and a second sub-pixel; a data line for transmitting a data signal; a first signal line for providing a first predetermined voltage; and a second signal line for providing a second predetermined voltage; And a demultiplexer, comprising: a first driving unit, comprising: a first transistor (Transistor) having a _Drain/Source and a second drain a source/gate and a gate, the first drain/source is coupled to the first sub-element through a first transmission line, and the second drain/source is coupled to the data line The first gate receives a first control signal, and the first transistor system inputs the data signal on the data line to the first sub-cell when the first control signal is enabled; and the first driver Early element, including: a first transistor with a third pole/source a fourth drain/source and a second gate, the third drain/source is coupled to the second sub-element via a first transmission line, and the fourth drain/source is coupled to the The second gate receives a second control signal, and the second transistor system inputs the data signal of the data line to the second sub-genogen when the second control signal is enabled; a three-transistor having a fifth drain/source, a 24 1345761. Sanda number: TW2870PA sixth drain/source and a third gate, the fifth drain/source via the second transmission line The second gate/source is coupled to the first signal line, the third gate receives a first set signal, and the third transistor system is coupled to the first When the signal is enabled, the first predetermined voltage is input to the second sub-pixel; and a fourth transistor 'has a seventh drain/source, an eighth drain/source, and a fourth gate The seventh drain/source is coupled to the second sub-element through the second and second pass wires, and the eighth drain/source is coupled to the second signal line, the first The gate receives a second setting signal, and the fourth transistor system inputs the second predetermined voltage into the second sub-pixel when the second setting signal is enabled; /, wherein the first control signal and the The enabling time of the second control signal is staggered' and the enabling time of the second control signal, the first setting signal, and the second setting signal are mutually offset. 2. As described in claim 1 The active display, wherein the active display further comprises: ', y a scan driver coupled to at least one scan line, the scan driver is configured to output at least one female cat signal to drive the selected cat line sweep The cat is the first child and the second child. The active display of the present invention, wherein the activation time of the broom signal comprises the activation time of the first control signal and the second control signal. 4. The active display of claim 1, wherein the length of the first control signal is greater than or equal to the second 25 1345761 • the three-digit number: the length of time of the TW2870PA control signal . 5. The active display of claim 3, wherein the first predetermined voltage and the second predetermined voltage are respectively a voltage minimum and a voltage maximum of the data signal. 6. The active display of claim 1, wherein the first setting signal is used to control the second sub-plasma to perform pre-discharge, and the second setting signal is used to control The second scorpion is pre-charged. 7. The active display of claim 6, wherein the multiplexer pre-charges and pre-discharges the second sub-pixel in a different frame period. 8. The active display of claim 6, wherein the first setting signal is the same as the enabling time of the first control signal when the second sub element is precharged. 9. The active display according to claim 6, wherein the second setting signal is the same as the first control signal when the second sub element is pre-discharged in the φ . 10. The active display of claim 2, wherein the active display further comprises: a control device for providing the first control signal, the second control signal, the first setting signal, a second set signal, the first predetermined voltage, and the second predetermined voltage. 11. The active display of claim 1, wherein the demultiplexer further comprises three driving units for respectively driving the pixel array 26 1345761. The three sub-numbers: TW2870PA Russell. 12. The active display of claim 1, wherein the active display is a sub-pixel Dot Inversion active display. 13. A display driving method for an active display, the active display comprising a data line, a pixel array, and a demultiplexer, the pixel elements of the pixel array respectively comprising a first sub-system and a second sub-system, the demultiplexer includes a first driving unit and a second driving unit to respectively drive the first sub-tenox and the second sub-tendin, The driving method includes: (a) providing a first control signal to enable one of the first driving unit, the first transistor, to input the data signal of the data line into the first sub-element (b) when the voltage of the second sub-halogen element is positive, providing a first setting signal to enable a third transistor of the second driving unit to input a first predetermined voltage The second sub-tendin; when the voltage of the second sub-halogen is negative, providing a second setting signal to enable the fourth transistor of the second driving unit to be a second a predetermined voltage is input to the second sub-genogen; (c) providing a second control signal No. a second transistor is enabled to input a data signal of the tributary line to the second sub-small element; and (d) repeating the above steps (a) to (c). 14. The driving method according to claim 13 wherein 27 13.45761 Sanda number: TW2870PA The active display further comprises: ^ a scan driver coupled to at least one scan line, the scan driver being used The at least -_ signal is output to drive the wire to sweep the second sub element of the cat and the second sub element. The driving method of claim 13, wherein the enabling time of the broom signal comprises an enabling time of the first control signal and the second control signal. The driving method of claim 13, wherein the first control signal has a time length greater than or equal to an enabling time length of the second control signal. The driving method of claim 13, wherein the first predetermined voltage and the second predetermined voltage are respectively a voltage minimum value and a voltage maximum value of the data δίΐ on the data line. 18. The driving method according to claim 13, wherein in the step (1), when the second sub-tend is pre-charged, the first attack signal and the first control signal are caused The time can be the same. The driving method of claim 13, wherein in the step (b), when the second sub element is pre-discharged, the first sigh signal and the first control signal are The enabling time is the same. The driving method of claim 13, wherein the active display is in a different frame scan cycle (Fr Tever Per (10) pre-charges and pre-discharges the second sub-pixel. In the driving method of claim 13, the active display further includes: eight 28 1345761 Sanda number: TW2870PA a control device for providing the first control signal, the second control signal, the The first setting signal, the second setting signal, the first predetermined voltage, and the second predetermined voltage. 22. The driving method of claim 13, wherein the demultiplexer further comprises three driving a unit for driving the three sub-pixels of the pixel of the pixel array. 23. The driving method of claim 13, wherein the active display is a sub-pixel voltage dot inversion (Dot Inversion) An active display. 24. A demultiplexer for use in an active display, the active display comprising a pixel array, a data line, a first signal line, and The second signal line, the pixel array has a plurality of pixels, each of the pixels includes a first sub-element and a second sub-element, the data line is for outputting a data signal, the first The signal line and the second data line are respectively configured to provide a first predetermined voltage and a second predetermined voltage. The demultiplexer includes: a first driving unit, comprising: a first transistor (Transistor) having a first gate/source, a second gate, a pole/source, and a first gate, the first gate/source being coupled to the first sub-pixel via a first transmission line, The second gate/source is coupled to the data line, and the first gate receives a first control signal, and the first transistor system inputs the data signal on the data line when the first control signal is enabled. The first sub-cell; and a second driving unit, comprising: 29 Ι3·45761 Sanda number: TW2870PA a second transistor having a third pole/source, a fourth drain/source and a second gate, the third drain/source is coupled to the second sub-tenon via a second transmission line The fourth drain/source is coupled to the data line, the second gate receives a second control signal, and the second transistor system transmits a data signal on the data line when the second control signal is enabled. Inputting the second sub-tendin; a third transistor having a fifth drain/source, a sixth drain/source, and a third gate, the fifth drain/source via the first The second transmission line is coupled to the second sub-element, the sixth drain/source is coupled to the first signal line, the third gate receives a first set signal, and the third electro-crystal system is in the When a set signal is enabled, the first predetermined voltage is input to the second sub element; and a fourth transistor has a seventh drain/source, an eighth drain/source, and a fourth a gate, the seventh drain/source is coupled to the second sub-element via the second transmission line, the eighth drain/source is coupled to the second signal line, and the fourth gate receives a a second setting signal, the fourth electro-optic system is configured to input the second predetermined voltage into the second sub-genogen when the second setting signal is enabled; wherein the fourth And the second control signal of the control signal is enabled time-based offset, and the second control signal, the first signal set, the second set of signal lines can be induced staggered times. 25. The multiplexer of claim 24, wherein the active display further comprises: a scan driver coupled to the at least one scan line, the scan driver 1345761,, the three-number: TW2870PA 33 The multiplexer of claim 24, wherein the active display further comprises: a control device for providing the first control signal, the second control signal, the first setting signal, a second set signal, the first predetermined voltage, and the second predetermined voltage. 34. The demultiplexer of claim 24, wherein the demultiplexer further comprises three drive units to respectively drive the three sub-tenks of the pixels of the alizarin array. The multiplexer of claim 24, wherein the active display is a sub-inverted Dot Inversion active display. 32