1343623 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種佈線結構與方法，特別是一種多相位佈線結構與方 法。 【先前技術】 傳統技術上，多相位信號的佈線常因為信號線過長，造成延遲。晶圓 製程雖尚未進人深次微米等級，但已㈣要_注意佈_翅，以避免 造成嚴重的餘電容效應。制是在佈線的安排上，更顯職慎注意過 長的走線，是否會造成過大的系統延遲。 傳統的走線安排上，主要是在不違反晶圓廠的設計準卵esignruies)下 進行佈局。然實際上’在電路佈局中，走線彼此之間會存在轉合電容㈣㈣ capacitance)，使得實際電路的非理想效應會比一般預估的嚴重。特別是針 對比較誠的臟電路，若賴比電_走線鶴在數位電_近，所造 成的干擾會更加嚴重。 再者示了叙s電谷所造成的影響之外，更包含多相位間延遲時間㈣叮 _的影響。請參照「第1A圖」為習知技射，多相位信號線的佈局示意 圖。雖然各信銳鱗長’然由於從各錢線所看人之貞載（例如：輕合 電容）並不完全相同’所以各信號線上的信號，由輸人端到輸出端的延遲 時間(tdO tdl.，.)也不會全部相同__厂）。而各個相位之間的延遲時間 沒有完全_ ’將影響到電路的特性、效_現。因此，習知技術中提 出另-種多相位信號線的佈局方式，請參照「第m圖」。其中，「第叫 5 1343623 各個相位的錢由輸人劇輸出端的相等。以「第a圖」的佈局 方式部有其他缺點。例如··如此的佈局方式，嶋較大的佈局面積。 因此，如健決在佈局料巾，_合電容峨.縛，為—亟待解 決的問題。 【發明内容】 有锻於此本發明提出來傳輸多相位錢的佈局結構，能有效解 决夕相位信號之間的延遲時間所產生的影響。利用幾何對稱機制或電性對 稱機制，料相位之間_合電容能彼此互相匹配。 本發明提出-種用來傳輸多相位信號的佈局結構，包含：—第一佈局 層；-第二佈局層’與第-佈局層實質上互相平行；複數條走線，每條走 線各傳輸-魏’而複數個賤各具有—她差；其中，設置於第一佈局 層與第二佈局層之同一層而相鄰的二條走線之間具有一水平轉合電容，設 於第佈弱與第二佈局層之不同層^相鄰的二條該走線之間具有一垂 直輪合電容，而複數條走線由水平耗合電容與垂直耗合電容所決定的她耦 合電容實質上相同。 ^ 一本發明亦提出另—種佈線方法，包括下列步驟：提供—第—佈局層斑 :第二佈局層’ I佈弱與第二編實f上互相平行；形成複數條信 ;線’、中-X置於第-佈局層與第二佈局層之同—層而相鄰的二條信號 線間具有-水平私電容值’設置於第—佈局層與第二佈局層之不同層而 !鄰=二條信號線之間具有—垂直齡電容值，而複數條信觀由水平編 。電谷與垂直㉟合電容所蚊聽齡電容實質上相同。 6 本發明亦提以„觀來傳輸多相 佈局層，·一第二体月思★ α 一佈局結構’包含：一第一 一佈局層與第二佈邪；’㈣—佈弱互卿行；複數個位置點，位於第 線各傳D 0 ’歧條走線’對軌置於錄置點，每條走 係「W，複數個信號各相隔—相位差，設置於第—佈弱與第二 °同層而相鄰的二條走線之間具有一水平耗合電容，設置於第- 2局層與第—佈局層之不同層而相鄰的二條走線之間具有—垂直輕合電 合母條走線各包含複數個區段，在不同區段走線與位置點之配置不同， 使複數條走線由水平耗合電容與垂絲合電容所決定的電氣特性實質上相 1^1 〇 有關本發明的較佳實施例及其功效，兹配合圖式說明如后。 【實施方式】 在解釋本發明前，請先參照「第2A圖」為原理解說圖(一）。「第2A圖」 中走線a用以傳輸乂乂電壓信號，而走線b用以傳輸-V)C電壓信號，也就是 說走線a與走線b所傳輸的信號其相位相差丨80度。利用底下公式之推導， 可將「第2A圖」中左邊的電路等效為右邊的電路。 C =吾…(1) ; i = ^...(2) ; i = CfxA...(3); V dt dt 將(2)式代人(3)式：虫= Cfxf ...(4); dt dt 單位時間内電壓的變化量為Vx-(-Vx)=2Vx，所以（4)式為： q = Cfx2V...(5)，將(5)式代入(1)式：C = 2Cf。 接著請參照「第2B圖」為原理解說圖(二）。圖中所示’走線a傳輸一 1343623 正弦信號相嫩s—身），走線鳴之號相位料—t， 走線C傳輪之正弦信號相㈣為W。）。其中，走線a與走線C所傳 輸的信號其相位相差⑽度。所以，利用上述「第2A圓」所推導的结果， 當走線a、走線b之輸合電容與走線b、走線e之間_合電容兩者互 相匹配時，「第則」⑽的電路可以等效為右邊的電路。因此，告走 線之間彼此電容互祕配時，電容所產”貞喊料可視為敎不見。 請參照「第2C圖」，該圖所示為本發明第一實施例之示意圖㈠。第一 實施例中多相位信號的佈局結構包含：第—佈局層ω、第二佈局層12、第 一走線30、第二走線4〇、第三走線5〇及第四走祕該第—走㈣、第 二走線如1三植衫四植的_纽職#四料她信號， 該四條多相位信號之相位係分別為〇度、9〇度、i8〇度、及挪卢。為方 便說明該先參照「第2C圖」之前半部份，即是「第犯圖」。 在「第2〇圖」中’第一佈局層10與第二佈局層U互相平行’且其中 ^佈局層H)具有第-位置點2〇與第四位置點％，而第二佈局層η具有 第一位置點22與第三位置點24。 走線之間具有耗合電容，例如，設置於第—佈局層iq與第二佈局層η 相鄰的二條走線之間具有水平·電容Ch,如「第2D圖」中 所不’第一走線30與第四走線6〇之間具有水平轉合電容❹，以及第二走 =〇與之間也同樣具有水輪合電容.另—方面設置於 六一以局如層與第第二佈局層之不同層而相鄰的二條走線之間具有垂直搞合電 ♦帛㈣」Μ示’第-走線30與第二走線4〇之間具有垂直 81343623 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a wiring structure and method, and more particularly to a multi-phase wiring structure and method. [Prior Art] Conventionally, the wiring of a multi-phase signal is often caused by a delay in the signal line being too long. Although the wafer process has not yet entered the deep micron level, it has been (4) to pay attention to the cloth to avoid serious residual capacitance effects. The system is in the arrangement of the wiring, and it is more careful to pay attention to the long route, whether it will cause excessive system delay. The traditional routing arrangement is mainly based on the layout of the fab's design esignruies. In fact, in the circuit layout, there will be a transfer capacitor (four) (four) capacitance between the traces, so that the non-ideal effect of the actual circuit will be more serious than the general estimate. Especially for the more dirty circuits, if the Lai _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In addition to the effects caused by the s electric valley, it also includes the influence of the multi-phase delay time (four) 叮 _. Please refer to "1A" for a schematic diagram of the layout of multi-phase signal lines. Although each letter is sharp and long, 'because the people from the money line (for example: light-combined capacitors) are not exactly the same 'so the signal on each signal line, the delay time from the input end to the output end (tdO tdl .,.) will not all be the same __ factory). The delay time between the phases is not completely _ ′ will affect the characteristics of the circuit, the effect _ now. Therefore, in the prior art, a layout method of another multi-phase signal line is proposed, please refer to "mth picture". Among them, "The money of each phase of the 5th 5,436,623 is equal to the output of the input drama. There are other disadvantages in the layout of the "A". For example, such a layout method, a large layout area. Therefore, if the health is in the layout of the towel, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ SUMMARY OF THE INVENTION There is a layout structure in which the present invention is proposed to transmit multi-phase money, which can effectively resolve the influence of the delay time between the phase signals. Using a geometric symmetry mechanism or an electrical symmetry mechanism, the _ capacitances between the material phases can match each other. The present invention proposes a layout structure for transmitting a multi-phase signal, comprising: a first layout layer; a second layout layer and a first layout layer are substantially parallel to each other; a plurality of traces, each of which is transmitted - Wei' and a plurality of 贱 each have - she is poor; wherein, the first layout layer and the second layout layer are on the same layer and the adjacent two traces have a horizontal transfer capacitance between the two The two traces adjacent to the different layers of the second layout layer have a vertical turn-on capacitance, and the plurality of traces are substantially the same as the coupling capacitance determined by the horizontally-combined capacitance and the vertical-combined capacitance. ^ The invention also proposes another wiring method comprising the steps of: providing - a layout layer spot: the second layout layer 'I cloth weak and the second code f are parallel to each other; forming a plurality of letters; line ', The middle-X is placed in the same layer of the first layout layer and the second layout layer, and the adjacent two adjacent signal lines have a horizontal private capacitance value set at different layers of the first layout layer and the second layout layer. = There is a vertical age capacitance value between the two signal lines, and a plurality of letter views are programmed horizontally. The electric valley and the vertical 35-capacitor have substantially the same age. 6 The present invention also proposes to transmit a multi-phase layout layer, a second body month, and a layout structure including: a first layout layer and a second cloth evil; '(four) - cloth weak mutual clear line ; a plurality of position points, located on the first line, D 0 'disparate line' is placed at the recording point, each line is "W, multiple signals are separated by each other - phase difference, set in the first - cloth weak and The second phase is in the same layer and the adjacent two traces have a horizontally-combined capacitance, and are disposed in different layers of the second to the second layer and the first layout layer, and have two vertical alignments between adjacent two traces. The electrical mating busbars each include a plurality of sections, and the arrangement of the different sections of the traces and the position points is different, so that the electrical characteristics of the plurality of traces determined by the horizontally-combined capacitance and the vertical-wire capacitance are substantially The preferred embodiment of the present invention and its effects will be described later with reference to the drawings. [Embodiment] Before explaining the present invention, please refer to "2A" for the original understanding of Figure (1). In Figure 2A, trace a is used to transmit the 乂乂 voltage signal, and trace b is used to transmit the -V) C voltage signal, that is, the phase difference between the signal transmitted by trace a and trace b 丨 80 degree. Using the derivation of the underlying formula, the circuit on the left in "A2A" can be equivalent to the circuit on the right. C = I...(1) ; i = ^...(2) ; i = CfxA...(3); V dt dt Put (2) into the formula (3): worm = Cfxf ...( 4); dt dt The amount of change in voltage per unit time is Vx-(-Vx)=2Vx, so (4) is: q = Cfx2V...(5), substituting (5) into equation (1): C = 2Cf. Next, please refer to "2B" for the original understanding of Figure (2). In the figure, the 'route a transmits a 1343623 sinusoidal signal s-body', the line sings the phase material-t, and the sine signal phase (4) of the line C transmission wheel is W. ). Among them, the signal transmitted by the trace a and the trace C is out of phase (10) degrees. Therefore, when the result of the above-mentioned "2A-circle" is used, when the input capacitance of the trace a and the trace b and the trace b and the trace e match each other, "the first" (10) The circuit can be equivalent to the circuit on the right. Therefore, when the mutual capacitance between the lines is matched, the "sound" produced by the capacitor can be regarded as missing. Please refer to "2C", which is a schematic view (1) of the first embodiment of the present invention. The layout structure of the multi-phase signal in the first embodiment includes: a first layout layer ω, a second layout layer 12, a first trace 30, a second trace 4〇, a third trace 5〇, and a fourth trace The first-going (four), the second line, such as 1 three-shirt four-planted _ New job # four material her signal, the phase of the four multi-phase signals are 〇, 9 、, i8 、, and Nolu . For the sake of convenience, the first half of the "Cth 2C" is referred to first. In the "second map", 'the first layout layer 10 and the second layout layer U are parallel to each other' and wherein the layout layer H) has a first-position point 2 〇 and a fourth position point %, and the second layout layer η There is a first position point 22 and a third position point 24. There is a consuming capacitance between the traces. For example, a horizontal capacitance H is provided between the two traces adjacent to the first layout layer iq and the second layout layer η, as in the "2D map". There is a horizontal turn-on capacitance ❹ between the trace 30 and the fourth trace 6〇, and the second pass=〇 also has a water wheel capacitor. The other aspect is set on the six-one board and the first The two layers of the layout layer have vertical alignment between the two adjacent traces. 帛 (4) Μ indicates that there is a vertical between the first trace 30 and the second trace 4
相合電谷Cv ’以及第四走線6〇與第三走線5〇之間也同樣具有垂直耦合電 v。由第2D圖可知’各走線相鄰的二走線所傳輸的信號之相位差180 列如’第一走線3〇相鄰的二走線為第二走線4〇以及第四走線6〇，且 讀第一走線40與第四走線6〇傳輸的信號的相位分別為9〇度以及27〇度(_9〇 X)’第—走線40相鄰的二走線為第一走線30以及第三走線50,且該第一 走線30與第二走線5〇傳輸的信號的相位分別為〇度以及18〇度；同理， 第-走線5G相鄰的二走線為第二走線4()以及第四走線6()，以及第四走線 60相鄰的二走線為第一走線3〇以及第三走線5〇。由帛2B圖的原理解說 圖’可得此佈線結構可消除耦合電容的影響。此絲結構鋪由—幾何對 稱機制以達到消除耦合電容的影響。The coincident electric valley Cv' and the fourth trace 6〇 and the third trace 5〇 also have a vertical coupling electric v. It can be seen from Fig. 2D that the phase difference of the signals transmitted by the two adjacent lines of each trace is 180 columns such as 'the first trace 3 〇 the adjacent two traces are the second trace 4 〇 and the fourth trace 6〇, and the signals transmitted by the first trace 40 and the fourth trace 6〇 are respectively 9 以及 degrees and 27 ( degrees (_9〇X) 'the first line of the adjacent line 40 is the first a line 30 and a third line 50, and the signals transmitted by the first line 30 and the second line 5 are respectively twisted and 18 degrees; similarly, the first line 5G is adjacent The second trace is the second trace 4 () and the fourth trace 6 (), and the second trace adjacent to the fourth trace 60 is the first trace 3 〇 and the third trace 5 〇. According to the original understanding of Fig. 2B, the wiring structure can eliminate the influence of the coupling capacitance. This wire structure is paved by a geometric symmetry mechanism to eliminate the effects of coupling capacitance.
清再參照「第2(：圖」。特別是參照「第2C圖」之前半部以及後半部， D發見第2C圖」之後半部的佈線係是「第2C圖」之前半部順時針旋轉 度。請參照「第2C圖」，由第2C圖示可知，第一走線3〇包含第一區段 31與第一區段32，第二走線⑽包含第—區段與第二區段犯，第三走線 包含第-區段51與第二區段52，第四走線⑼包含第—區段μ與第二 區& 62。也就疋說，將各走線的第一區段順時針旋轉如度，即可得到各走 線的第二區段所設置之位ρ於此，祕於稱針旋㈣度，逆時針旋轉 9〇度也可達到相同功效。此外，由财可看出，第一走線％〜第四走輯 ”的第，與_條走線之另—的第—區段實質上係上下重叠 (〇吻）。例如，第-走線之第—區段31與第二走線之第—區㈣上下 重疊：第四走線之第-區段61與第三走線之第—區段Μ也為上下重疊。For the second half of the "second picture", the second half of the "second picture" is clockwise. For the degree of rotation, please refer to "2C". As can be seen from the 2C, the first trace 3〇 includes the first segment 31 and the first segment 32, and the second trace (10) includes the first segment and the second segment. In the segment, the third trace includes a first segment 51 and a second segment 52, and the fourth trace (9) includes a first segment μ and a second region & 62. In other words, each trace is The first section rotates clockwise by degrees, so that the position ρ of the second section of each trace can be obtained, and the same effect can be achieved by rotating the needle by four degrees and counterclockwise by 9 degrees. As can be seen from the wealth, the first line of the first line to the fourth line, and the first part of the line of the _ line are substantially overlapped (〇 kiss). For example, the first line The first segment 31 overlaps with the first region (four) of the second trace: the first segment of the fourth trace and the first segment of the third trace are also vertically overlapped.
丄J ;'、、H兒明’各走線中的第—區段與第二區段之間是彼此互相連 接的。「第 2Γ1 isi 〇,, 、、 」中’為了方便說明，才將各走線的第一區段與第二區段 、’方式來表不。此外每條走線的第—區段之長度可以等於第二區段之 長度。 吞青參·昭「楚OC1 Γβ) >L· r 」為第2C圖」的俯視圖，由該俯視圖可以更清楚 各走線於第-佈局層與第二佈局層的配置方式。圖中以粗線代表位於 2佈局層的走線，以細線代表位於第二佈局層的走線。由圖所示，可以 '月楚看出各走線的第_區段與第二區段皆為互相連接。 凊續參照「第2C圖」，第四走線之第__區段61與第—走線之第一區段 31間具有水平耗合電容Ch，而第四走線之第二區段62與第-走線之第二 區段幻間具有垂錄合電容Cv，所以，第_走線鄕四走__合電 谷係為水平Μ合電容Ch與垂直鮮電容〜並聯。_可知，各走雜相 鄰走線間的输上相物，_合咖h與咖合電 容⑺並聯），峰舰對稱。如此，可使彳衫—走㈣、第二走線仙、 第二走線50及第四走線60中，由水平輕合電容ch與垂直輕合電容〜所 決定的電氣特性實質上相同。 由上述推導可知，每條走線之間的總耗合電容皆為水平輕合電容⑶並 聯咖合電W，各綱_嫩值响上為⑽。 請參照「第3A圖」，該圖所示為本發明第二實施例之第一示意圖。於 此實施例中，同樣每條走線皆包含二個區段。與「第犯圖」的差異在於， 第二實施财，第二走㈣的㈣段41與第高以配置的位置點 10 1343623 皆-致，均位於第二位置點22。同樣的，細走線6G的第—區段&與第 二區段62所配置的位置點皆一致，均位於第四位置點％。走線中只有第一 走線30與第三走線5〇的第區段與第二區段設置的位置點有所不^由 圖中可見’此佈線設計侧樣使得每條走線之__合電容皆為水平輛 合電容Ch加上垂純合電容Cv’達到各走線之_總_合電容互相匹配。第J; ', H, Ming' The first section and the second section of each of the traces are connected to each other. "The 2nd 1 isi 〇, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In addition, the length of the first segment of each trace may be equal to the length of the second segment. The plan view of the second layout is shown in Fig. 2, and the arrangement of the traces on the first layout layer and the second layout layer can be more clearly seen from the plan view. In the figure, the thick lines represent the traces located in the 2 layout layer, and the thin lines represent the traces located in the second layout layer. As shown in the figure, it can be seen that the first and second sections of each trace are connected to each other. Referring to the "2Cth diagram", the __ section 61 of the fourth trace has a horizontal consumption capacitance Ch between the first section 31 of the first trace and the second section 62 of the fourth trace. The second section of the first-line has a recording capacitance Cv. Therefore, the first-to-one line is a horizontal coupling capacitor Ch and a vertical capacitor-to-parallel. _ It can be seen that the input phase between the adjacent lines and the adjacent lines, _ _ _ ah and the coffee capacitor (7) in parallel), the peak ship is symmetrical. Thus, the electrical characteristics determined by the horizontal light-combining capacitor ch and the vertical light-combining capacitor 〜 can be substantially the same in the —--(4), the second-line 、, the second trace 50, and the fourth trace 60. It can be seen from the above derivation that the total combined capacitance between each trace is a horizontal light-combined capacitor (3) and is connected to the power W, and the value of each class is (10). Please refer to "FIG. 3A", which shows a first schematic diagram of a second embodiment of the present invention. In this embodiment, each of the traces also includes two segments. The difference from the "figure map" is that the second implementation, the second (4) segment (41) and the fourth position (101343623) are located at the second location point 22. Similarly, the first section of the thin trace 6G and the location of the second section 62 are identical, and both are located at the fourth location. Among the traces, only the first trace 30 and the third trace 5〇 of the first section and the second section are located at the location point. It can be seen from the figure that 'this wiring design side makes each trace _ _Combined capacitors are horizontally combined capacitors Ch plus vertical homogenized capacitors Cv' to achieve the _ total_combined capacitance of each trace.
同理，可讓第一走線30的第一區段31與第二區段32，以及第三走線 50的第-區段51與第二區段52分別配置的位置點皆一致，分別位於第一 位置點20及第三位置點24。相對的，第二走線4〇與第四走線⑹之第一區 段分別設置於第二位置，點22及第四位置點26,於第二區段時兩者互換設置 的位置點’使得第二走線4〇與第四走線6〇的第二區段分別設置於第四位 置點26與第二位置點22，如「第3B圊」所示。Similarly, the first segment 31 and the second segment 32 of the first trace 30, and the first segment 51 and the second segment 52 of the third trace 50 are respectively disposed at the same position, respectively Located at the first location point 20 and the third location point 24. In contrast, the first segments of the second trace 4〇 and the fourth trace (6) are respectively disposed at the second position, the point 22 and the fourth position point 26, and the position points of the two segments are interchangeably set in the second segment. The second sections of the second trace 4〇 and the fourth trace 6〇 are respectively disposed at the fourth location point 26 and the second location point 22, as shown in “3B圊”.
-較佳實酬’請麵「第4A圖」為本發明第三實關之示意圓。第 二實施例中’第-走線30包含第-區段31〜第四區段34 ;第二走線4〇包 含第-區段41〜第四區段44 ;第三走線5〇包含第一區段51〜第四區段54 ; 第四走線60包含第一區段61〜第四區段64。第一走線3〇〜第四走線6〇之第 -區段分別設置於第-位置點2〇〜第四位置點26。接下來，將各走線的第 二區段旋轉90度；再將各走線的第三區段以同一方向再旋轉9〇度；最後 將各走線的第四區段以同一方向再旋轉9〇度。經由上述之配置，可讓各走 線間的總耦合電容皆為：第一水平耦合電gchl並聯第二水平耦合電容Ch2 並聯第一垂直耦合電容〇1並聯第二垂直耦合電容Cv2。所以，各走線間 的總耦合電容互相匹配，均為Chl+Ch2+Cvl+Cv2。 1343623 請參照「第4B圖」’為對應「第μ圖」之俯視圖。由該俯視圖可清楚 看出各走_第-區段〜第四區段於第—佈弱與第二佈局層的配置方 式’同時也可清楚看出各走線的第一區段〜第四區段皆為互相連接。此外各 走線的第一區段之長度〜第四區段之長度可以相同。 上述所介紹的第-實施例〜第三實施例，其走線佈局的方式可稱之為幾 何對稱。所謂的幾何對稱就是指不論從哪—條走線看人的幾何形狀，皆為 對稱而-勝藉域何對稱可讓各相位之_電容能彼此互相匹 配。如此，可翻消除電容影響與延遲_影響之目的。 〜請參照「第5圖」為本發明第四實施例之示意圖。第四實施例與上述 實施例之差在於’本實施_由碰祕之__，使各走線間的 總耦合電容互相匹配。 第四實施_樣咖條植為_·,但並“四條祕為限。第 —走線30設置於第—佈局層1()，用以傳輸第_信㈣二走線明設置於- Better paid" Please contact "4A" as the schematic circle of the third real customs of the present invention. In the second embodiment, the 'th-line 30 includes the first-segment 31 to the fourth-segment 34; the second trace 4 〇 includes the first-segment 41 to the fourth-segment 44; the third trace 5 〇 includes The first segment 51 to the fourth segment 54; the fourth trace 60 includes the first segment 61 to the fourth segment 64. The first line from the first line 3 〇 to the fourth line 6 - is disposed at the first position point 2 〇 to the fourth position point 26, respectively. Next, rotate the second section of each trace by 90 degrees; then rotate the third section of each trace by 9 degrees in the same direction; finally, rotate the fourth section of each trace in the same direction. 9 degrees. Through the above configuration, the total coupling capacitance between the wires can be made as follows: the first horizontal coupling electric gchl is connected in parallel with the second horizontal coupling capacitance Ch2, and the first vertical coupling capacitance 〇1 is connected in parallel with the second vertical coupling capacitance Cv2. Therefore, the total coupling capacitance between the traces matches each other, and is Chl+Ch2+Cvl+Cv2. 1343623 Please refer to "4B Figure" as a top view corresponding to "Fig. It can be clearly seen from the top view that the respective sections of the _th-section to the fourth section are arranged in the first-week and the second layout layer, and the first section to the fourth section of each trace are also clearly visible. The sections are all connected to each other. Further, the length of the first section of each of the traces to the length of the fourth section may be the same. In the above-described first to third embodiments, the manner in which the traces are laid out can be referred to as geometric symmetry. The so-called geometric symmetry means that no matter which line - the human geometry is seen from the line, it is symmetrical and the symmetry of the domain can match the capacitances of the phases. In this way, the effect of the capacitor and the delay_effect can be eliminated. - Please refer to "figure 5" for a schematic view of a fourth embodiment of the present invention. The difference between the fourth embodiment and the above embodiment lies in the fact that the present embodiment is matched by the __, which makes the total coupling capacitance between the lines match each other. The fourth implementation _ sample coffee is planted as _·, but "four secrets are limited. The first - the trace 30 is set at the first - layout layer 1 (), used to transmit the first letter (four) two traces set in
第二佈局層12，__二信號H «與第-域之相位差為 9〇度。第三走線5〇設置於第二綱12，用哺鮮三錢，而第三信 被與第二域之她差為9Q度。第四祕6()設第—佈弱I用以 傳輸第四賴，.四信_三《之她絲9〇度。其巾，各走線所 傳輸的信號可以為水平同步信號。 _汉一；第—佈局層H)的與第二佈局層12相_二條走線(如圖中所 不’第-走線30與第四走⑽，⑽：走線4g與㈣㈣)之間呈有 水伟合電容Ch。另―方面，設置於苐_佈觸iq與第二佈弱U之不 12 1343623 同層而相鄰的二條走線(如圖中所示，第一走線30與第二走線4〇，以及第 四走線60與第二走線50)之間具有垂直耗合電容Cv。由於走線之間的搞合 電容，其電容值與兩走線間的距離成反比。因此，利用此特性，調整各走 線之間的距離，使各走線之間的總耦合電容(不論是水平耦合電容ch或垂 直耦合電容Cv)皆互相匹配，即，水平耦合電容ch實質上等於垂直耦合電 容Cv。在此，該實施例其走線佈局的方式可稱之為電性對稱。所謂的電性 對稱就疋指不論從哪一條走線看入，其電性特性皆實質上一致。藉由電性 對稱’同樣可讓各相位之間的總耦合電容能彼此互相匹配。如此，可達到 消除電容影響與延遲時間影響之目的。 雖然本發明的技術内容已經以較佳實施例揭露如上’然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神所作些許之更動與 乃飾查應涵蓋於本發明的範疇内，因此本發明之保護範圍當視後附之申 請專利範騎衫者為準。 【圖式簡單說明】 第1八圖：習知技術之第一種多相位高頻電路佈局示意圖。 第1B圖：習知技術之第二種多相位高頻電路佈局示意圖。 第2A圖：原理解說圖(一）。 第2B圖：原理解說圖(二）。 第2C圖：本發明第一實施例之示意圖（一）。 第2D圖：本發明第一實施例之示意圖(二）。 第2E圖：本發明第一實施例之俯視圖。 13 1343623 第2E圖：本發明第一實施例之俯視圖。 第3A圖：本發明第二實施例之第一示意圖。 . 第3B圖：本發明第二實施例之第二示意圖。 . 第4A圖：本發明第三實施例之示意圖。 • 第4B圖：本發明第三實施例之俯視圖。 ’ 第5圖：本發明第四實施例之示意圖。 ' 【主要元件符號說明】 Φ〇~Φ3 ·相位 td〇〜td3 :延遲時間 Ch :水平耦合電容 Chi :第一水平耦合電容 Ch2 :第二水平耦合電容 Cv :垂直耦合電容 Cvl :第一垂直耦合電容 ® Cv2 :第二垂直搞合電容 a、b、c :走線 • Cf、C :耦合電容The second layout layer 12, the __ two signal H « and the first domain have a phase difference of 9 degrees. The third line 5〇 is set in the second level 12, and the third letter is used to feed the money, and the third letter is 9Q degrees from the second field. The fourth secret 6 () set the first - cloth weak I used to transmit the fourth Lai, four letters _ three "the her silk 9 〇 degrees. The towel, the signal transmitted by each trace can be a horizontal sync signal. _ Han Yi; the first layout layer H) and the second layout layer 12 phase _ two traces (not shown in the figure - the first - the line 30 and the fourth walk (10), (10): the line 4g and (four) (four)) There is a water condenser capacitor Ch. On the other hand, the two traces disposed adjacent to the same layer and the second trace of the second cloth weak i is not 12 1343623 (as shown in the figure, the first trace 30 and the second trace 4〇, And a vertical consuming capacitance Cv between the fourth trace 60 and the second trace 50). Due to the capacitance between the traces, the capacitance is inversely proportional to the distance between the two traces. Therefore, by using this characteristic, the distance between the traces is adjusted so that the total coupling capacitance (whether the horizontal coupling capacitor ch or the vertical coupling capacitor Cv) between the traces matches each other, that is, the horizontal coupling capacitor ch is substantially Equal to the vertical coupling capacitor Cv. Here, the manner in which the trace layout is arranged in this embodiment can be referred to as electrical symmetry. The so-called electrical symmetry means that the electrical characteristics are substantially the same regardless of which trace is taken. The electrical coupling symmetry 'also allows the total coupling capacitance between the phases to match each other. In this way, the effect of eliminating the effects of capacitance and delay time can be achieved. Although the technical content of the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art, in light of the spirit and scope of the present invention, should be included in the present invention. Therefore, the scope of protection of the present invention is subject to the patent application vest. [Simple description of the figure] Figure 18: Schematic diagram of the first multi-phase high-frequency circuit layout of the prior art. Figure 1B: Schematic diagram of a second multi-phase high frequency circuit layout of the prior art. Figure 2A: The original understanding of the diagram (a). Figure 2B: The original understanding of Figure (2). 2C is a schematic view (1) of the first embodiment of the present invention. 2D is a schematic view (2) of the first embodiment of the present invention. Figure 2E is a plan view of the first embodiment of the present invention. 13 1343623 Figure 2E: Top view of the first embodiment of the invention. Figure 3A is a first schematic view of a second embodiment of the present invention. Figure 3B is a second schematic view of a second embodiment of the present invention. Figure 4A is a schematic view of a third embodiment of the present invention. • Fig. 4B is a plan view of a third embodiment of the present invention. Fig. 5 is a schematic view showing a fourth embodiment of the present invention. ' [Main component symbol description] Φ〇~Φ3 · Phase td〇~td3: Delay time Ch: Horizontal coupling capacitance Chi: First horizontal coupling capacitance Ch2: Second horizontal coupling capacitance Cv: Vertical coupling capacitance Cvl: First vertical coupling Capacitor® Cv2: second vertical fit capacitor a, b, c: trace • Cf, C: coupling capacitor
Vx :電壓信號 w 10 :第一佈局層 - 12:第二佈局層 20 :第一位置點 14 1343623 24 :第三位置點 26 :第四位置點 30 :第一走線 31 :第一走線之第一區段 32 :第一走線之第二區段 33 :第一走線之第三區段 34 :第一走線之第四區段 40 :第二走線 41 :第二走線之第一區段 42 :第二走線之第二區段 43 :第二走線之第三區段 44:第二走線之第四區段 50 :第三走線 51 :第三走線之第一區段 52 :第三走線之第二區段 53 :第三走線之第三區段 54 :第三走線之第四區段 60 :第四走線 61 :第四走線之第一區段 62 :第四走線之第二區段 63 :第四走線之第三區段 15 1343623 64 :第四走線之第四區段Vx: voltage signal w 10 : first layout layer - 12: second layout layer 20: first position point 14 1343623 24: third position point 26: fourth position point 30: first trace 31: first trace The first section 32: the second section 33 of the first trace: the third section 34 of the first trace: the fourth section 40 of the first trace: the second trace 41: the second trace The first section 42: the second section of the second trace 43: the third section of the second trace 44: the fourth section of the second trace 50: the third trace 51: the third trace The first section 52: the second section of the third trace 53: the third section of the third trace 54: the fourth section of the third trace 60: the fourth trace 61: the fourth trace The first section 62: the second section of the fourth trace 63: the third section of the fourth trace 15 1343623 64: the fourth section of the fourth trace