TWI339438B - Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell - Google Patents
Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell Download PDFInfo
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1339438 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種半導體記憶裝置,且更特定言之係關 於一種具有一堆疊記憶體單元之半導體記憶裝置。 【先前技術】 相變隨機存取記憶體(PRAM)由諸如硫族化物合金之相 變材料形成,當對其進行加熱並冷卻時,其變成兩個相中 之第一相,且當再次對其進行加熱並冷卻時,其變成第二 相。此處,兩個相為晶相及非晶相。美國專利第6,487,1 1 3 及6,4 80,438號中揭示PRAM。當PRAM變成結晶時,其具 有低電阻值,且當其為非晶系時具有高電阻值。根據 PRAM之電阻值可判定邏輯值為0或1。PRAM之晶相對應 於設定狀態或具有邏輯值0,且其非晶相對應於重設狀態 或具有邏輯值1。 為了使PRAM之相變為非晶相,將PRAM加熱至高於 PRAM熔融溫度之溫度並快速冷卻。為了使PRAM之相變 為晶相,將PRAM加熱至低於熔融溫度之溫度歷時一預定 時間。 PRAM之關鍵之處在於,其由相變材料(諸如硫族化物) 形成。通常,該相變材料為由鍺(Ge)、銻(Sb)及碲(Te)合 成之GST合金。當加熱或冷卻GST合金時,其狀態在非晶 態(重設狀態)與晶態(設定狀態)之間快速變化,換言之, 其邏輯值在1與0之間切換。因此,該GST合金作為用於 PRAM記憶裝置之材料係有用的。 110756.doc f 了向PRAM之記憶體單元寫人資#,將硫族化物加熱 至專於或大於其溶融溫度之溫度並快速冷卻以使硫族化物 處於非晶態。另外,以小於熔融溫度之溫度加熱硫族化 物,保持該溫度,並冷卻以使硫族化物變為晶態。 圖1為美國專利第5,883,827號中所揭示之一習知相變記 肢單元1 0之電路圖。該記憶體單元1 〇包括一相變可變電 I5裝置R1 ’其一第一端子連接至_位元線且其一第二 端子連接至-選擇電晶體心_沒極;及該選擇電晶體 N1,其閘極連接至一字線WL且其源極連接至一參考電壓 VSS。 圖2為一包含等同於圖丨之該相變記憶體1〇之複數個相變 记憶體單元10之相變記憶體陣列1〇〇的電路圖。該複數個 相變記憶體單元10連接至一位元線肛,該位元線肌連接 至一感應放大器(未圖示)。 近來,PRAM作為下-代記憶體吸引了相當大的關注。 然而,需要改良PRAM之整合性以使得PRAM可與諸如動 態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM) 及快閃記憶體之其他類型記憶體競爭。 如上文所述,藉由使用焦耳熱量加熱PRAM將資料寫入 至PRAM ^然而,在減小習知記憶體單元之控制電晶體之 尺寸方面存在限制,其提供產生焦耳熱量所需之電流,藉 此防止PRAM之整合密度增加。 因此,對於可增加PRAM之整合密度的單元結構及使用 該改良之單元結構之半導體記憶裝置之配置改良存在不斷 110756.doc 1339438 增長的需求。 【發明内容】 本發明提供一種具有改良之整合密度之相變記憶體單 元0 ,本發明亦提供一種具有此一相變隨機存取記憶體 • (PRAM)單元之半導體記憶裝置。 根據本發明之一態樣,提供一種相變記憶體單元,其包 φ 含形成於不同層上之複數個控制電晶體及一由一相變材料 形成之可變電阻裝置。 在一實施例中,控制電晶體之數目為二。 在另一實施例中’該等控制電晶體包括:—第一控制電 晶體,其為一塊狀電晶體;及一第二控制電晶體,其形成 於6玄第一控制電晶體上且為一薄層電晶體。 在另一實施例中,該等控制電晶體進一步包括一形成於 °亥第一控制電晶體上之第三控制電晶體。該等控制電晶體 籲可為M〇S電晶體,並形成-二極體。該等控制電晶體可視 .@况包含雙極電晶體。該第二控制電晶體可形成於該第一 控制電晶體上。該可變電阻裝置可包含鍺(Ge)、錄(叫及 蹄(Te) 〇 ^料發明之另—態樣,提供_種半導體記憶裝置,其 王局位元線,複數個局部位元線,其分別經由對 應於該等局部位元線之局部位元線選擇電路而連接至該全 ::广:或與邊全局位元線斷開連接;及複數個相變記憶 ,·且,當其分別連接至該等局部位元線時其健存資 )I0756.doc 料。該等相變記憶體單元組之每一者之該等相變記憶體單 7L之每一者包含形成於不同層上之複數個控制電晶體,及 一由一相變材料形成之可變電阻裝置。 在一實施例中’該等局部位元線選擇電路為電晶體,其 回應於一局部位元線選擇訊號而將該等局部位元線連接至 4王局位元線或將該等局部位元線與該全局位元線斷開連 接°所有該等控制電晶體之閘極連接至一相應字線。 在另一實施例中,該半導體記憶裝置視情況進一步包括 一周邊電路。該周邊電路可包含一反相器電路,該反相器 電路包括一形成於一第一層上之塊狀電晶體,及一形成於 —第二層上之薄層電晶體。該塊狀電晶體可包含一 NM〇s 電晶體’且該薄層電晶體可包含一 PMOS電晶體。 在另一實施例中,該半導體記憶裝置進一步包括一連接 至該全局位元線之感應放大器。 根據本發明之又一態樣,提供一種相變記憶體單元,其 包括:複數個控制電晶體’其閘極連接至一字線且其形成 於不同層上;及一可變電阻裝置,每一控制電晶體之—第 知子及一第二端子之一者連接至該可變電阻裝置,且另 一者連接至一接地電壓源。 根據本發明之又一態樣,提供一種相變記憶體單元,其 包括;一第一控制電晶體’其形成於一第一基板上且具有 一源極、閘極及汲極;一第二基板,其形成於該第一控制 電晶體上;一第二控制電晶體’其形成於該第二基板上且 具有一源極、閘極及汲極;及一可變電阻裝置,其連接至 110756.doc 1339438 該第二控制電晶體之該源極及該汲極之一者且由一相變材 料形成。 在一實施例中,該第一控制電晶體之該源極電連接至該 第二控制電晶體之該源極,該第一控制電晶體之該汲極電 連接至該第二控制電晶體之該汲極’且該第一控制電晶體 之該閘極電連接至該第二控制電晶體之該閉極。 在另一實施例中,該第一及該第二控制電晶體具有一平 面電晶體結構、一鰭式場效電晶體結構或一多通道場效電 晶體結構。 在另一實施例中’該第二基板形成為平行於該第一基板 並與該第一基板部分地重疊。將該可變電阻裂置連接至該 第一控制電晶體之該源極及該沒極之一者的一第一接觸插 塞,以及將一外部電源連接至該第一控制電晶體之該源極 及該汲極之一者的一第二接觸插塞由一導電層形成。 在另一實施例中’該等接觸插塞連接至該第二控制電晶 體之該源極及該沒極。 根據本發明之又一實施例,提供—種製造一相變記憶體 單元之方法’ έ亥方法包括:在一第一基板上形成一具有一 源極、閘極及汲極之第一控制電晶體;在該第一控制電晶 體上形成一第二基板;在該第二基板上形成一具有一源 極、閘極及汲極之第二控制電晶體;及將一可變電阻裝置 連接至該第二控制電晶體之該源極及該汲極之一者,該可 變電阻裝置由一相變材料形成。 在一實施例中’該方法進一步包括:形成一第一接觸插 110756.doc -10- 1339438 塞,其將該可變電阻裝置連接至該第―控制電晶體之該源 極及該汲極之-者;及形成—第二接_塞 電源連接至該第-控制電晶體之該源極及該汲極之一者。 【實施方式】 下文將參看附圖詳細描述本發明之例示性實施例。本揭 示案中,相同參考標號用來表示相同或等同元件。BRIEF DESCRIPTION OF THE DRAWINGS 1. Field of the Invention This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a stacked memory cell. [Prior Art] Phase change random access memory (PRAM) is formed of a phase change material such as a chalcogenide alloy, which when heated and cooled, becomes the first of the two phases, and when again When it is heated and cooled, it becomes the second phase. Here, the two phases are a crystalline phase and an amorphous phase. PRAM is disclosed in U.S. Patent Nos. 6,487,1, 3, and 6, 4,80,438. When the PRAM becomes crystalline, it has a low resistance value and has a high resistance value when it is amorphous. The logic value can be determined to be 0 or 1 based on the resistance value of the PRAM. The crystal of the PRAM corresponds to a set state or has a logic value of 0, and its amorphous corresponds to a reset state or has a logic value of one. In order to change the phase of the PRAM to an amorphous phase, the PRAM is heated to a temperature higher than the melting temperature of the PRAM and rapidly cooled. In order to change the phase of the PRAM to a crystalline phase, the PRAM is heated to a temperature below the melting temperature for a predetermined period of time. The key to PRAM is that it is formed from a phase change material such as a chalcogenide. Typically, the phase change material is a GST alloy composed of germanium (Ge), antimony (Sb), and tellurium (Te). When the GST alloy is heated or cooled, its state rapidly changes between an amorphous state (reset state) and a crystalline state (set state), in other words, its logic value is switched between 1 and 0. Therefore, the GST alloy is useful as a material for a PRAM memory device. 110756.doc f Writes the memory to the memory cell of the PRAM, heating the chalcogenide to a temperature specific to or greater than its melting temperature and rapidly cooling to make the chalcogenide amorphous. Further, the chalcogenide is heated at a temperature lower than the melting temperature, maintained at this temperature, and cooled to bring the chalcogenide into a crystalline state. Figure 1 is a circuit diagram of one of the conventional phase change recording limb units 10 disclosed in U.S. Patent No. 5,883,827. The memory unit 1 〇 includes a phase change variable electrical I5 device R1 ′ having a first terminal connected to the _ bit line and a second terminal connected to the -selecting the transistor core _ no pole; and the selection transistor N1 has its gate connected to a word line WL and its source connected to a reference voltage VSS. Figure 2 is a circuit diagram of a phase change memory array 1A comprising a plurality of phase change memory cells 10 equivalent to the phase change memory of Figure 。. The plurality of phase change memory cells 10 are connected to a bit line anal, which is connected to a sense amplifier (not shown). Recently, PRAM has attracted considerable attention as a lower-generation memory. However, there is a need to improve the integration of PRAMs to enable PRAMs to compete with other types of memory such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory. As described above, data is written to the PRAM by heating the PRAM using Joule heat. However, there is a limitation in reducing the size of the control transistor of the conventional memory cell, which provides the current required to generate Joule heat. This prevents an increase in the integration density of the PRAM. Therefore, there is a growing demand for a cell structure that can increase the integrated density of PRAM and a configuration of a semiconductor memory device using the improved cell structure. SUMMARY OF THE INVENTION The present invention provides a phase change memory cell 0 having an improved integrated density. The present invention also provides a semiconductor memory device having such a phase change random access memory (PRAM) cell. According to an aspect of the present invention, there is provided a phase change memory cell comprising: φ comprising a plurality of control transistors formed on different layers and a variable resistance device formed of a phase change material. In one embodiment, the number of control transistors is two. In another embodiment, the control transistors include: a first control transistor, which is a block transistor; and a second control transistor formed on the 6-first control transistor and A thin layer of transistor. In another embodiment, the control transistors further include a third control transistor formed on the first control transistor. The control transistors can be M〇S transistors and form a diode. These control transistors are visible. The condition includes a bipolar transistor. The second control transistor can be formed on the first control transistor. The variable resistance device may include 锗 (Ge), recording (called and hoof (Te) 〇 发明 发明 发明 发明 发明 发明 , , , , , , , , , , 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Connected to the entire via: a local bit line selection circuit corresponding to the local bit lines, respectively:: or disconnected from the edge global bit line; and a plurality of phase change memories, and It is connected to the local bit line when it is stored in the I0756.doc material. Each of the phase change memory cells 7L of each of the phase change memory cell groups includes a plurality of control transistors formed on different layers, and a variable resistor formed of a phase change material Device. In one embodiment, the local bit line selection circuits are transistors that are coupled to the local bit lines or to the local bits in response to a local bit line selection signal. The meta-line is disconnected from the global bit line. The gates of all of the control transistors are connected to a corresponding word line. In another embodiment, the semiconductor memory device further includes a peripheral circuit as appropriate. The peripheral circuit can include an inverter circuit including a bulk transistor formed on a first layer and a thin layer transistor formed on the second layer. The bulk transistor may comprise an NM〇s transistor' and the thin layer transistor may comprise a PMOS transistor. In another embodiment, the semiconductor memory device further includes a sense amplifier coupled to the global bit line. According to still another aspect of the present invention, a phase change memory cell is provided, comprising: a plurality of control transistors having a gate connected to a word line and formed on different layers; and a variable resistance device each One of the control transistor and one of the second terminal and the second terminal is connected to the variable resistance device, and the other is connected to a ground voltage source. According to still another aspect of the present invention, a phase change memory unit includes: a first control transistor formed on a first substrate and having a source, a gate and a drain; and a second a substrate formed on the first control transistor; a second control transistor formed on the second substrate and having a source, a gate and a drain; and a variable resistance device connected to 110756.doc 1339438 The source of the second control transistor and one of the drains are formed of a phase change material. In one embodiment, the source of the first control transistor is electrically connected to the source of the second control transistor, and the drain of the first control transistor is electrically connected to the second control transistor. The drain is electrically connected to the gate of the second control transistor. In another embodiment, the first and second control transistors have a planar transistor structure, a fin field effect transistor structure or a multi-channel field effect transistor structure. In another embodiment, the second substrate is formed to be parallel to and partially overlap the first substrate. Connecting the variable resistor to a first contact plug of the source of the first control transistor and the one of the poles, and connecting an external power source to the source of the first control transistor A second contact plug of the pole and one of the drains is formed by a conductive layer. In another embodiment, the contact plugs are coupled to the source and the gate of the second control transistor. According to still another embodiment of the present invention, a method for fabricating a phase change memory cell is provided. The method includes: forming a first control circuit having a source, a gate, and a drain on a first substrate. Forming a second substrate on the first control transistor; forming a second control transistor having a source, a gate and a drain on the second substrate; and connecting a variable resistance device to The source of the second control transistor and one of the drains, the variable resistance device is formed of a phase change material. In one embodiment, the method further includes: forming a first contact plug 110756.doc -10- 1339438 plug, the variable resistance device being coupled to the source of the first control transistor and the drain And forming a second connection _ plug power source connected to the source of the first control transistor and one of the drains. [Embodiment] Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the present disclosure, the same reference numerals are used to refer to the same or equivalent elements.
現將參看圖3及圖4描述根據本發明之一實施例之半導體 圯憶裝置之单元結構。在此實施例中,該半導體記憶裝置 表不由相變材料形成之相變隨機存取記憶體(PRAM)。 ,…义思瓶早 -----。,口,》> rj尽工&罘一及 第二控制電晶體咖謂2,及一由一相變材料形成之可 變電阻裝置R3。 —該第一及該第二控制電晶體N 3 i及N 3 2之開極連接至一 子線WL。該第一及該第二控制電晶體N3 1及之每一者 之第一端子連接至一參考電壓,例如接地電壓Vss。 忒等個別第一及第二控制電晶體N3丨及N32之每一者之 一第二端子連接至該可變電阻裝置R3之一第一端子。咳可 變電阻裝置R3之-第二端子連接至一位元線扯〇 ^ 參看圖4,第一及第二控制電晶體N31及N32形成於不同 層上。在一實施例中,第_控制電晶體N3丨為塊狀電晶 體且第一控制電晶體N32為薄層電晶體。第一控制電晶 體之一閘電極65及第二控制電晶體N32之一閘電極67 連接至一予線(未圖示)。 第-控制電晶體N31之—源電極71B及第二控制電晶體 lW756.doc - 1339438 N32之一源電極69B經由一第一接觸插塞6IA而連接至接地 電壓Vss及一第一降落墊59A »第一控制電晶體N3】之一汲 電極71 A及第二控制電晶體N32之一汲電極69A經由一第二 接觸插塞61B而連接至一第二降落墊59B。 降洛塾59B經由一較低電極57而連接至一相變層μ。該 相變層55經由一電極53而連接至一局部位元線5丨。第二控 制電晶體N32為形成於一磊晶矽層(未圖示)上之薄層電晶 體。 在不同應用之不同實施例中’第一及第二控制電晶體 N31及N32可為MOS電晶體或雙極電晶體,且可形成一二 極體。 根據此實施例’控制電晶體N3 1及N32形成於不同層上 以增加半導體記憶裝置之整合密度。相變記憶體單元3 〇包 括控制電晶體N3 1及N32以增加流經可變電阻裝置R3之電 流量’該增加之電流量進而提供快速改變裝置之相所必需 的熱量。然而’包括多個控制電晶體N3 1及N32將增大相 變記憶體單元3 0之尺寸。為了解決此問題,多個電晶體 N31及N32形成於裝置之不同層上。 可向相變記憶體單元3 0添加一為薄層電晶體之第三控制 電晶體(未圖示)以進一步增加相變記憶體單元3〇之整合。 圖5為根據本發明之一實施例半導體記憶裝置(未圖示) 之相變記憶體陣列300之電路圖。該相變記憶體陣列300包 括一全局位元線GBL ;第一及第二局部位元線LBL1及 LBL2 ;及第一及第二相變記憶體單元組5〇及7〇(諸如圖3之 H0756.doc 12 1339438 相變記憶體單元30),當其正分別連接至局部位元線LBLI 及LBL2時,其儲存資料。 局部位元線LBL1及LBL2分別經由第一及第二局部位元 線選擇電路N3及N5而連接至全局位元線GBL,或與全局 位兀線GBL斷開連接。換言之,局部位元線選擇電路N3& N5可為電晶體,其允許局部位元線LBU&LBL2回應於局 4位元線選擇訊號LBS1及LBS2而連接至全局位元線 或與全局位元線GBL斷開連接。在圖5中,僅說明兩個局 部位元線LBL1及LBL2,但不限定局部位元線之數目^ 第一相k έ己憶體單元組50之複數個相變記憶體單元3〇之 母一者,及第二相變記憶體單&組7〇之複數個相冑記憶體 單元40之每一者包括形成於不同層上之複數個控制電晶體 及一由相變材料形成之可變電阻裝置。在圖5中,相變記 隐體單兀組50及70之每一者之相變記憶體單元的數目為 七,然而,相變記憶體單元之數目並不限於此。 多看圖5帛相變舌己憶體單元組5 〇之相變記憶體單元 3〇連接至第-局部位元紅如,且第二相變記憶體單元 組70之相變記憶體單元4〇連接至第二局部位元線胤卜 第一局部位元線選擇電路N3回應於第一局部位元線選擇 訊號LBS1而將第-局部位元線咖連接至全局位元線 咖。第二局部位元線選擇電路奶回應於第二局部位元線 選擇訊號LBS2而將第-片卹仏_ a τ ^ 矛一·局。卩位το線LBL2連接至全局位元 線 G B L 〇 在讀取或寫入操作期間,第—及第二局部位元線選擇訊 110756.doc 唬lbs 1及LBS2允許回應於一位址訊號來選擇個別第一及 第二相變記憶體單元組50及70之一者,其用於讀取或寫入 資料。 —感應放大器(未圖示)連接至全局位元線GBL以放大自 選定之第一或第二相變記憶體單元組5〇或7〇讀取之資料。 如上文所述’在根據本發明之一實施例之半導體記憶裝 置中,藉由在不同層上形成複數個控制電晶體來製造每一 记憶體單元。因此,在減小記憶體單元之每一者的尺寸同 時將大篁程式電流(pr〇gramming current)供應至相變可變 電阻裝置係可能的。 同樣,使用全局位元線及局部位元線來實現根據本發明 之半導體記憶裝置之相變記憶體單元陣列之階層式位元線 結構係可能的’藉此能夠製造緊密記憶體陣列。 根據本發明之半導體記憶裝置可進—步包括—周邊電路 (未圖不)°《周邊電路可為—反相器電路,其包括-塊狀 電晶體及-形成於該塊狀電晶體上之薄層電晶體。塊狀電 晶體可為NMOS雷„曰駚η » μ „ 电曰a體且该薄層電晶體可為pm〇S電晶 體。 §將包括形成於χ , 、不同層上之該NM〇s電晶體及該pM〇s 電晶體之反相器電路用你由A + 用作周邊電路時,半導體記憶裝置之 整合密度進一步:Μό、 (k, 〇〇 a 。舉例而言’藉由向圖3之相變記憶 體單元3 0之結構添力作 作為周邊電路之電晶體來增加半導體 記憶裝置之整合係可能的。 根據本發明,構成4 成相交记憶體皁元之控制電晶體形成於 110756.doc 14 1339438 不同層上,且該等控制電晶體之數目可多於一個。已參看 圖3描述控制電晶體,且因此將省略詳細描述。 在一應用中’將根據本發明之半導體記憶裝置連同一邏 輯晶片一起安裝於一系統LSI邏輯晶片中。 圖6A為根據本發明之一實施例一相變記憶體單元600之 橫截面圖。圖6B為圖6A之相變記憶體單元600之—第—控 制電晶體N3】之平面圖。圖6C為圖6 A之相變記憶體單元 600之側視圖。 參看圖6A,相變記憶體單元600包括:複數個第一控制 電晶體N3I,其每一者形成於一第一基板612上且具有一源 極S〗、一閘極G11及一汲極D1 ; 一形成於該等第—控制電 Bb體N3 1上之第二基板614 ;複數個第二控制電晶體N32, 其每一者形成於該第二基板614上且具有一源極52、一閘 極G2 1及一汲極D2 ;及一可變電阻裝置6丨6,其連接至該 第二控制電晶體N32之一者之該源極S2、該閘極G21及該 沒極D2之一者且由一相變材料形成。 為方便起見,圖6 A說明第一及第二控制電晶體N3 }及 N32之每一者中之兩個分別形成於第一及第二基板612及 614上。然而,根據本發明,待形成於第一基板612上之第 一控制電晶體N31之數目及待形成於第二基板614上之第二 控制電晶體N32之數目均不存在限制。 圖6A之相變記憶體單元6〇〇對應於圖3及圖4中所說明之 相變記憶體單元30在相變記憶體單元3〇之製造期間的橫截 面0 )I0756.doc -15- 1339438 第一控制電晶體N3 1之源極S 1電連接至第二控制電晶體 N32之源極S2,且第一控制電晶體N3 1之汲極D1電連接至 第·一控制電晶體N32之沒極D 2。 經由接觸插塞CP11及CP22來提供此等電連接。特定言 之’第一控制電晶體N 3 1之源極S 1連接至接觸插塞c P11, 接觸插塞CP11連接至第二基板614。又,第二控制電晶體 N32之源極S2連接至接觸插塞CP21。 類似地’第一控制電晶體N 3 1之汲極D1連接至接觸插塞 CP12’接觸插塞CP12連接至第二基板614。又,第二控制 電晶體N32之汲極D2連接至接觸插塞CP22。 接觸插塞CP11、CP21、CP12及CP22為允許電傳導之導 電層。 第一控制電晶體N3 1之閘極G11電連接至第二控制電晶 體N32之閘極G21。經由圖6C之一接觸插塞CP(圖όΑ中未圖 示)來執行此電連接。在圖6Α中,11表示一絕緣材料,且 12表示一介電層。 圖6Α之第一及第二控制電晶體N3i及Ν32具有一平面電 晶體結構。平面電晶體為閘極形成於基板上之電晶體。圖 6Β為第一控制電晶體Ν3 1之平面圖’第一控制電晶體 為平面電晶體。參看圓6B,閘極G11及G12形成於第—基 板612上。 圖6C為圖6A之相變記憶體單元6〇〇之側視圖。參看圖 6C在第一及第二基板612及614上水平地形成第一控制電 晶體N31之閘極Gu及第二控制電晶體N32之閘極〇2丨,其 I10756.doc •16- 1339438 延伸相變S己憶體單元600之完全寬度。閘極G11與G21經由 〜 接觸插塞CP而電連接。 ' 另外,一活性區域ACTIVE (即,源極及汲極區域)形成 於第一及第二基板612及614之每一者中。 圖7A為根據本發明之另一實施例一相變記憶體單元7〇〇 之k截面圖。該相變記憶體單元7〇〇之構造,除了複數個 第一及第二控制電晶體N3 1及N32具有一鰭式場效電晶體 φ (FlnFET)結構外,其餘與圖6A之相變記憶體單元600之構 造相同。 換言之,第一控制電晶體N3I形成於一第一基板7】2上, 且一第二基板714形成於第一控制電晶體N31上。第二控制 電晶體N32形成於第二基板714上。 一可變電阻裝置716分別經由接觸插塞CP1丨及CP22而連 接至第—及第二控制電晶體N3 1及N32之汲極。又,第一 及第二控制電晶體N3〗與N32之源極經由接觸插塞及 • CP22電連接。A cell structure of a semiconductor memory device according to an embodiment of the present invention will now be described with reference to Figs. In this embodiment, the semiconductor memory device represents a phase change random access memory (PRAM) formed of a phase change material. , ... Yisi bottle early -----. , mouth, "> rj" and the second control transistor 2, and a variable resistance device R3 formed of a phase change material. The open ends of the first and second control transistors N 3 i and N 3 2 are connected to a sub-line WL. The first terminals of the first and second control transistors N3 1 and each of the terminals are connected to a reference voltage, such as a ground voltage Vss. A second terminal of each of the individual first and second control transistors N3 and N32 is coupled to a first terminal of the variable resistance device R3. The second terminal of the cough variable resistance device R3 is connected to a one-dimensional wire. Referring to Fig. 4, the first and second control transistors N31 and N32 are formed on different layers. In one embodiment, the first control transistor N3 turns into a bulk transistor and the first control transistor N32 is a thin layer transistor. One of the gate electrode 65 of the first control transistor and the gate electrode 67 of the second control transistor N32 are connected to a predetermined line (not shown). The source electrode 71B of the first control transistor N31 and the second control transistor lW756.doc - 1339438 N32 one source electrode 69B is connected to the ground voltage Vss and a first landing pad 59A via a first contact plug 6IA. One of the first control transistor N3 and one of the second control transistor N32 is connected to a second landing pad 59B via a second contact plug 61B. The falling sputum 59B is connected to a phase change layer μ via a lower electrode 57. The phase change layer 55 is connected to a local bit line 5A via an electrode 53. The second control transistor N32 is a thin layer of transistor formed on an epitaxial layer (not shown). In different embodiments of different applications, the first and second control transistors N31 and N32 may be MOS transistors or bipolar transistors and may form a diode. According to this embodiment, the control transistors N31 and N32 are formed on different layers to increase the integration density of the semiconductor memory device. The phase change memory unit 3 includes control transistors N3 1 and N32 to increase the current flowing through the variable resistance device R3. This increased amount of current provides the heat necessary to rapidly change the phase of the device. However, including a plurality of control transistors N3 1 and N32 will increase the size of the phase change memory cell 30. To solve this problem, a plurality of transistors N31 and N32 are formed on different layers of the device. A third control transistor (not shown), which is a thin layer transistor, can be added to the phase change memory cell 30 to further increase the integration of the phase change memory cell. 5 is a circuit diagram of a phase change memory array 300 of a semiconductor memory device (not shown) in accordance with an embodiment of the present invention. The phase change memory array 300 includes a global bit line GBL; first and second local bit lines LBL1 and LBL2; and first and second phase change memory cell groups 5 and 7 (such as FIG. H0756.doc 12 1339438 Phase change memory unit 30) stores data when it is connected to local bit lines LBLI and LBL2, respectively. The local bit lines LBL1 and LBL2 are connected to the global bit line GBL via the first and second local bit line selection circuits N3 and N5, respectively, or are disconnected from the global bit line GBL. In other words, the local bit line selection circuit N3 & N5 may be a transistor that allows the local bit line LBU&LBL2 to be connected to the global bit line or to the global bit line in response to the local 4-bit line select signals LBS1 and LBS2. GBL is disconnected. In FIG. 5, only two local bit lines LBL1 and LBL2 are illustrated, but the number of local bit lines is not limited. ^ The first phase k is the mother of a plurality of phase change memory cells 3 of the memory cell group 50. And each of the plurality of phase memory cells 40 of the second phase change memory single & group 7 includes a plurality of control transistors formed on different layers and a phase change material. Variable resistance device. In Fig. 5, the number of phase change memory cells of each of the phase change hidden cell groups 50 and 70 is seven, however, the number of phase change memory cells is not limited thereto. Looking at Figure 5, the phase change memory cell unit 5 is connected to the first-local bit red, and the phase change memory cell of the second phase-change memory cell group 70 is 〇Connecting to the second partial bit line 第一 The first partial bit line selecting circuit N3 connects the first partial bit line to the global bit line in response to the first partial bit line selection signal LBS1. The second partial bit line selection circuit milk responds to the second partial bit line selection signal LBS2 to cause the first sheet to 仏_ a τ ^.卩 το line LBL2 is connected to the global bit line GBL 第 During the read or write operation, the first and second partial bit line selection signals 110756.doc 唬 lbs 1 and LBS2 allow selection in response to a bit address signal One of the individual first and second phase change memory cell groups 50 and 70 for reading or writing data. - A sense amplifier (not shown) is connected to the global bit line GBL to amplify the data read from the selected first or second phase change memory cell group 5 or 7 . As described above, in a semiconductor memory device according to an embodiment of the present invention, each memory cell is fabricated by forming a plurality of control transistors on different layers. Therefore, it is possible to supply a pr〇 gramming current to the phase change varistor device while reducing the size of each of the memory cells. Similarly, the use of global bit lines and local bit lines to implement a hierarchical bit line structure of a phase change memory cell array of a semiconductor memory device in accordance with the present invention is capable of producing a compact memory array. The semiconductor memory device according to the present invention may further include a peripheral circuit (not shown). The peripheral circuit may be an inverter circuit including a bulk transistor and formed on the bulk transistor. Thin layer transistor. The bulk transistor can be an NMOS 曰駚 曰駚 » μ μ 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且§ The integrated circuit of the semiconductor memory device will be further included when the NM〇s transistor formed on the χ, and the different layers and the inverter circuit of the pM〇s transistor are used by A + as the peripheral circuit: Μό (k, 〇〇a. For example, it is possible to increase the integration of the semiconductor memory device by adding the structure of the phase change memory cell 30 of FIG. 3 as a transistor of the peripheral circuit. According to the present invention, The control transistor constituting 4 intersecting memory soap cells is formed on different layers of 110756.doc 14 1339438, and the number of such control transistors may be more than one. The control transistor has been described with reference to FIG. 3, and thus will be omitted DETAILED DESCRIPTION In one application, a semiconductor memory device in accordance with the present invention is mounted in a system LSI logic die along with a logic die. Figure 6A is a cross section of a phase change memory cell 600 in accordance with an embodiment of the present invention. Figure 6B is a plan view of the -> control transistor N3 of the phase change memory cell 600 of Figure 6A. Figure 6C is a side view of the phase change memory cell 600 of Figure 6A. Referring to Figure 6A, phase change memory Body order 600 includes: a plurality of first control transistors N3I, each of which is formed on a first substrate 612 and has a source S, a gate G11, and a drain D1; one formed in the first control a second substrate 614 on the electric Bb body N3 1 ; a plurality of second control transistors N32 each formed on the second substrate 614 and having a source 52, a gate G2 1 and a drain D2 And a variable resistance device 6丨6 connected to one of the source S2, the gate G21 and the gate D2 of one of the second control transistors N32 and formed of a phase change material. For convenience, FIG. 6A illustrates that two of each of the first and second control transistors N3} and N32 are formed on the first and second substrates 612 and 614, respectively. However, according to the present invention, There is no limitation on the number of first control transistors N31 formed on the first substrate 612 and the number of second control transistors N32 to be formed on the second substrate 614. The phase change memory unit 6 of Fig. 6A Corresponding to the cross-section of the phase change memory cell 30 illustrated in FIGS. 3 and 4 during the fabrication of the phase change memory cell 3〇0)I07 56.doc -15- 1339438 The source S 1 of the first control transistor N3 1 is electrically connected to the source S2 of the second control transistor N32, and the drain D1 of the first control transistor N3 1 is electrically connected to the A control pole D 2 of the transistor N32. These electrical connections are provided via contact plugs CP11 and CP22. Specifically, the source S 1 of the first control transistor N 3 1 is connected to the contact plug c P11 , and the contact plug CP 11 is connected to the second substrate 614. Further, the source S2 of the second control transistor N32 is connected to the contact plug CP21. Similarly, the drain D1 of the first control transistor N 3 1 is connected to the contact plug CP12'. The contact plug CP12 is connected to the second substrate 614. Further, the drain D2 of the second control transistor N32 is connected to the contact plug CP22. The contact plugs CP11, CP21, CP12 and CP22 are conductive layers that allow electrical conduction. The gate G11 of the first control transistor N31 is electrically connected to the gate G21 of the second control transistor N32. This electrical connection is performed via a contact plug CP (not shown in Fig. 6) of Fig. 6C. In Fig. 6A, 11 denotes an insulating material, and 12 denotes a dielectric layer. The first and second control transistors N3i and Ν32 of Fig. 6 have a planar crystal structure. A planar transistor is a transistor in which a gate is formed on a substrate. Figure 6 is a plan view of the first control transistor Ν 31. The first control transistor is a planar transistor. Referring to circle 6B, gates G11 and G12 are formed on the first substrate 612. Figure 6C is a side elevational view of the phase change memory cell 6A of Figure 6A. Referring to FIG. 6C, the gates Gu of the first control transistor N31 and the gates 第二2 of the second control transistor N32 are horizontally formed on the first and second substrates 612 and 614, and the I10756.doc • 16-1339438 extension The full width of the phase change S memory cell 600. The gates G11 and G21 are electrically connected via the ~ contact plug CP. In addition, an active region ACTIVE (i.e., source and drain regions) is formed in each of the first and second substrates 612 and 614. Figure 7A is a cross-sectional view of a phase change memory cell 7A according to another embodiment of the present invention. The structure of the phase change memory cell 7〇〇, except that the plurality of first and second control transistors N3 1 and N32 have a fin field effect transistor φ (FlnFET) structure, and the phase change memory of FIG. 6A Unit 600 is constructed identically. In other words, the first control transistor N3I is formed on a first substrate 7]2, and a second substrate 714 is formed on the first control transistor N31. The second control transistor N32 is formed on the second substrate 714. A variable resistance device 716 is connected to the drains of the first and second control transistors N3 1 and N32 via contact plugs CP1 and CP22, respectively. Further, the first and second control transistors N3 and N32 are electrically connected via a contact plug and a CP 22 .
FmFET具有一結構,其中沿著一通道之兩側形成閘電 極,且因此該等閘電極具有長通道長度,藉此抑制短通道 效應。 圖7B為圖7A之相變記憶體單元7〇〇之第一控制電晶體 N31之平面圖。圖7B說明第一基板712面積小於圖佔之第 一基板612,因為在本實施例中將FinFET用作第一控制電 晶體N3 I。 圖7C為圖7A之相變記憶體單元700之側視圖。與圖6C之 D0756.doc • J7· 1339438 側視圖中相比,第一及第二FinFET控制電晶體N3丨及N32 之閘極Gl 1及G22經形成以包圍活性區域ACTIVE,藉此伸 長該等閘極之通道CH。 或者,第一及第二控制電晶體N31及N32可具有一多通 道場效電晶體(McFET)結構。圖7D為根據本發明之另一實 施例一相變記憶體單元之側視圖。圖7D中說明該McFET。The FmFET has a structure in which gate electrodes are formed along both sides of a channel, and thus the gate electrodes have a long channel length, thereby suppressing the short channel effect. Figure 7B is a plan view of the first control transistor N31 of the phase change memory cell 7 of Figure 7A. Fig. 7B illustrates that the first substrate 712 has a smaller area than the first substrate 612, since the FinFET is used as the first control transistor N31 in this embodiment. Figure 7C is a side view of the phase change memory cell 700 of Figure 7A. The gates G1 1 and G22 of the first and second FinFET control transistors N3 丨 and N32 are formed to surround the active region ACTIVE, as compared to the side view of D0756.doc • J7·1339438 of FIG. 6C, thereby elongating the Channel CH of the gate. Alternatively, the first and second control transistors N31 and N32 may have a multi-channel field effect transistor (McFET) structure. Figure 7D is a side elevational view of a phase change memory cell in accordance with another embodiment of the present invention. The McFET is illustrated in Figure 7D.
McFET之結構與FinFET之結構類似,但在如圖7D中所 說明之活性區域ACTIVE方面不同於FinFET。換言之,圖 7D之活性區域ACTIVE以不同於圖7C之方式形成以使得通 道CH較長。 如上文所述,根據本發明之相變記憶體單元之第一及第 二控制電晶體可具有一平面電晶體結構、一 FinFET結構或 一 McFET結構。 圖8A為說明根據本發明之一實施例諸如圖6A及圖7a中 所展示的接觸插塞分別至第一及第二基板812及814之連接 的圖。參看圖8A,一接觸插塞Cpi連接至第一基板812之 頂部及第二基板8 14之底部。—接觸插塞cp2連接至第二基 板814之頂部。又,接觸插塞cp2可連接至—外部電源,例 如接地電壓源。 然而,第一基板8〗2至一外部電源之電連接促使接觸插 塞CP1及CP2與第-及第二基板812及814之接觸表面上的 接觸電阻。因此,希望緩和該接觸電阻。 ,圖為說明根據本發明之另一實施例接觸插塞至基板之 連接的圖,該連接減小接觸電阻。The structure of the McFET is similar to that of the FinFET, but differs from the FinFET in the active area ACTIVE as illustrated in Figure 7D. In other words, the active region ACTIVE of Fig. 7D is formed in a manner different from that of Fig. 7C to make the channel CH longer. As described above, the first and second control transistors of the phase change memory cell according to the present invention may have a planar transistor structure, a FinFET structure or a McFET structure. Figure 8A is a diagram illustrating the connection of the contact plugs shown in Figures 6A and 7a to the first and second substrates 812 and 814, respectively, in accordance with an embodiment of the present invention. Referring to Fig. 8A, a contact plug Cpi is connected to the top of the first substrate 812 and the bottom of the second substrate 814. - The contact plug cp2 is connected to the top of the second substrate 814. Also, the contact plug cp2 can be connected to an external power source such as a ground voltage source. However, the electrical connection of the first substrate 8 to 2 to an external power source causes contact resistance between the contact plugs CP1 and CP2 and the contact surfaces of the first and second substrates 812 and 814. Therefore, it is desirable to alleviate the contact resistance. Figure is a diagram illustrating the connection of a contact plug to a substrate in accordance with another embodiment of the present invention that reduces contact resistance.
H07S6MOC -J8· 1339438 圖6A中所說明之相變記憶體單元600之第二基板614及圖 、 7A中所說明之相變記憶體單元7〇〇之第二基板714經配置分 ' 別平行於第一基板612及第一基板712,且與第一基板612 及第一基板712部分地重疊。 特定言之,參看圖8B,垂直於第一基板812,將第二基 板814稍許對角地移動至第一基板812之左或右側。接觸插 塞CP由一導電層形成,該導電層連接至第二基板但不 Φ 被第二基板814分開,且自一外部電源(未圖示)延伸至第一 基板8 12。因此’顯著減小接觸電阻係可能的。 返回參看圖6A及圖7A,將可變電阻裝置616及716連接 至第一控制電晶體N31之汲極D1的接觸插塞Cp12&cp22, 以及將外部電源連接至第一控制電晶體N3丨之源極s丨及汲 極D1的接觸插塞CPU及CP12* 一導電層形成,該導電層 連接至第二基板614及714但不被第二基板614及714分開。 圖9A至圖9D為說明根據本發明之一實施例製造相變記 • 憶體單元之方法的橫截面圖。首先,參看圖9A,在一第一 基板912上形成一具有一源極 '閘極及汲極之第一控制電 • 晶體N31,藉由一絕緣材料II來包圍一閘極G11,且用一介 電層12塗覆該閘極G11之一底部。 接著,參看圖9B,在第一控制電晶體N3 1上形成一第二 基板914,且在該第一基板912上形成接觸插塞CP。及 CP12,且接觸插塞CP11及(:^^接觸該第二基板914。 接著,參看圖9C,在第二基板914上形成一具有一源 極、閘極及汲極之第二控制電晶體N32。最後,參看圖 110756.doc • 19- 1339438 90,在第二基板914上形成接觸插塞〇?21及0卩22,且經由 該接觸插塞CP22將一由一相變材料形成之可變電阻裝置 916連接至第二控制電晶體N32之源極及汲極之一者。 圖9 A至圖9D中所說明之方法可進一步包括形成一接觸 插塞,該接觸插塞將可變電阻裝置9丨6連接至第一控制電 晶體N3 1之源極或沒極;及形成_接觸插塞,該接觸插塞 將一外部電源連接至第一控制電晶體N3丨之源極或汲極, 如圖8 B所示。 上文已描述根據圖9A至圖9D之方法而獲得之相變記憶 體單元之構造。 如上文所述,根據本發明之半導體記憶裝置包括複數個 相變記憶體單元,每一相變記憶體單元具有形成於不同層 上之複數個控制t日曰曰體及由相變材料形成之可變電阻裝 置另夕卜》亥|導體5己憶裝置具有使用全局位元線及局部 位兀線之階層式位元線結構’藉此增加半導體記憶裝置之 整合密度及流經相變記憶體單元之每—者的電流量。 儘管已參看本發明之例示性實施例而特定展示並描述本 發明’但熟習此項技術者將瞭料在不㈣隨附之申請專 :範圍所界定之本發明之精神及範嘴的情況下作出各種形 式及細節變化。 【圖式簡單說明】 圖1為一習知相變記憶體單元之電路圖; 圖2為具有等同於圖丨之相 _ ,障體軍 文己隐體早兀之複數個相變記 心' 早凡的一相變記憶體陣列之電路圖. 110756.doc •20- 圖3為根據本發明之一實施例一相變記憶體單元之電路 圖; 圖4為說明圖3之相變記憶體單元之垂直結構的圖; 圏5為根據本發明之一實施例一半導體記憶裝置之一相 變記憶體陣列的電路圖,該相變記憶體陣列包括等同於圖 3之相變記憶體單元之複數個相變記憶體單元; 圓6A為根據本發明之一實施例一相變記憶體單元之橫截 面圖; 圖6B為圖6 A之相變記憶體單元之一第一控制電晶體之 平面圖; 圖6C為圖6A之相變記憶體單元之側視圖; 圖7A為根據本發明之另一實施例一相變記憶體單元之橫 截面圖; 圖7B為圖7A之相變記憶體單元之一第一控制電晶體之 平面圖; 圖7C為圖7A之相變記憶體單元之側視圖; 圖7D為根據本發明之另一實施例一相變記憶體單元之側 視圖; 圖8A為說明根據本發明之一實施例諸如圖6a或圖7A中 所說明的接觸插塞至基板之連接的圖; 圖8B為說明根據本發明之另一實施例接觸插塞至基板之 連接的圖,該連接減小接觸電阻; 圖9 A至圖9D為說明根據本發明之一實施例一製造一相 變記憶體單元之方法的橫截面圖。 110756.doc -21 · 1339438H07S6MOC -J8· 1339438 The second substrate 614 of the phase change memory cell 600 illustrated in FIG. 6A and the second substrate 714 of the phase change memory cell 7 illustrated in FIG. 7A are configured to be 'parallel to The first substrate 612 and the first substrate 712 partially overlap the first substrate 612 and the first substrate 712. Specifically, referring to Fig. 8B, perpendicular to the first substrate 812, the second substrate 814 is moved slightly diagonally to the left or right of the first substrate 812. The contact plug CP is formed of a conductive layer that is connected to the second substrate but is not Φ separated by the second substrate 814 and extends from an external power source (not shown) to the first substrate 812. Therefore 'significantly reducing the contact resistance is possible. Referring back to FIGS. 6A and 7A, the variable resistance devices 616 and 716 are connected to the contact plugs Cp12 & cp22 of the drain D1 of the first control transistor N31, and the external power source is connected to the first control transistor N3. The contact plug CPU of the source s and the drain D1 and the CP12* are formed of a conductive layer that is connected to the second substrates 614 and 714 but not separated by the second substrates 614 and 714. 9A through 9D are cross-sectional views illustrating a method of fabricating a phase change memory cell in accordance with an embodiment of the present invention. First, referring to FIG. 9A, a first control transistor N31 having a source gate and a drain is formed on a first substrate 912, and a gate G11 is surrounded by an insulating material II, and a gate is used. The dielectric layer 12 coats one of the bottoms of the gate G11. Next, referring to Fig. 9B, a second substrate 914 is formed on the first control transistor N31, and a contact plug CP is formed on the first substrate 912. And the CP12, and the contact plugs CP11 and (:^^ contact the second substrate 914. Next, referring to FIG. 9C, a second control transistor having a source, a gate and a drain is formed on the second substrate 914. N32. Finally, referring to FIG. 110756.doc • 19-1339438 90, contact plugs 21 and 22 are formed on the second substrate 914, and a phase change material is formed via the contact plug CP22. The variable resistance device 916 is coupled to one of the source and the drain of the second control transistor N32. The method illustrated in Figures 9A through 9D can further include forming a contact plug that will have a variable resistor The device 9丨6 is connected to the source or the pole of the first control transistor N31; and forms a contact plug, which connects an external power source to the source or the drain of the first control transistor N3 As shown in Fig. 8B. The configuration of the phase change memory cell obtained according to the method of Figs. 9A to 9D has been described above. As described above, the semiconductor memory device according to the present invention includes a plurality of phase change memories. Unit, each phase change memory unit has a plurality of layers formed on different layers Controlling the t-day body and the variable resistance device formed by the phase change material, in addition, the "Hei|conductor 5" device has a hierarchical bit line structure using global bit lines and local bit lines" The integrated density of the semiconductor memory device and the amount of current flowing through each of the phase change memory cells. Although the present invention has been specifically shown and described with reference to the exemplary embodiments of the present invention, those skilled in the art will (4) Attached application: Various forms and details are changed in the context of the invention and the scope of the invention as defined in the scope. [Fig. 1 is a circuit diagram of a conventional phase change memory unit; 2 is a circuit diagram with a phase change memory array of the same phase as the phase _, which is equivalent to the figure ,, the body of the body, and the early phase of the body. 110756.doc •20- Figure 3 is based on 1 is a circuit diagram of a phase change memory cell; FIG. 4 is a diagram illustrating a vertical structure of the phase change memory cell of FIG. 3; FIG. 5 is a phase of a semiconductor memory device according to an embodiment of the present invention. Variable memory array The phase change memory array includes a plurality of phase change memory cells equivalent to the phase change memory cells of FIG. 3; circle 6A is a cross-sectional view of a phase change memory cell according to an embodiment of the present invention; 6B is a plan view of a first control transistor of one phase change memory cell of FIG. 6A; FIG. 6C is a side view of the phase change memory cell of FIG. 6A; FIG. 7A is a phase change according to another embodiment of the present invention. Figure 7B is a plan view of the first control transistor of one of the phase change memory cells of Figure 7A; Figure 7C is a side view of the phase change memory cell of Figure 7A; Figure 7D is a side view of the phase change memory cell of Figure 7A; A further side view of a phase change memory cell; FIG. 8A is a diagram illustrating the connection of a contact plug to a substrate as illustrated in FIG. 6a or FIG. 7A in accordance with an embodiment of the present invention; FIG. 8B is an illustration A connection according to another embodiment of the present invention contacts a plug to a substrate, the connection reducing contact resistance; FIGS. 9A-9D are diagrams illustrating a method of fabricating a phase change memory cell in accordance with an embodiment of the present invention Cross-sectional view. 110756.doc -21 · 1339438
【主要元件符號說明】 10 習 知相變記憶體單元 30、 40 相 變記憶體單 元 50 第 一相變記憶 體單元組 51 局 部位元線 53 電 極 55 相 變層 57 較低電極 59A 第 一降落塾 59B 第 二降落塾 61A 第 一接觸插塞 61B 第 二接觸插塞 65 第 一控制電晶 體N31之- -閘 電 極 67 第 二控制電晶 體N32之- -閘 電 極 69A 第 二控制電晶 體N32之一 -汲 電 極 69B 第 二控制電晶 體N32之一 -源 電 極 70 第 二相變記憶體單元組 71A 第 一控制電晶 體N31之- -汲 電極 71B 第 一控制電晶 體N31之- •源 電 極 100 ' 300 相 變記憶體陣 列 600 ' 700 相 變記憶體單 元 612 、712、 812、 912第 一基板 614 ' 714、 814、 914第 二基板 616 、716、 916 可 變電阻裝置 110756.doc -22- 1339438[Major component symbol description] 10 conventional phase change memory unit 30, 40 phase change memory unit 50 first phase change memory unit group 51 local bit line 53 electrode 55 phase change layer 57 lower electrode 59A first landing塾 59B second drop 塾 61A first contact plug 61B second contact plug 65 - first control transistor N31 - - gate electrode 67 - second control transistor N32 - - gate electrode 69A second control transistor N32 One-electrode electrode 69B One of the second control transistor N32 - source electrode 70 Second phase change memory cell group 71A - First control transistor N31 - - 汲 electrode 71B First control transistor N31 - Source electrode 100 '300 phase change memory array 600' 700 phase change memory unit 612, 712, 812, 912 first substrate 614 '714, 814, 914 second substrate 616, 716, 916 variable resistance device 110756.doc -22- 1339438
ACTIVE 活性區域 BL 位元線 CH 通道 CP、CPI、CP2、 接觸插塞 CPI 1、CP12、 CP21 、 CP22 D1 第一控制電晶體N3 1之汲極 D2 第二控制電晶體N32之汲極 Gil 第一控制電晶體N3 1之閘極 G12、G22 閘極 G21 第二控制電晶體N32之閘極 GBL 全局位元線 11 絕緣材料 12 介電層 LBL1 第一局部位元線 LBL2 第二局部位元線 LBS1 第一局部位元線選擇訊號 LBS2 第二局部位元線選擇訊號 N1 選擇電晶體 N31 第一控制電晶體 N32 第二控制電晶體 N3 第一局部位元線選擇電路 N5 第二局部位元線選擇電路 R1 相變可變電阻裝置 110756.doc -23- 1339438 R3 可 變 電 阻 裝 置 SI 第 一 控 制 電 晶體N31之 源極 S2 第 二 控 制 電 晶體N32之 源極 Vss 參考 電 壓 /接地電壓 WL 字 線 I10756.doc •24-ACTIVE Active area BL bit line CH channel CP, CPI, CP2, contact plug CPI 1, CP12, CP21, CP22 D1 first control transistor N3 1 drain D2 second control transistor N32 drain Gil first Control transistor N3 1 gate G12, G22 gate G21 second control transistor N32 gate GBL global bit line 11 insulation material 12 dielectric layer LBL1 first local bit line LBL2 second local bit line LBS1 First local bit line selection signal LBS2 second local bit line selection signal N1 selection transistor N31 first control transistor N32 second control transistor N3 first local bit line selection circuit N5 second local bit line selection Circuit R1 Phase change variable resistance device 110756.doc -23- 1339438 R3 Variable resistance device SI First control transistor N31 source S2 Second control transistor N32 source Vss Reference voltage / ground voltage WL Word line I10756 .doc •24-
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