TWI339438B - Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell - Google Patents

Description

BRIEF DESCRIPTION OF THE DRAWINGS 1. Field of the Invention This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a stacked memory cell. [Prior Art] Phase change random access memory (PRAM) is formed of a phase change material such as a chalcogenide alloy, which when heated and cooled, becomes the first of the two phases, and when again When it is heated and cooled, it becomes the second phase. Here, the two phases are a crystalline phase and an amorphous phase. PRAM is disclosed in U.S. Patent Nos. 6,487,1, 3, and 6, 4,80,438. When the PRAM becomes crystalline, it has a low resistance value and has a high resistance value when it is amorphous. The logic value can be determined to be 0 or 1 based on the resistance value of the PRAM. The crystal of the PRAM corresponds to a set state or has a logic value of 0, and its amorphous corresponds to a reset state or has a logic value of one. In order to change the phase of the PRAM to an amorphous phase, the PRAM is heated to a temperature higher than the melting temperature of the PRAM and rapidly cooled. In order to change the phase of the PRAM to a crystalline phase, the PRAM is heated to a temperature below the melting temperature for a predetermined period of time. The key to PRAM is that it is formed from a phase change material such as a chalcogenide. Typically, the phase change material is a GST alloy composed of germanium (Ge), antimony (Sb), and tellurium (Te). When the GST alloy is heated or cooled, its state rapidly changes between an amorphous state (reset state) and a crystalline state (set state), in other words, its logic value is switched between 1 and 0. Therefore, the GST alloy is useful as a material for a PRAM memory device. 110756.doc f Writes the memory to the memory cell of the PRAM, heating the chalcogenide to a temperature specific to or greater than its melting temperature and rapidly cooling to make the chalcogenide amorphous. Further, the chalcogenide is heated at a temperature lower than the melting temperature, maintained at this temperature, and cooled to bring the chalcogenide into a crystalline state. Figure 1 is a circuit diagram of one of the conventional phase change recording limb units 10 disclosed in U.S. Patent No. 5,883,827. The memory unit 1 〇 includes a phase change variable electrical I5 device R1 ′ having a first terminal connected to the _ bit line and a second terminal connected to the -selecting the transistor core _ no pole; and the selection transistor N1 has its gate connected to a word line WL and its source connected to a reference voltage VSS. Figure 2 is a circuit diagram of a phase change memory array 1A comprising a plurality of phase change memory cells 10 equivalent to the phase change memory of Figure 。. The plurality of phase change memory cells 10 are connected to a bit line anal, which is connected to a sense amplifier (not shown). Recently, PRAM has attracted considerable attention as a lower-generation memory. However, there is a need to improve the integration of PRAMs to enable PRAMs to compete with other types of memory such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory. As described above, data is written to the PRAM by heating the PRAM using Joule heat. However, there is a limitation in reducing the size of the control transistor of the conventional memory cell, which provides the current required to generate Joule heat. This prevents an increase in the integration density of the PRAM. Therefore, there is a growing demand for a cell structure that can increase the integrated density of PRAM and a configuration of a semiconductor memory device using the improved cell structure. SUMMARY OF THE INVENTION The present invention provides a phase change memory cell 0 having an improved integrated density. The present invention also provides a semiconductor memory device having such a phase change random access memory (PRAM) cell. According to an aspect of the present invention, there is provided a phase change memory cell comprising: φ comprising a plurality of control transistors formed on different layers and a variable resistance device formed of a phase change material. In one embodiment, the number of control transistors is two. In another embodiment, the control transistors include: a first control transistor, which is a block transistor; and a second control transistor formed on the 6-first control transistor and A thin layer of transistor. In another embodiment, the control transistors further include a third control transistor formed on the first control transistor. The control transistors can be M〇S transistors and form a diode. These control transistors are visible. The condition includes a bipolar transistor. The second control transistor can be formed on the first control transistor. The variable resistance device may include 锗 (Ge), recording (called and hoof (Te) 〇 发明 发明 发明 发明 发明 发明 , , , , , , , , , , 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体Connected to the entire via: a local bit line selection circuit corresponding to the local bit lines, respectively:: or disconnected from the edge global bit line; and a plurality of phase change memories, and It is connected to the local bit line when it is stored in the I0756.doc material. Each of the phase change memory cells 7L of each of the phase change memory cell groups includes a plurality of control transistors formed on different layers, and a variable resistor formed of a phase change material Device. In one embodiment, the local bit line selection circuits are transistors that are coupled to the local bit lines or to the local bits in response to a local bit line selection signal. The meta-line is disconnected from the global bit line. The gates of all of the control transistors are connected to a corresponding word line. In another embodiment, the semiconductor memory device further includes a peripheral circuit as appropriate. The peripheral circuit can include an inverter circuit including a bulk transistor formed on a first layer and a thin layer transistor formed on the second layer. The bulk transistor may comprise an NM〇s transistor' and the thin layer transistor may comprise a PMOS transistor. In another embodiment, the semiconductor memory device further includes a sense amplifier coupled to the global bit line. According to still another aspect of the present invention, a phase change memory cell is provided, comprising: a plurality of control transistors having a gate connected to a word line and formed on different layers; and a variable resistance device each One of the control transistor and one of the second terminal and the second terminal is connected to the variable resistance device, and the other is connected to a ground voltage source. According to still another aspect of the present invention, a phase change memory unit includes: a first control transistor formed on a first substrate and having a source, a gate and a drain; and a second a substrate formed on the first control transistor; a second control transistor formed on the second substrate and having a source, a gate and a drain; and a variable resistance device connected to 110756.doc 1339438 The source of the second control transistor and one of the drains are formed of a phase change material. In one embodiment, the source of the first control transistor is electrically connected to the source of the second control transistor, and the drain of the first control transistor is electrically connected to the second control transistor. The drain is electrically connected to the gate of the second control transistor. In another embodiment, the first and second control transistors have a planar transistor structure, a fin field effect transistor structure or a multi-channel field effect transistor structure. In another embodiment, the second substrate is formed to be parallel to and partially overlap the first substrate. Connecting the variable resistor to a first contact plug of the source of the first control transistor and the one of the poles, and connecting an external power source to the source of the first control transistor A second contact plug of the pole and one of the drains is formed by a conductive layer. In another embodiment, the contact plugs are coupled to the source and the gate of the second control transistor. According to still another embodiment of the present invention, a method for fabricating a phase change memory cell is provided. The method includes: forming a first control circuit having a source, a gate, and a drain on a first substrate. Forming a second substrate on the first control transistor; forming a second control transistor having a source, a gate and a drain on the second substrate; and connecting a variable resistance device to The source of the second control transistor and one of the drains, the variable resistance device is formed of a phase change material. In one embodiment, the method further includes: forming a first contact plug 110756.doc -10- 1339438 plug, the variable resistance device being coupled to the source of the first control transistor and the drain And forming a second connection _ plug power source connected to the source of the first control transistor and one of the drains. [Embodiment] Hereinafter, an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the present disclosure, the same reference numerals are used to refer to the same or equivalent elements.

A cell structure of a semiconductor memory device according to an embodiment of the present invention will now be described with reference to Figs. In this embodiment, the semiconductor memory device represents a phase change random access memory (PRAM) formed of a phase change material. , ... Yisi bottle early -----. , mouth, "> rj" and the second control transistor 2, and a variable resistance device R3 formed of a phase change material. The open ends of the first and second control transistors N 3 i and N 3 2 are connected to a sub-line WL. The first terminals of the first and second control transistors N3 1 and each of the terminals are connected to a reference voltage, such as a ground voltage Vss. A second terminal of each of the individual first and second control transistors N3 and N32 is coupled to a first terminal of the variable resistance device R3. The second terminal of the cough variable resistance device R3 is connected to a one-dimensional wire. Referring to Fig. 4, the first and second control transistors N31 and N32 are formed on different layers. In one embodiment, the first control transistor N3 turns into a bulk transistor and the first control transistor N32 is a thin layer transistor. One of the gate electrode 65 of the first control transistor and the gate electrode 67 of the second control transistor N32 are connected to a predetermined line (not shown). The source electrode 71B of the first control transistor N31 and the second control transistor lW756.doc - 1339438 N32 one source electrode 69B is connected to the ground voltage Vss and a first landing pad 59A via a first contact plug 6IA. One of the first control transistor N3 and one of the second control transistor N32 is connected to a second landing pad 59B via a second contact plug 61B. The falling sputum 59B is connected to a phase change layer μ via a lower electrode 57. The phase change layer 55 is connected to a local bit line 5A via an electrode 53. The second control transistor N32 is a thin layer of transistor formed on an epitaxial layer (not shown). In different embodiments of different applications, the first and second control transistors N31 and N32 may be MOS transistors or bipolar transistors and may form a diode. According to this embodiment, the control transistors N31 and N32 are formed on different layers to increase the integration density of the semiconductor memory device. The phase change memory unit 3 includes control transistors N3 1 and N32 to increase the current flowing through the variable resistance device R3. This increased amount of current provides the heat necessary to rapidly change the phase of the device. However, including a plurality of control transistors N3 1 and N32 will increase the size of the phase change memory cell 30. To solve this problem, a plurality of transistors N31 and N32 are formed on different layers of the device. A third control transistor (not shown), which is a thin layer transistor, can be added to the phase change memory cell 30 to further increase the integration of the phase change memory cell. 5 is a circuit diagram of a phase change memory array 300 of a semiconductor memory device (not shown) in accordance with an embodiment of the present invention. The phase change memory array 300 includes a global bit line GBL; first and second local bit lines LBL1 and LBL2; and first and second phase change memory cell groups 5 and 7 (such as FIG. H0756.doc 12 1339438 Phase change memory unit 30) stores data when it is connected to local bit lines LBLI and LBL2, respectively. The local bit lines LBL1 and LBL2 are connected to the global bit line GBL via the first and second local bit line selection circuits N3 and N5, respectively, or are disconnected from the global bit line GBL. In other words, the local bit line selection circuit N3 & N5 may be a transistor that allows the local bit line LBU&LBL2 to be connected to the global bit line or to the global bit line in response to the local 4-bit line select signals LBS1 and LBS2. GBL is disconnected. In FIG. 5, only two local bit lines LBL1 and LBL2 are illustrated, but the number of local bit lines is not limited. ^ The first phase k is the mother of a plurality of phase change memory cells 3 of the memory cell group 50. And each of the plurality of phase memory cells 40 of the second phase change memory single & group 7 includes a plurality of control transistors formed on different layers and a phase change material. Variable resistance device. In Fig. 5, the number of phase change memory cells of each of the phase change hidden cell groups 50 and 70 is seven, however, the number of phase change memory cells is not limited thereto. Looking at Figure 5, the phase change memory cell unit 5 is connected to the first-local bit red, and the phase change memory cell of the second phase-change memory cell group 70 is 〇Connecting to the second partial bit line 第一 The first partial bit line selecting circuit N3 connects the first partial bit line to the global bit line in response to the first partial bit line selection signal LBS1. The second partial bit line selection circuit milk responds to the second partial bit line selection signal LBS2 to cause the first sheet to 仏_ a τ ^.卩 το line LBL2 is connected to the global bit line GBL 第 During the read or write operation, the first and second partial bit line selection signals 110756.doc 唬 lbs 1 and LBS2 allow selection in response to a bit address signal One of the individual first and second phase change memory cell groups 50 and 70 for reading or writing data. - A sense amplifier (not shown) is connected to the global bit line GBL to amplify the data read from the selected first or second phase change memory cell group 5 or 7 . As described above, in a semiconductor memory device according to an embodiment of the present invention, each memory cell is fabricated by forming a plurality of control transistors on different layers. Therefore, it is possible to supply a pr〇 gramming current to the phase change varistor device while reducing the size of each of the memory cells. Similarly, the use of global bit lines and local bit lines to implement a hierarchical bit line structure of a phase change memory cell array of a semiconductor memory device in accordance with the present invention is capable of producing a compact memory array. The semiconductor memory device according to the present invention may further include a peripheral circuit (not shown). The peripheral circuit may be an inverter circuit including a bulk transistor and formed on the bulk transistor. Thin layer transistor. The bulk transistor can be an NMOS 曰駚 曰駚 » μ μ 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且§ The integrated circuit of the semiconductor memory device will be further included when the NM〇s transistor formed on the χ, and the different layers and the inverter circuit of the pM〇s transistor are used by A + as the peripheral circuit: Μό (k, 〇〇a. For example, it is possible to increase the integration of the semiconductor memory device by adding the structure of the phase change memory cell 30 of FIG. 3 as a transistor of the peripheral circuit. According to the present invention, The control transistor constituting 4 intersecting memory soap cells is formed on different layers of 110756.doc 14 1339438, and the number of such control transistors may be more than one. The control transistor has been described with reference to FIG. 3, and thus will be omitted DETAILED DESCRIPTION In one application, a semiconductor memory device in accordance with the present invention is mounted in a system LSI logic die along with a logic die. Figure 6A is a cross section of a phase change memory cell 600 in accordance with an embodiment of the present invention. Figure 6B is a plan view of the -> control transistor N3 of the phase change memory cell 600 of Figure 6A. Figure 6C is a side view of the phase change memory cell 600 of Figure 6A. Referring to Figure 6A, phase change memory Body order 600 includes: a plurality of first control transistors N3I, each of which is formed on a first substrate 612 and has a source S, a gate G11, and a drain D1; one formed in the first control a second substrate 614 on the electric Bb body N3 1 ; a plurality of second control transistors N32 each formed on the second substrate 614 and having a source 52, a gate G2 1 and a drain D2 And a variable resistance device 6丨6 connected to one of the source S2, the gate G21 and the gate D2 of one of the second control transistors N32 and formed of a phase change material. For convenience, FIG. 6A illustrates that two of each of the first and second control transistors N3} and N32 are formed on the first and second substrates 612 and 614, respectively. However, according to the present invention, There is no limitation on the number of first control transistors N31 formed on the first substrate 612 and the number of second control transistors N32 to be formed on the second substrate 614. The phase change memory unit 6 of Fig. 6A Corresponding to the cross-section of the phase change memory cell 30 illustrated in FIGS. 3 and 4 during the fabrication of the phase change memory cell 3〇0)I07 56.doc -15- 1339438 The source S 1 of the first control transistor N3 1 is electrically connected to the source S2 of the second control transistor N32, and the drain D1 of the first control transistor N3 1 is electrically connected to the A control pole D 2 of the transistor N32. These electrical connections are provided via contact plugs CP11 and CP22. Specifically, the source S 1 of the first control transistor N 3 1 is connected to the contact plug c P11 , and the contact plug CP 11 is connected to the second substrate 614. Further, the source S2 of the second control transistor N32 is connected to the contact plug CP21. Similarly, the drain D1 of the first control transistor N 3 1 is connected to the contact plug CP12'. The contact plug CP12 is connected to the second substrate 614. Further, the drain D2 of the second control transistor N32 is connected to the contact plug CP22. The contact plugs CP11, CP21, CP12 and CP22 are conductive layers that allow electrical conduction. The gate G11 of the first control transistor N31 is electrically connected to the gate G21 of the second control transistor N32. This electrical connection is performed via a contact plug CP (not shown in Fig. 6) of Fig. 6C. In Fig. 6A, 11 denotes an insulating material, and 12 denotes a dielectric layer. The first and second control transistors N3i and Ν32 of Fig. 6 have a planar crystal structure. A planar transistor is a transistor in which a gate is formed on a substrate. Figure 6 is a plan view of the first control transistor Ν 31. The first control transistor is a planar transistor. Referring to circle 6B, gates G11 and G12 are formed on the first substrate 612. Figure 6C is a side elevational view of the phase change memory cell 6A of Figure 6A. Referring to FIG. 6C, the gates Gu of the first control transistor N31 and the gates 第二2 of the second control transistor N32 are horizontally formed on the first and second substrates 612 and 614, and the I10756.doc • 16-1339438 extension The full width of the phase change S memory cell 600. The gates G11 and G21 are electrically connected via the ~ contact plug CP. In addition, an active region ACTIVE (i.e., source and drain regions) is formed in each of the first and second substrates 612 and 614. Figure 7A is a cross-sectional view of a phase change memory cell 7A according to another embodiment of the present invention. The structure of the phase change memory cell 7〇〇, except that the plurality of first and second control transistors N3 1 and N32 have a fin field effect transistor φ (FlnFET) structure, and the phase change memory of FIG. 6A Unit 600 is constructed identically. In other words, the first control transistor N3I is formed on a first substrate 7]2, and a second substrate 714 is formed on the first control transistor N31. The second control transistor N32 is formed on the second substrate 714. A variable resistance device 716 is connected to the drains of the first and second control transistors N3 1 and N32 via contact plugs CP1 and CP22, respectively. Further, the first and second control transistors N3 and N32 are electrically connected via a contact plug and a CP 22 .

The FmFET has a structure in which gate electrodes are formed along both sides of a channel, and thus the gate electrodes have a long channel length, thereby suppressing the short channel effect. Figure 7B is a plan view of the first control transistor N31 of the phase change memory cell 7 of Figure 7A. Fig. 7B illustrates that the first substrate 712 has a smaller area than the first substrate 612, since the FinFET is used as the first control transistor N31 in this embodiment. Figure 7C is a side view of the phase change memory cell 700 of Figure 7A. The gates G1 1 and G22 of the first and second FinFET control transistors N3 丨 and N32 are formed to surround the active region ACTIVE, as compared to the side view of D0756.doc • J7·1339438 of FIG. 6C, thereby elongating the Channel CH of the gate. Alternatively, the first and second control transistors N31 and N32 may have a multi-channel field effect transistor (McFET) structure. Figure 7D is a side elevational view of a phase change memory cell in accordance with another embodiment of the present invention. The McFET is illustrated in Figure 7D.

The structure of the McFET is similar to that of the FinFET, but differs from the FinFET in the active area ACTIVE as illustrated in Figure 7D. In other words, the active region ACTIVE of Fig. 7D is formed in a manner different from that of Fig. 7C to make the channel CH longer. As described above, the first and second control transistors of the phase change memory cell according to the present invention may have a planar transistor structure, a FinFET structure or a McFET structure. Figure 8A is a diagram illustrating the connection of the contact plugs shown in Figures 6A and 7a to the first and second substrates 812 and 814, respectively, in accordance with an embodiment of the present invention. Referring to Fig. 8A, a contact plug Cpi is connected to the top of the first substrate 812 and the bottom of the second substrate 814. - The contact plug cp2 is connected to the top of the second substrate 814. Also, the contact plug cp2 can be connected to an external power source such as a ground voltage source. However, the electrical connection of the first substrate 8 to 2 to an external power source causes contact resistance between the contact plugs CP1 and CP2 and the contact surfaces of the first and second substrates 812 and 814. Therefore, it is desirable to alleviate the contact resistance. Figure is a diagram illustrating the connection of a contact plug to a substrate in accordance with another embodiment of the present invention that reduces contact resistance.

H07S6MOC -J8· 1339438 The second substrate 614 of the phase change memory cell 600 illustrated in FIG. 6A and the second substrate 714 of the phase change memory cell 7 illustrated in FIG. 7A are configured to be 'parallel to The first substrate 612 and the first substrate 712 partially overlap the first substrate 612 and the first substrate 712. Specifically, referring to Fig. 8B, perpendicular to the first substrate 812, the second substrate 814 is moved slightly diagonally to the left or right of the first substrate 812. The contact plug CP is formed of a conductive layer that is connected to the second substrate but is not Φ separated by the second substrate 814 and extends from an external power source (not shown) to the first substrate 812. Therefore 'significantly reducing the contact resistance is possible. Referring back to FIGS. 6A and 7A, the variable resistance devices 616 and 716 are connected to the contact plugs Cp12 & cp22 of the drain D1 of the first control transistor N31, and the external power source is connected to the first control transistor N3. The contact plug CPU of the source s and the drain D1 and the CP12* are formed of a conductive layer that is connected to the second substrates 614 and 714 but not separated by the second substrates 614 and 714. 9A through 9D are cross-sectional views illustrating a method of fabricating a phase change memory cell in accordance with an embodiment of the present invention. First, referring to FIG. 9A, a first control transistor N31 having a source gate and a drain is formed on a first substrate 912, and a gate G11 is surrounded by an insulating material II, and a gate is used. The dielectric layer 12 coats one of the bottoms of the gate G11. Next, referring to Fig. 9B, a second substrate 914 is formed on the first control transistor N31, and a contact plug CP is formed on the first substrate 912. And the CP12, and the contact plugs CP11 and (:^^ contact the second substrate 914. Next, referring to FIG. 9C, a second control transistor having a source, a gate and a drain is formed on the second substrate 914. N32. Finally, referring to FIG. 110756.doc • 19-1339438 90, contact plugs 21 and 22 are formed on the second substrate 914, and a phase change material is formed via the contact plug CP22. The variable resistance device 916 is coupled to one of the source and the drain of the second control transistor N32. The method illustrated in Figures 9A through 9D can further include forming a contact plug that will have a variable resistor The device 9丨6 is connected to the source or the pole of the first control transistor N31; and forms a contact plug, which connects an external power source to the source or the drain of the first control transistor N3 As shown in Fig. 8B. The configuration of the phase change memory cell obtained according to the method of Figs. 9A to 9D has been described above. As described above, the semiconductor memory device according to the present invention includes a plurality of phase change memories. Unit, each phase change memory unit has a plurality of layers formed on different layers Controlling the t-day body and the variable resistance device formed by the phase change material, in addition, the "Hei|conductor 5" device has a hierarchical bit line structure using global bit lines and local bit lines" The integrated density of the semiconductor memory device and the amount of current flowing through each of the phase change memory cells. Although the present invention has been specifically shown and described with reference to the exemplary embodiments of the present invention, those skilled in the art will (4) Attached application: Various forms and details are changed in the context of the invention and the scope of the invention as defined in the scope. [Fig. 1 is a circuit diagram of a conventional phase change memory unit; 2 is a circuit diagram with a phase change memory array of the same phase as the phase _, which is equivalent to the figure ,, the body of the body, and the early phase of the body. 110756.doc •20- Figure 3 is based on 1 is a circuit diagram of a phase change memory cell; FIG. 4 is a diagram illustrating a vertical structure of the phase change memory cell of FIG. 3; FIG. 5 is a phase of a semiconductor memory device according to an embodiment of the present invention. Variable memory array The phase change memory array includes a plurality of phase change memory cells equivalent to the phase change memory cells of FIG. 3; circle 6A is a cross-sectional view of a phase change memory cell according to an embodiment of the present invention; 6B is a plan view of a first control transistor of one phase change memory cell of FIG. 6A; FIG. 6C is a side view of the phase change memory cell of FIG. 6A; FIG. 7A is a phase change according to another embodiment of the present invention. Figure 7B is a plan view of the first control transistor of one of the phase change memory cells of Figure 7A; Figure 7C is a side view of the phase change memory cell of Figure 7A; Figure 7D is a side view of the phase change memory cell of Figure 7A; A further side view of a phase change memory cell; FIG. 8A is a diagram illustrating the connection of a contact plug to a substrate as illustrated in FIG. 6a or FIG. 7A in accordance with an embodiment of the present invention; FIG. 8B is an illustration A connection according to another embodiment of the present invention contacts a plug to a substrate, the connection reducing contact resistance; FIGS. 9A-9D are diagrams illustrating a method of fabricating a phase change memory cell in accordance with an embodiment of the present invention Cross-sectional view. 110756.doc -21 · 1339438

[Major component symbol description] 10 conventional phase change memory unit 30, 40 phase change memory unit 50 first phase change memory unit group 51 local bit line 53 electrode 55 phase change layer 57 lower electrode 59A first landing塾 59B second drop 塾 61A first contact plug 61B second contact plug 65 - first control transistor N31 - - gate electrode 67 - second control transistor N32 - - gate electrode 69A second control transistor N32 One-electrode electrode 69B One of the second control transistor N32 - source electrode 70 Second phase change memory cell group 71A - First control transistor N31 - - 汲 electrode 71B First control transistor N31 - Source electrode 100 '300 phase change memory array 600' 700 phase change memory unit 612, 712, 812, 912 first substrate 614 '714, 814, 914 second substrate 616, 716, 916 variable resistance device 110756.doc -22- 1339438

ACTIVE Active area BL bit line CH channel CP, CPI, CP2, contact plug CPI 1, CP12, CP21, CP22 D1 first control transistor N3 1 drain D2 second control transistor N32 drain Gil first Control transistor N3 1 gate G12, G22 gate G21 second control transistor N32 gate GBL global bit line 11 insulation material 12 dielectric layer LBL1 first local bit line LBL2 second local bit line LBS1 First local bit line selection signal LBS2 second local bit line selection signal N1 selection transistor N31 first control transistor N32 second control transistor N3 first local bit line selection circuit N5 second local bit line selection Circuit R1 Phase change variable resistance device 110756.doc -23- 1339438 R3 Variable resistance device SI First control transistor N31 source S2 Second control transistor N32 source Vss Reference voltage / ground voltage WL Word line I10756 .doc •24-

Claims (1)

1339438 (* 丄 095114912 Patent Application Chinese Patent Application Substitution (October 1997) X. Patent Application Range: 1 · A phase change memory unit comprising: a plurality of controls formed on different layers a transistor; and a variable resistance device formed of a phase change material, the variable power device coupled to each of the control transistors, wherein the plurality of control transistors are connected in parallel with each other. The phase change memory unit of the request item, wherein the number of the control transistors is two. Repair 3. The phase change memory unit of the request, wherein the control transistor comprises: a first control transistor, a piece of transistor; and a first control transistor formed on the first control transistor and being a thin layer of transistors. Into the crystal 4. The phase change memory unit of claim 3 The control transistor includes a third control body formed on the second control transistor. 5. The phase change memory unit of claim 4, wherein each of the control transistors is one of a MOS transistor and a bipolar transistor. 6. The phase change memory unit of claim 4, wherein the body forms a diode. Wherein the plurality of control electrodes 7. In the phase change memory unit of claim 1, the 彳 resistance resistor device includes 锗 (Ge), 锑 (Sb), and 碲 (Te). 8. A semiconductor memory device, comprising: a global bit line; IJ0756-971017.doc a plurality of local bit lines connected to the local bit line selection circuit corresponding to the local bit lines, respectively The global bit line is disconnected from the global bit line; and a plurality of phase change memory cell groups are stored when they are respectively connected to the local bit lines, wherein the phase change memory cell group Each of the phase change memory cells of each of: comprising: a plurality of control transistors formed on different layers; and a variable resistance device formed of a phase change material, the variable power device Each of the control transistors is coupled to the plurality of control transistors that are connected in parallel with each other. 9. The semiconductor memory device of claim 8, wherein the local bit line selection circuit is a transistor that is coupled to the global bit line or in response to a local bit line selection signal The local bit lines are disconnected from the global bit line. 10. The semiconductor memory device of claim 8, wherein the gates of the control transistors are coupled to a respective word line. 11. The semiconductor memory device of claim 8, wherein the number of the plurality of control electro-crystals is two. 12. The semiconductor memory device of claim 8, wherein each of the plurality of control transistors comprises: - a first control transistor, which is a block transistor; and a first control transistor formed on the The first control electro-crystal is a thin layer of transistors. The semiconductor memory device of claim 12, wherein each of the plurality of control transistors further comprises a third control transistor formed on the second control transistor. 14. The semiconductor memory device of claim 13, wherein each of the control transistors is one of a MOS transistor and a bipolar transistor. 15. The semiconductor memory device of claim 13, wherein the plurality of control transistors form a diode. 16. The semiconductor memory device of claim 8, wherein the variable resistance device comprises germanium (Ge), germanium (Sb), and germanium (Te). 17. The semiconductor memory device of claim 8, further comprising a peripheral circuit, wherein the peripheral circuit is an inverter circuit comprising a bulk transistor and a thin layer of electricity formed on the bulk transistor Crystal. 18. The semiconductor memory device of claim 17, wherein the bulk transistor is an NMOS transistor and the thin layer transistor is a pmS transistor. 19. The semiconductor memory device of claim 18, further comprising a sense amplifier coupled to the global bit line. 20. A phase change memory cell comprising: a plurality of control transistors, each of which is connected to a same word line, and the control transistors are formed on different layers; A variable resistance device formed by a phase change material, wherein one of a first terminal and a second terminal of each of the control transistors is connected to the variable resistance device, and the other is connected to a ground The voltage, wherein the plurality of control transistors are connected to each other in parallel with 110756-971017.doc 1339438. The phase change memory unit of claim 20, wherein the control transistors comprise: - a first control transistor, which is a block transistor; and a second control transistor formed at the first Control the transistor and be a thin layer of transistor. 22. The phase change memory cell of claim 21, wherein the control transistor further comprises a third control transistor formed on the second control transistor 23. The phase change memory of claim 20 a unit, wherein each of the control transistors is one of a MOS transistor and a bipolar transistor. 24. The phase change memory unit of claim 20, wherein the control transistors form a diode. 25. A phase change memory cell, comprising: a first control transistor formed on a first substrate and having a source, a gate and a drain; a second substrate formed on the first a control transistor; a second control transistor formed on the second substrate and having a source, a gate and a drain; and a variable resistance device connected to the second control transistor One of the source and the drain is formed by a phase change material, wherein: the source of the first control transistor is electrically connected to the source of the second control transistor; the first control transistor The drain is electrically connected to the drain of the second control transistor I10756-971017.doc 1339438; and the gate of the first control transistor is electrically connected to the gate of the second control transistor. 26. The phase change memory cell of claim 25, wherein the first and second control transistors have a planar transistor structure. 27. The phase change memory cell of claim 25, wherein the first and second control transistors have a fin field effect transistor structure. 28. The phase change memory cell of claim 25, wherein the first and second control transistors have a multi-channel field effect transistor structure. 29. The phase change memory cell of claim 25, wherein the first control transistor is a bulk transistor and the second control transistor is a thin layer transistor. 30. The phase change memory cell of claim 25, wherein the second substrate is formed parallel to the first substrate and partially overlaps the first substrate, and the variable resistance device is connected to the first control a first contact plug of the source of the crystal and one of the drains, and a second contact plug connecting an external power source to the source of the first control transistor and one of the drains The plug is formed by a conductive layer. 31. The phase change memory unit of claim 30, wherein the contact plugs are coupled to the source and the drain of the second control transistor. 32. The phase change memory cell of claim 25, wherein the first and second control transistors have a structure selected from the group consisting of a planar transistor structure, a fin field effect transistor structure, and a multi-channel field effect transistor structure. Different structures. 33. A method of fabricating a phase change memory cell, comprising: forming a source, a gate, and a drain on a first substrate 110756-971017.doc 1339438 34. 35. 36. 37. 38. 39. A control transistor; forming a second substrate on the first control transistor; forming a second control circuit having a source, a gate and a drain on the second substrate a crystal; and connecting a variable resistance device to the source of the second control transistor and the drain, the variable resistance device being formed of a phase change material, wherein: the first control transistor The source is electrically connected to the source of the second control electric body; the drain of the first control transistor is electrically connected to the drain of the second control electric body; and the first control transistor The gate is electrically connected to the gate of the second control electric body. The method of claim 33 wherein the first and second control transistors have a planar transistor structure. The method of claim 33, wherein the first and second control transistors have a rotating field effect transistor structure. The method of claim 33 wherein the first and second control transistors have a multi-channel field effect transistor structure. The method of claim 33, wherein the first control transistor is a bulk electrical body and the second control transistor is a thin layer transistor. The method of claim 33, wherein the second substrate is formed such that it is parallel to and partially overlaps the "substrate substrate. The method of claim 38, further comprising forming a first contact plug B 曰曰曰曰曰 110756-97l017.doc -6 - 1339438 plug, the variable resistor 奘w μ , the 丨 and the device are connected to the The source of the first control transistor and one of the poles, B jny 1, λ. have, and form a second contact plug, which connects an external power source to the first batch. The source of the electric solar body and one of the drain electrodes, wherein the contact plugs are formed by a conductive layer. 40. The method of claim 39, wherein the contact plug is connected to the source of the second control transistor and the drain. 41. The method of claim 33, wherein the bean flute, the first child and the second control transistor have a structure selected from the group consisting of a planar transistor structure, a fin type % effect transistor structure, and a multi-channel % effect system Different structures of the crystal structure. 110756-971017.doc