TWI338365B - Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory - Google Patents
Non-volatile memory and manufacturing method and operating method thereof and circuit system including the non-volatile memory Download PDFInfo
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P950162 22261 twf.doc/n 九、發明說明: 【發明所屬之技術領織】 本發明是有關於·__>錄坐道μ _ 方法,特別是錢於及其製造方法與操作 操作方法。 _揮贿記㈣及造方法與 【先前技術】 非揮發性記憶體中的 (職_有可進行的二電;=可程式唯讀記憶體 動作,且存人之資料存人、讀取、抹除等 成為個人電腦 典型的可電抹除且ί 種記憶體元件。 層_2〇祕㈣哪娜之間的絕緣 」而Jl述可電抹除且可程式唯讀記憶體需要形成多 個多晶發層與多個氧化碎層。在製作過程中,會經過多道 光罩步驟’不但拉長製作流程,且耗費鮮的製造成本。 ,上述可電抹除且可程式唯讀記憶體在一個記憶胞中 只能夠儲存一位元之資料,雙層閘極也會佔去較多空間’ 不利於元件的積集化趨勢。 之後’業界提出了具有氮化物電荷陷入層的記憶體, 此&己憶胞結構係藉由將電荷陷入(trapping)於氮化矽的介 電層中’而儲存資料。雖然此種具有氮化物電荷陷入層之 &己憶體能夠在單一記憶胞中儲存二位元資料,然而這兩位 P9S0162 22261rwf.doc/n 元的資料容易互相影響,造成可靠度的下降,且其尚有電 荷保持力(endurance)不佳的問題。再加上現今對於元件積 集度的要求越來越高,亟需一種具有高元件積集度、高可 靠性的非揮發性記憶體。 【發明内容】 有鑑於此,依A?、本發明提供實施例之目的就是在提供 一種非揮發性記憶體,可以在單—記憶胞中儲存多個位^ 的資料。 依照本發明提供實施例之再一目的是提供—種非揮發 性記憶體的製造方法’湘多次自行對準的方式而形成可 在單一記憶胞中儲存多位元資料的非揮發性記憶體。 依照本發明提供實施例之又一目的是提供—種非揮發 性記憶體的操作方法’可⑽作單—記憶胞巾的多個位元。 本發明提出一種非揮發性記憶體,包括設置於基底上 之一記憶胞,此記憶胞包括第—單元、半導體層第二單 4雜區。第-單元包括第—閘極、第―電荷陷入層與 第,電荷陷人層’其t,第-電荷陷人層與第二電荷陷入 層设置於第一閘極兩側。半導體層設置於基底上,覆芸住 第-單元’且半導體層的橫向尺寸大於第—單元的橫=尺 寸:第"Γ單元設置於半導體層上,以半導體層為對稱軸, ,第一單元鏡像對稱。第二單元包括設置於半導體層上之 ,閘極,以及5又置於第一閘極兩側之第三電荷陷入層與 =四電荷陷人層。摻雜區設置於半導體層兩側,用以作為 第一早元與第二單元共用之源極/汲極區。 P950I62 22261twf.doc/n 依照本發明實施例所述之非揮發性記憶體,其中第一 %入層、第一電荷陷入層、第三電荷陷入層與第四電 荷入層的材質包括奈米結晶(nan〇Crysta丨)、組氧化層、 鈦酸锶層或铪氧化層。 依照本發明實施例所述之非揮發性記憶體,其中第一 電荷入層、第一電荷陷入層、第三電荷陷入層與第四電 荷陷入層的材質包括氮化石夕。 “依照本發明實施例所述之非揮發性記憶體,其中第一 電荷入層、第二電荷陷入層、第三電荷陷入層與第四電 荷陷入層的材質包括氧化矽/氮化矽/氧化矽(〇N〇)複合材 料。 ^依照本發明實施例所述之非揮發性記憶體,其中第一 單元位於基底中,且第一單元與基底之間設置有一層保護 層。 依照本發明實施例所述之非揮發性記憶體,其中基底 上設置有介電層,且第一單元設置於介電層中。 依照本發明實施例所述之非揮發性記憶體,更包括多 個記憶胞,於基底上排列成一行/列陣列。 依照本發明實施例所述之非揮發性記憶體,其中,同 —行上的這些記憶胞以鏡像對稱的方式鄰接設置。 依照本發明實施例所述之非揮發性記憶體,其中以鏡 像對稱的方式配置的相鄰二記憶胞,共用—個摻雜區。 依照本發明實施例所述之非揮發性記憶體,更包括多 數條底字元線、多數條頂t元線A多數條位元線。這些底 P950162 22261twf.d〇c/n 字元線在行方向上平行排列,連接同一行之這些記憶胞的 第一閘極條頂字元線在行方向上平行排列,連接同一 行之5己‘丨思胞的第二閘極;多條位元線在列方向上平行排 列’連接同一列之記憶胞的摻雜區。 依照本發明實施例所述之非揮發性記憶體,更包括一 詹穿随介電層,分別設置於第—單元與半導體層之間 二單元與半導體層之間。 依照本發明實施例所述之非揮發性記憶體,其中之穿 隧介電層包含一多層結構。 ' 依照本發明實施例所述之非揮發性記憶體,其中之多 層結構為一最底層氧化矽/中間層氮化矽/最上層氧化 (ΟΝΟ)的複合材料。 依照本發明實施例所述之非揮發性記憶體,1中在 合材料最底層的氧化料度為小於2奈米,例如是介於約 0‘5至2奈米,或是小於1 5奈米。 依照本發明實施例所述之非揮發性記憶體,1 合材料中間層的氮化赠度為小於2奈米,例如是介 1至2奈米。 、、 依照本發明實施例所述之非揮發性記憶體,P950162 22261 twf.doc/n Nine, the invention description: [Technical woven fabric of the invention] The present invention relates to the __> recording lane _ method, in particular, and its manufacturing method and operation method. _==================================================================================================== Wiping and so on become the typical erasable and 记忆 memory components of personal computers. Layer 2 〇 secret (4) 哪 between the insulation of the Nina and Jl can be electrically erased and programmable read-only memory needs to form multiple Polycrystalline hair layer and multiple oxidized layer. During the production process, multiple reticle steps will pass through, which not only lengthen the production process, but also consumes a small manufacturing cost. The above-mentioned electrically erasable and programmable read-only memory is A memory cell can only store one bit of data, and a double-layer gate also takes up more space', which is not conducive to the accumulation of components. Then the industry has proposed a memory with a nitride charge trapping layer. & recalls the cell structure by storing the charge trapped in the dielectric layer of the tantalum nitride. Although such a nitride charge trapping layer can be in a single memory cell Store two-digit data, however these two P9S0162 222 The 61rwf.doc/n data is easy to influence each other, causing a decrease in reliability, and it has a problem of poor charge retention. Nowadays, the requirements for component accumulation are getting higher and higher. There is a need for a non-volatile memory having high component integration and high reliability. In view of the above, the object of the present invention is to provide a non-volatile memory, which can be A single-memory cell stores a plurality of bits of data. A further object of the present invention is to provide a non-volatile memory manufacturing method that can be formed in a single memory by multiple self-alignment methods. Non-volatile memory for storing multi-bit data in cells. A further object of embodiments according to the present invention is to provide a method for operating non-volatile memory, which can (10) be a single-memory cell. The present invention provides a non-volatile memory comprising a memory cell disposed on a substrate, the memory cell comprising a first unit and a second single 4 impurity region of the semiconductor layer. The first unit includes a first gate, a first The charge trapping layer and the first, the charge trapping layer 't, the first-charge trapping layer and the second charge trapping layer are disposed on both sides of the first gate. The semiconductor layer is disposed on the substrate to cover the first-cell' The lateral dimension of the semiconductor layer is larger than the horizontal dimension of the first cell: the first "Γ cell is disposed on the semiconductor layer, and the semiconductor layer is symmetrical, and the first cell is mirror-symmetrical. The second cell is disposed on the semiconductor layer, a gate, and a third charge trapping layer and a four-charge trapping layer disposed on both sides of the first gate. The doped regions are disposed on both sides of the semiconductor layer for sharing as the first early element and the second unit The source/drain region of P950I62 22261 twf.doc/n is a non-volatile memory according to an embodiment of the invention, wherein the first % in-layer, the first charge trapping layer, the third charge trapping layer and the fourth charge The material of the in-layer includes nanocrystals (nan〇Crysta丨), a group oxide layer, a barium titanate layer or a tantalum oxide layer. According to the non-volatile memory of the embodiment of the invention, the material of the first charge-in layer, the first charge-trapping layer, the third charge-trapping layer and the fourth charge-trapping layer comprises nitrite. The non-volatile memory according to the embodiment of the present invention, wherein the materials of the first charge in-layer, the second charge trapping layer, the third charge trapping layer and the fourth charge trapping layer comprise yttrium oxide/tantalum nitride/oxidation矽(〇N〇) composite material. The non-volatile memory according to the embodiment of the invention, wherein the first unit is located in the substrate, and a protective layer is disposed between the first unit and the substrate. The non-volatile memory of the embodiment, wherein the substrate is provided with a dielectric layer, and the first unit is disposed in the dielectric layer. The non-volatile memory according to the embodiment of the invention further includes a plurality of memory cells. Arranging a row/column array on a substrate. The non-volatile memory according to the embodiment of the invention, wherein the memory cells on the same line are arranged adjacent to each other in a mirror symmetrical manner. The non-volatile memory, wherein the adjacent two memory cells are arranged in a mirror-symmetrical manner, sharing a doped region. The non-volatile memory according to the embodiment of the invention further includes a plurality of strips. The word line, the majority of the top t-yuan line A, and the plurality of bit lines. These bottom P950162 22261twf.d〇c/n character lines are arranged in parallel in the row direction, connecting the first gate strips of the memory cells of the same row. The word lines are arranged in parallel in the row direction, and are connected to the second gate of the 5th cell of the same row; the plurality of bit lines are arranged in parallel in the column direction to connect the doped regions of the memory cells of the same column. The non-volatile memory of the embodiment of the invention further includes a dielectric layer disposed between the second unit and the semiconductor layer between the first unit and the semiconductor layer. The volatile memory, wherein the tunneling dielectric layer comprises a multilayer structure. The non-volatile memory according to the embodiment of the invention, wherein the multilayer structure is a bottommost yttrium oxide/intermediate layer of tantalum nitride/ The uppermost layer of oxidized (ΟΝΟ) composite material. According to the non-volatile memory of the embodiment of the invention, the oxidizing degree of the bottom layer of the composite material is less than 2 nm, for example, between about 0'5 and 2 nm, or less than 15 nm. In the non-volatile memory of the embodiment of the invention, the nitrided contribution of the intermediate layer of the composite material is less than 2 nm, for example, 1 to 2 nm, and is non-volatile according to an embodiment of the present invention. Memory,
合材料最上㈣氧切厚度為小於2奈米,例如是 L5至2奈米。 U 本發明提出-種非揮發性記憶體的製造方法 是先提供基底。於基底上依序形成一絕緣層與―; 層。然後於基底上形成第—介電層,第—介電層具有一第 P950162 2226ltwf.doc/n 一開口 ’裸露出底導體層。接著於第—開 元,第-單元包括:第一電荷陷入層與第二電单 分別形成於第-開4側壁;以及第—服層’ 並且電性賴底導體層。繼祕基底上形人=’ 第二介電層具有第二開口,裸露出第-單it。’ 開口中形成第三介電層,覆蓋住第—單元。^ 中形成一半導體層,覆蓋住第—單元,且半導體 第-:元之橫向尺寸。接下來,於半導;= 成第-早兀’弟二單元包括:第二閘極,形成於 上’以及第三電荷陷人層與第四電荷陷人層, 二 第二明t之於半導體層兩側之中形成—摻雜^ 法,:ίί右例所述之非揮發性記憶體的製造方 於凹陷’且絕緣層與底導體層是依序形成 法,發,實Γ賴述之非揮發性記憶體的製造方 4 /、中弟早兀的形成方法例如是先於開口中 電荷陷入材料層、然後移除部分電荷陷人材料層f於^ ,壁分別形成第-電荷陷入層與第二電荷陷二:;且 底導體層。接著於開口中填滿第1二連接 法,㈣所述之非揮發性記憶體的製造方 二電於第-電荷陷入層與第 …、本發月貝〜例所述之非揮發性記,It體的製造方 1338365 P950162 22261 twf.doc/n 法’其中第二單元的形成方法例如是於先基底上形成第二 閘極,然後在基底上依序形成—層電荷陷入材料層。接著, 移除部分電相人材料層,分別於第二閘極兩側形成第三 電荷陷入層與第四電荷陷入層。 依照本發明實施例所述之非揮發性記憶體的製造方 法,更包括於形成第二閘極之前,於半導體層上形成一層 穿隧介電層。 0 依照本發明實施例所述之非揮發性記憶體的製造方 法’更包括於形成第三電荷陷入層與第四電荷陷入層之 刖’於弟一閘極兩側形成一層介電層。 依照本發明實施例所述之非揮發性記憶體的製造方 法,其中半導體層的形成方法包括磊晶橫向成長法 (Epitaxial Lateral Overgrowth)。 依知本發明實施例所述之非揮發性記憶體的製造方 法,其中於凹陷中依序形成絕緣層與底導體層,填滿凹陷 的方法例如是先於基底上依序形成一層絕緣材料層與一層 導體材料層,然後以基底為終止層,利用化學機械研磨法 移除部分絕緣材料層與導體材料層。 依照本發明實施例所述之非揮發性記憶體的製造方 法,其中第一電荷陷入層、第二電荷陷入層、第三電荷陷 入層與第四電荷陷入層的材質包括奈米結晶、钽氧化層、 欽酸錄層或給氧化層。 依照本發明實施例所述之非揮發性記憶體的製造方 法,其中第一電荷陷入層、第二電荷陷入層、第三電荷陷 P950I62 22261twf.doc/n 入層與第四電荷陷人層的材質包括氮化石夕。 亿…、本^明Μ知例所述之非揮發性記憶體的製 法思其中第—電荷陷人層、第二電荷陷人層、第^ ^與第四電荷陷人層的材質包括氧化石 化^ (ΟΝΟ)複合材料。 /孔化矽 依照本發明實施贿述之轉發性記憶體的製造方 法’更包括於第二單元上形成—層頂導體層,電性連接 二閘極。 本發明提出—種非揮發性記憶體㈣作方法,適用於 之記憶胞’記憶胞包括:第一單元,包括了 w甲。、弟一電荷陷入層與第二電荷陷入層,其中第一 入層ί第二電荷陷人層設置於第—閘極之兩侧;半 住第—單元;第二單元’設置於半導體層上, L抓ν \θ,與第—單元鏡像對稱,第二單元包 °又f於半?體層上之第二閘極 ’以及設置於第二閘極兩 貝一電荷陷入層與第四電荷陷入層;以及源極區與汲 ^二單置於第二單元兩側之半導體層中’用以作為 早兀/、第二單元共用之源極區與汲極區,其中,此操 作方法包括: Y。'化操作時,於第一閘極施加第一電壓,源極 區万&力π第二雷厭 四電壓,;中ίΤ區施加第三電壓’第二間極施加第 電壓與第四電ί::壓大於第二電壓:第二電壓大於第三 η ^使電荷進入第一電荷陷入層。 依知、本發明實施例所述之非揮發性記憶體的操作方 1338365 P950162 22261 twf.doc/n 法,其中進行程式化操__包括通電子仰醜! Hot Electron)注入模式。 其中第一電壓介於5〜10伏特⑽,第 〜6伏特之間’第三電壓與第四電壓為〇伏特。丨、 依照本發明實施崎述之麵發性錢體 法,更包括於進行抹除操作時:於第—閘極施加第五^ 源極區施加第六電壓,汲極區施加第七電壓,' 施加第八電壓’其中第五電壓小於第六電壓、第夂= 第八電壓’第六電壓高於第七電㈣“電壓=第 一電荷陷入層中的電荷。 ^钚除弟 =¾本發明實_所述之非料性記憶體的操作方 式’。八進仃抹除操作的機制包括價帶-導帶熱電洞注入模 去發明實施例所述之非揮發性記憶體的摔作方 法’其中第五電壓為負電壓,第六電壓為正錢吨作方 法,所述之非揮發性_的操作方 〜外伏特^ 特之間,第六f壓介於 ..Λ , 第七電壓與第八電壓為0伏特。 依知本發明實施例所述 法’更包括於進行嘈如品仇η±,竿七性°己U館的麵作方 源極區施加第十^ 7^ % .於第—閘極施加第九電度, 極施加第十區施加第十-電壓,於第二問 層的儲存狀態,。4 %壓,以讀取第1荷陷入 12 1338365 P950162 22261 twf.doc/n 依照本發明實施例所述之非揮發性記憶體的操作方 法,其中進行讀取操作的機制包括逆向讀取(reverse 模式。 依照本發明實施例所述之非揮發性記憶體的操作方 法,其中第九電壓介於3〜5伏特之間,第十一電壓介於i 〜2伏特之間,第十電壓與第十二電壓為〇伏特。The highest (4) oxygen cut thickness of the composite material is less than 2 nm, for example, L5 to 2 nm. U The present invention proposes a method of manufacturing a non-volatile memory by first providing a substrate. An insulating layer and a layer are sequentially formed on the substrate. A first dielectric layer is then formed on the substrate, the first dielectric layer having a P950162 2226 ltwf.doc/n opening bare exposed bottom conductor layer. Next, in the first-cell, the -cell includes: a first charge trapping layer and a second electrical sheet are respectively formed on the first-opening 4 sidewall; and the first-layer layer and electrically insulating the bottom conductor layer. Forming a person on the substrate ● The second dielectric layer has a second opening, exposing the first-single it. A third dielectric layer is formed in the opening to cover the first unit. A semiconductor layer is formed in the ^, covering the first cell, and the lateral dimension of the semiconductor -: element. Next, in the semi-conducting; = into the first - early 兀 'di two units including: the second gate, formed on the 'and the third charge trapped layer and the fourth charge trapped layer, two second Ming t The doping method is formed on both sides of the semiconductor layer, and the manufacturing method of the non-volatile memory described in the right example is in the recess', and the insulating layer and the bottom conductor layer are sequentially formed, and the method is performed. The manufacturing method of the non-volatile memory 4 /, the method of forming the younger brother is as follows: the charge is trapped in the material layer before the opening, and then the partial charge trapping material layer f is removed, and the wall forms a first charge trap. The layer and the second charge are trapped by: and the bottom conductor layer. Then, the opening is filled with the first two connection method, and the manufacturing method of the non-volatile memory described in (4) is electrically non-volatile in the first-charge trapping layer and the ... The manufacture of the It body 1338365 P950162 22261 twf.doc/n method The second unit is formed by, for example, forming a second gate on the substrate and then sequentially forming a layer of charge trapping material on the substrate. Then, a portion of the electrical phase human material layer is removed, and a third charge trapping layer and a fourth charge trapping layer are formed on both sides of the second gate, respectively. The method for fabricating a non-volatile memory according to an embodiment of the invention further includes forming a tunneling dielectric layer on the semiconductor layer before forming the second gate. The manufacturing method of the non-volatile memory according to the embodiment of the present invention further includes forming a dielectric layer on both sides of the gate of the third charge trapping layer and the fourth charge trapping layer. A method of fabricating a non-volatile memory according to an embodiment of the invention, wherein the method of forming the semiconductor layer comprises an Epitaxial Lateral Overgrowth method. The method for manufacturing a non-volatile memory according to the embodiment of the present invention, wherein the insulating layer and the bottom conductor layer are sequentially formed in the recess, and the method of filling the recess is, for example, sequentially forming a layer of insulating material on the substrate. With a layer of conductive material and then a substrate as a termination layer, a portion of the insulating material layer and the conductive material layer are removed by chemical mechanical polishing. The method for manufacturing a non-volatile memory according to the embodiment of the present invention, wherein the materials of the first charge trapping layer, the second charge trapping layer, the third charge trapping layer and the fourth charge trapping layer comprise nanocrystals, germanium oxide Layer, acid layer or oxide layer. A method of manufacturing a non-volatile memory according to an embodiment of the invention, wherein the first charge trapping layer, the second charge trapping layer, the third charge trapping P950I62 22261 twf.doc/n and the fourth charge trapping layer The material includes nitrite. In the case of the non-volatile memory described in the example, the material of the first charge trap layer, the second charge trap layer, and the second and fourth charge trap layers includes oxidized petrochemical ^ (ΟΝΟ) Composite. The method for manufacturing a transmissive memory according to the present invention further comprises forming a layer-top conductor layer on the second unit and electrically connecting the two gates. The invention proposes a non-volatile memory (four) method, which is suitable for the memory cell. The memory cell comprises: a first unit comprising w-A. a first charge layer and a second charge trap layer, wherein the first input layer ί second charge trap layer is disposed on both sides of the first gate; the half-cell-unit; the second unit is disposed on the semiconductor layer , L scratch ν \θ, mirror symmetry with the first unit, the second unit package ° f and half? a second gate on the bulk layer and a second charge-trap layer and a fourth charge trapping layer disposed on the second gate; and a source region and a semiconductor layer disposed on both sides of the second unit The source region and the bungee region shared by the early 兀/, the second unit, wherein the operation method includes: Y. During the operation, the first voltage is applied to the first gate, the source region 10,000 & force π the second lightning is four voltages; the third voltage is applied to the middle region, and the second voltage is applied to the second voltage. ί:: The voltage is greater than the second voltage: the second voltage is greater than the third η ^ to cause the charge to enter the first charge trapping layer. The operating method of the non-volatile memory according to the embodiment of the present invention is 1338365 P950162 22261 twf.doc/n, wherein the stylized operation __including the electronic ugly! Hot Electron injection mode. The first voltage is between 5 and 10 volts (10), and between the first and sixth volts, the third voltage and the fourth voltage are 〇 volts.丨 实施 实施 实施 实施 实施 实施 实施 实施 实施 , 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照 依照'Applying an eighth voltage' wherein the fifth voltage is less than the sixth voltage, the third voltage is the eighth voltage, and the sixth voltage is higher than the seventh voltage (four) "voltage = the charge in the first charge trapping layer. ^钚除弟=3⁄4本The invention relates to the operation mode of the non-material memory. The mechanism of the occlusion device includes a valence band-guide band thermoelectric hole injection mold to the non-volatile memory method described in the embodiment. 'The fifth voltage is a negative voltage, the sixth voltage is a positive money ton method, the non-volatile _ the operation side ~ the outer volts between the special, the sixth f voltage is between .. Λ, the seventh voltage And the eighth voltage is 0 volts. The method according to the embodiment of the present invention is further included in the process of performing the tenth ^ 7 ^ % of the surface source region of the U 性 ° Applying a ninth degree of electricity to the first gate, applying a tenth-voltage to the tenth region, and storing the second layer, 4% pressure to read the first charge trap 12 1338365 P950162 22261 twf.doc/n The method of operating a non-volatile memory according to an embodiment of the present invention, wherein the mechanism for performing the read operation includes reverse reading (reverse A method for operating a non-volatile memory according to an embodiment of the invention, wherein the ninth voltage is between 3 and 5 volts, the eleventh voltage is between i and 2 volts, and the tenth voltage is The twelve voltages are volts.
依照本發明實施例所述之非揮發性記憶體的操作方 ^,更包括:進行程式化操作時,於第一閘極施加第一電 壓,源極區施加第三電壓,汲極區施加第二電壓,第二閘 極施加第四電壓,利用通道熱電子注人模式,使電荷進入 第二電荷陷入層; —進行抹除操作時,於第一閘極施加第五電壓,源極區 施加第七電壓’汲極區施加第六電壓,於第二閘極施加第 八電壓’利用價帶-導帶熱電洞注人模式,抹除第二電荷陷 入層中的電荷;以及The operating method of the non-volatile memory according to the embodiment of the invention further includes: applying a first voltage to the first gate, applying a third voltage to the source region, and applying the first region to the drain region during the stylizing operation. Two voltages, the second gate applies a fourth voltage, and the channel is used to enter the second charge trapping layer by using the channel hot electron injection mode; - when the erase operation is performed, the fifth voltage is applied to the first gate, and the source region is applied a seventh voltage 'applying a sixth voltage in the drain region and an eighth voltage applied to the second gate' utilizes a valence band-guide band thermoelectric hole injection mode to erase the charge in the second charge trapping layer;
^進行讀取操作時,於第一閘極施加第九電壓,源極區 =加第十—電壓,汲極區施加第十電壓,於第二閘極施加 ^二電壓,以逆向讀取的方式讀取第二電荷陷入層中 儲存狀態。 、依照本發明實施例所述之非揮發性記憶體的操作方 更包括:進行程式化操作時,於第一閘極施加第四電 墼,源極區施加第二電壓,汲極區施加第三電壓,於第二 閘,施加第一電壓,利用通道熱電子注入模式,使電荷進 入第三電荷陷入層; 13 1338365 P950162 22261twf.d〇c/] ^進行抹除操作時,於第一閘極施加第八電壓,源極區 1第六電麼’汲極區施加第七電壓,於第二閘極施加第 龟t利用彳貝帶_導帶熱電洞注入模式,抹除第三荷陷入 層中的電荷;以及 〇進行讀取操作時,於第一閘極施加第十二電壓,源極 加第十電壓,沒極區施加第^電壓,於第二閘極施 加第九電壓,以逆向讀取的方式讀取第三電荷陷入層中的 儲存狀態。 曰 依照本發明實施例所述之非揮發性記憶體的操作方 =,更包括:進行程式化操作時,於第一閘極施加第四電 壓’源極區施加第三電壓,汲極區施加第二電壓,於第二 問極施加第一電壓,利用通道熱電子注入模式,使電荷進 入第四電荷陷入層; 進行抹除操作時,於第一閘極施加第八電壓,源極區 施加第七電壓,汲極區施加第六電壓,於第二閘極施加第 五電壓’利用價帶-導帶熱電洞注入模式,將電洞注入於抹 除第四電荷陷入層中的電荷;以及 進行讀取操作時,於第一閘極施加第十二電壓,源極 區化加第十一電麼,沒極區施加第十電壓,於第二閉極施^ When performing a read operation, a ninth voltage is applied to the first gate, a source region = plus a tenth voltage, a tenth voltage is applied to the drain region, and a voltage is applied to the second gate for reverse reading. The mode reads the storage state in the second charge trapping layer. The operation of the non-volatile memory according to the embodiment of the present invention further includes: applying a fourth power to the first gate, applying a second voltage to the source region, and applying the second region to the drain region during the stylization operation. Three voltages, at the second gate, applying a first voltage, using a channel hot electron injection mode to cause charge to enter the third charge trapping layer; 13 1338365 P950162 22261twf.d〇c/] ^ when performing the erase operation, at the first gate The eighth voltage is applied to the pole, the sixth voltage of the source region 1 is applied, the seventh voltage is applied to the drain region, the first turtle is applied to the second gate, and the hot hole injection mode is used to remove the third charge. The charge in the layer; and when the read operation is performed, the twelfth voltage is applied to the first gate, the tenth voltage is applied to the source, the voltage is applied to the non-polar region, and the ninth voltage is applied to the second gate to The reverse reading mode reads the storage state in the third charge trapping layer. The operating side of the non-volatile memory according to the embodiment of the invention further includes: applying a fourth voltage to the first gate during the staging operation, applying a third voltage to the source region, and applying the drain region a second voltage, applying a first voltage to the second polarity, using a channel hot electron injection mode to cause the charge to enter the fourth charge trapping layer; performing an erase operation, applying an eighth voltage to the first gate, and applying the source region a seventh voltage, a sixth voltage is applied to the drain region, and a fifth voltage is applied to the second gate. The charge is implanted into the fourth charge trapping layer by using a valence band-guide band thermal hole injection mode; When performing a read operation, the twelfth voltage is applied to the first gate, the source region is increased by the eleventh electric power, the tenth voltage is applied to the non-polar region, and the second closed electrode is applied.
加第九電壓’以逆向讀取的方式讀取第四電荷陷入層中的 儲存狀態。 B 本發明提出一種電路系統’包括非揮發性記憶體以及 電路。非揮發性記憶體包括多個記憶胞、多數條字元線與 多數條位元線。記憶胞排列成一行/列陣列,各記憶胞包括 14 1338365 P950I62 22261twf.doc/n 一第一單元 早導體層 第二 __ 單元與一摻雜區。第— 單元包括有第-閘極,以及設置於第一間極兩側之第 荷陷入層與第二電荷陷入層;半導體層設置於基底上 „元’且半導體層的橫向尺寸大於第一 二第,單元設置於半導體層上,以半導體層為對稱 ,,與r衫鏡像對稱’第二單元包括設置於半導體層 之弟-閘極,以及設置於第二閉極兩側之一第三 陷入層與-第四電荷陷人層。摻㈣設置 兩 單元與第二單元共用之源極‘ 3 Γ線,包^數條底字元線,在行方向上平行排列, ί的第1極,以及多數條頂字元 線在仃方向上平行排列,連接同—行 =多數條位元線’在列方向上平行排列,= =之=錢蘭摻雜區。電㈣祕至非揮發性記作 列解這些位元線之行解碼11,這些字元線之 -資料:二及t接至打解碼器之—資料輸入結構’其中 中。、…該㈣輸人結構儲存於該非揮發性記憶體 入芦依;本;!實施例所述之電路系統’其”-電荷陷 θ弟一電何陷入層、第二μ 層的材質包括;^ ν — 層與第四電荷陷入 或給氧化層 日日㈣噴购1)、12氧化層、鈦酸錄層 入層依Ϊ本ϋΓΓ述之電路系統,其中第—電荷陷 弟-电何陷入層、第三電荷陷入層與第四電荷陷入 15 1338365 P950162 22261 twf.doc/n 層的材質包括氣化石夕。 依照本發明實施例所述之電路系統,其中第一電荷陷 入層、第二電荷陷入層、第三電荷陷入層與第四電荷陷入 層的材質包括氧化矽/氮化矽/氧化矽(0N0)複合材料。 依照本發明實施例所述之電路系統,其中半導體層是 以 *&日日 & 向成長法(Epitaxial Lateral Overgrowth)所形成 的。The ninth voltage is applied to read the storage state in the fourth charge trapping layer in a reverse reading manner. B The present invention proposes a circuit system 'comprising non-volatile memory and circuitry. The non-volatile memory includes a plurality of memory cells, a plurality of word lines, and a plurality of bit lines. The memory cells are arranged in a row/column array, and each memory cell includes 14 1338365 P950I62 22261twf.doc/n a first unit early conductor layer second __ unit and a doped region. The first unit includes a first gate, and a first charge trapping layer and a second charge trapping layer disposed on both sides of the first interlayer; the semiconductor layer is disposed on the substrate and the lateral dimension of the semiconductor layer is greater than the first two First, the unit is disposed on the semiconductor layer and is symmetric with the semiconductor layer, and is mirror-symmetrical with the r-shirt. The second unit includes a gate-gate disposed on the semiconductor layer, and a third trapped on one of the two sides of the second closed-pole. Layer and - fourth charge trapping layer. Doping (d) set the source '3 Γ line shared by the two units and the second unit, including a number of bottom word lines, arranged in parallel in the row direction, ί of the first pole, and Most of the top word lines are arranged in parallel in the 仃 direction, and the same line = most = bit lines are arranged in parallel in the column direction, = = = Chanlan doped area. Electricity (4) secret to non-volatile record The rows of these bit lines are decoded 11 , and the data of these word lines are: 2 and t are connected to the decoder - the data input structure is in which ..., the (4) input structure is stored in the non-volatile memory Into the reed; this; the circuit system described in the embodiment 'its' - electricity The material of the second layer is included; ^ ν — the layer and the fourth charge are trapped or the oxide layer is sprayed daily (4), and the 12 oxide layer and the titanate layer are layered. The circuit system described herein, in which the first-charge trapping-electrical trapping layer, the third charge trapping layer and the fourth charge trapping layer 1 1338365 P950162 22261 twf.doc/n layer material includes gas fossil eve. According to the circuit system of the embodiment of the invention, the material of the first charge trapping layer, the second charge trapping layer, the third charge trapping layer and the fourth charge trapping layer comprises yttrium oxide/tantalum nitride/yttria (0N0). Composite material. A circuit system according to an embodiment of the invention, wherein the semiconductor layer is formed by *& Epitaxial Lateral Overgrowth.
依照本發明實施例所述之電路系統,其中,同—行的 這些記憶胞以鏡像對稱的方式鄰接設置。 ^依照本發明實施例所述之電路系統,其中,以鏡像對 稱的方式配置的相鄰二記憶胞,共用摻雜區。 本發明利用自行對準的方式於閘極兩側形成了電荷陷 入層’並且以半導體層中之4參雜區作為上下兩個單元此用 的源極/祕區,形成—個具有高積集度的記憶胞,在^一 g胞中即可儲存多個位元的資料,符合現今高積集度的A circuit system according to an embodiment of the invention, wherein the memory cells of the same line are arranged adjacently in a mirror symmetrical manner. The circuit system according to the embodiment of the invention, wherein adjacent two memory cells configured in a mirror-symmetrical manner share a doped region. The present invention forms a charge trapping layer on both sides of the gate by self-alignment and uses the four doping regions in the semiconductor layer as the source/secret region for the upper and lower cells, forming a high accumulation. The memory of the memory cell can store multiple bits of data in a cell, which is consistent with the current high accumulation.
此外 崎此航憶朗料㈣設置於閘 :側’因此’藉由在源極區、祕區 ==的電壓’可以报容易地程式化、抹除玆 提高其可紐與記㈣的表2相干__ ’可以 易懂為述和其他目的、特徵和優點能更明顯 下。文特舉貝施例’並配合所附圖式,作詳細說明如 16 1338365 P950162 22261twf.doc/n 【實施方式】 圖1A是繪示本發明一實施例之一種非揮發性記憶體 的結構剖面圖。圖1Β是繪示本發明另一實施例之一種非 揮發性記憶體的結構剖面圖。圖2是繪示本發明一實施例 之一種非揮發性記憶體的結構上視圖。 凊參照圖1Α與圖1Β,先以單一記憶胞Mc來說明本 發明提出之非揮發性記憶體。記憶胞Mc設置於基底1〇〇 上,由半導體層140、第一單元12〇、第二單元16〇與摻雜 區165所組成。 凊苓照圖1A,基底100例如是矽基底。第一單元12〇 包含^第一閘極130,以及設置於第—閘極13〇兩側的第 電荷陷入層122a與第二電荷陷入層122b。其中,第一 閘極〗30例如是摻雜多晶矽,而第一電荷陷入層】與第 —電荷陷入層122b的材質例如是氮化矽,或是氧化矽/氮 =矽、氧化矽/氮化矽、氧化矽(〇N〇,〇s〇)等的複合材料。 田然,第一電荷陷入層122a與第二電荷陷入層122b的材 質並不限於氮化⑦,也可以是其他能夠使電荷陷入於其中 之材貝,例如是奈米結晶(nan〇crysta丨)、鈕氧化層、鈦酸勰 層與铪氧化層等。 第—閘極130與第一電荷陷入層122a與第二電荷陷入 層122b之間,還可以設置有一層介 5。 的材質例如是氧切。 電詹 第—單元120例如是設置於基底1〇〇中,第—單元12〇 之第一問極130之間例如是設置有保護層ι17,將第一閘 17 P950162 22261twf.doc/n 極no與基底100隔離開來。在一實施例中,第一電荷陷 入層122a、第二電荷陷入層122b與基底100之間也可以 設置有一層保護層119,以避免電荷陷入層中所捕捉的電 荷進入基底100中。保護層117、保護層119的材質例如 是氧化石夕。 請參照圖1B,在另一實施例中,第一單元12〇還可以 是設置於基底100上之介電層115中。介電層115的材質 例如是氧化石夕。 請參照圖1A與圖1B,半導體層設置於基底1〇〇 上,覆蓋住第一單元120,其橫向尺寸大於第一單元12〇 的橫向尺寸。半導體層140例如是以磊晶橫向成長法 (Epitaxial Lateral Overgrowth)所形成的。第一單元 12〇 與 半導體層140之間還設置有一層穿隧介電層135,即設置 於半導體層140與第一閘極130之間。穿随介電層135可 以是單層或是多層的結構,其材質例如是氧化矽或是氧化 矽遺化矽、氧化矽/氮化矽、氧化矽(0N0,0S0)等的複合 材料,在複合材料最底層的氧化矽厚度為小於2奈米,在 一實施例中可以為約0.5至2奈米,在另一實施例中可以 小於1.5奈米,在複合材料中間層的氮化矽、氧化矽厚度 為小於2奈米,在一實施例中可以為約丨至2奈米,而在 複合材料最上層的氧化矽厚度為小於2奈米,在一實施例 中可以為約1.5至2奈米。 第二單元160設置於半導體層14〇上,以半導體層14〇 為對稱輪,與第-單^ 12G鏡像對稱。第二單元16〇曰包括 P950162 22261 twf.d〇c/n 了設置於半導體層140上的第二閘極145,以及設置於第 二閘極14 5兩側之第三電荷陷入層丨5 5 a與第四電荷陷入層 155b。 第二閘極145的材質例如是摻雜多晶矽、金屬矽化物 等導體材料。第三電荷陷入層155a與第四電荷陷入層155b 的材質例如是氮化矽、氧化矽/氮化矽、氧化矽/氮化矽氧 化矽(ΟΝΟ)複合材料,或是其他能夠使電荷陷入於其中之 材質,例如奈米結晶、氮氧化矽、氧化鈕、鈇酸鳃或 姶等。 請參照圖1Β,在另一實施例中,半導體層14〇可以是 叹置於介電層132中,將相鄰記憶胞之半導體層 隔絕開來。第二單元160兩側可以是設置有介電層163, 以便於後續字it線的形成。介電層132、介電層163的材 質例如是氧化石夕之類的介電材料。 …一請參照圖1A’第二單元160之第三電荷陷入層155&' 第一閘極145、第四電街陷入層155b底部與半導體層140 ,設置有一層穿隧介電層143。穿隧介電層143S可以 =單層或是多層的結構,其材質例如是氧切或是氧化石夕/ 二化矽、氧化石夕/氮化石夕、氧化石夕(〇N〇,〇s〇)等的 =^在複合材料最底層的氧化矽厚度為小於2奈米,在一 二知例中可以為約G.5至2奈米,在另—實施例中可以小 / 1.5奈米,在複合材料中間層的氮化石夕、氧化石夕厚度為 2奈米’在一實施例中可以為約…奈米,而在複 °材料最上層的氧化料度為小於2奈米,在―實施例中 1338365 P950162 22261twf.doc/n I以為約1.5至2奈来。且第二閘極145兩側壁與第三電 何陷入層155a、第四電荷陷人層155b之間例如是設置有 —層介電層153,介電層153的材質例如是氡化矽。 請參照圖1B ’在另—實施例中,穿隨介電層143例如 是設置於第二閘極145與半導體層14〇之間。而第三電荷 陷入層155a、第四電荷陷入層155b的側壁及底部,與^ 二閘極145、半導體層14〇之間,則設置有介電層153。呓 憶體的操作過程中,電荷可以經由介電層153 (尤其是電 荷陷入層IMa'IHb下方的部分)與穿隨介電層143 出電荷陷入層155a、15 5b。 π摻雜區165設置於半導體層14〇兩側,也就是位於第 =單=160與第一單元12〇兩側之半導體層14〇中,作為 第一單το 120與第二單元160共用之源極/汲極區。在—實 施例中,基底1〇〇例如是ρ型基底,摻雜區165例如是ς 雜有碟或石申的Ν型重摻雜區。 少 一亡述第一電荷陷入層ma、第二電荷陷入層mb、第 三電荷陷入層155a與第四電荷陷入層155b,分別可以儲 存資料。也就是說,在一個記憶胞1^(:之中,便可以儲疒 多個位元的資料。 子 請參照圖2,多個記憶胞MC在基底1〇〇上可以是排 列成行/列陣列。同-行(X方向)上的這些記憶胞Mc以 鏡像對稱的方式鄰接設置。這些相鄰二記憶胞MC可 共用摻雜區165。 在這個記憶胞陣列之中,還包括有多條底字元線 20 1338365 P950162 22261twf.doc/n BWU、BWL2、BWL3,多條頂字元線 TWU、TWL2、 TWL3,以及多條位元線BL1、BL2、BL3。 各底字元線BWL1、BWL2、BWL3連接同一行(χ 方向)之記憶胞MC的第一閘極130;各頂字元線丁^^以、 TWL2、TWL3連接同一行(X方向)之記憶胞MC的第二 閘極145 ;位元線BL1、BL2、BL3例如是藉由插夷175 則連接同一列(Y方向)之記憶胞MC的摻雜區165。In addition, this airline memory (4) is set on the gate: side 'so 'by the voltage in the source zone, the secret zone ==' can be easily stylized, erased, and improved by the table 2 (4) Coherent __ 'can be easily understood and other purposes, features and advantages can be more obvious. FIG. 1A is a structural cross-section of a non-volatile memory according to an embodiment of the present invention. FIG. 1A is a cross-sectional view of a non-volatile memory according to an embodiment of the present invention. Figure. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A is a cross-sectional view showing the structure of a non-volatile memory according to another embodiment of the present invention. Fig. 2 is a structural top view showing a non-volatile memory according to an embodiment of the present invention. Referring to Fig. 1A and Fig. 1A, the non-volatile memory proposed by the present invention will be described first with a single memory cell Mc. The memory cell Mc is disposed on the substrate 1B, and is composed of a semiconductor layer 140, a first cell 12A, a second cell 16A, and a doped region 165. Referring to Figure 1A, substrate 100 is, for example, a germanium substrate. The first unit 12A includes a first gate 130, and a first charge trapping layer 122a and a second charge trapping layer 122b disposed on both sides of the first gate 13A. Wherein, the first gate 30 30 is, for example, doped polysilicon, and the material of the first charge trapping layer and the first charge trapping layer 122b is, for example, tantalum nitride, or yttrium oxide/nitrogen=矽, yttrium oxide/nitriding. A composite material such as ruthenium or osmium oxide (〇N〇, 〇s〇). Tian Ran, the material of the first charge trapping layer 122a and the second charge trapping layer 122b is not limited to the nitriding 7, and may be other materials capable of trapping charges therein, such as nanocrystals (nan〇crysta丨). , button oxide layer, barium titanate layer and tantalum oxide layer. The first gate 130 is interposed between the first charge trapping layer 122a and the second charge trapping layer 122b, and may also be provided with a layer 5. The material is, for example, oxygen cut. For example, the first unit is provided with a protective layer ι17, and the first gate 17 is P950162 22261 twf.doc/n pole no. Isolated from the substrate 100. In an embodiment, a protective layer 119 may also be disposed between the first charge trapping layer 122a, the second charge trapping layer 122b, and the substrate 100 to prevent the charge trapped in the charge trapping layer from entering the substrate 100. The material of the protective layer 117 and the protective layer 119 is, for example, oxidized stone. Referring to FIG. 1B, in another embodiment, the first unit 12A may also be disposed in the dielectric layer 115 on the substrate 100. The material of the dielectric layer 115 is, for example, oxidized stone. Referring to FIG. 1A and FIG. 1B, a semiconductor layer is disposed on the substrate 1A to cover the first unit 120, and its lateral dimension is larger than the lateral dimension of the first unit 12A. The semiconductor layer 140 is formed, for example, by an Epitaxial Lateral Overgrowth method. A tunneling dielectric layer 135 is disposed between the first unit 12A and the semiconductor layer 140, that is, between the semiconductor layer 140 and the first gate 130. The dielectric layer 135 may be a single layer or a multilayer structure, and the material thereof is, for example, a composite material of yttrium oxide or yttrium oxide yttrium oxide, yttrium oxide/tantalum nitride, yttrium oxide (0N0, 0S0), etc. The bottommost cerium oxide layer of the composite material has a thickness of less than 2 nanometers, and may be about 0.5 to 2 nanometers in one embodiment, and less than 1.5 nanometers in another embodiment, tantalum nitride in the intermediate layer of the composite material, The thickness of the cerium oxide is less than 2 nanometers, in one embodiment from about 丨 to 2 nanometers, and the thickness of the cerium oxide in the uppermost layer of the composite is less than 2 nanometers, and in one embodiment may be about 1.5 to 2 Nano. The second unit 160 is disposed on the semiconductor layer 14A, and has a semiconductor layer 14〇 as a symmetrical wheel, which is mirror-symmetrical to the first-only 12G image. The second unit 16A includes a second gate 145 disposed on the semiconductor layer 140, and a third charge trapping layer 丨5 5 disposed on opposite sides of the second gate 145. a and the fourth charge trapping layer 155b. The material of the second gate 145 is, for example, a conductive material such as doped polysilicon or metal germanide. The materials of the third charge trapping layer 155a and the fourth charge trapping layer 155b are, for example, tantalum nitride, hafnium oxide/tantalum nitride, hafnium oxide/tantalum nitride tantalum oxide (yttrium) composite material, or other materials capable of trapping charges. Among them, materials such as nanocrystals, bismuth oxynitride, oxidation knobs, strontium ruthenate or strontium. Referring to FIG. 1A, in another embodiment, the semiconductor layer 14 may be slid in the dielectric layer 132 to isolate the semiconductor layers of adjacent memory cells. A dielectric layer 163 may be disposed on both sides of the second unit 160 to facilitate formation of a subsequent word line. The material of the dielectric layer 132 and the dielectric layer 163 is, for example, a dielectric material such as oxidized stone. Referring to FIG. 1A', the third charge trapping layer 155 of the second cell 160, the first gate 145, the fourth electrical street trapping layer 155b, and the semiconductor layer 140 are provided with a tunneling dielectric layer 143. The tunneling dielectric layer 143S may be a single layer or a multilayer structure, and the material thereof is, for example, oxygen cutting or oxidized stone cerium/anthraquinone, oxidized stone cerium/nitridin cerium, oxidized stone cerium (〇N〇, 〇s 〇), etc. = ^ The thickness of the yttrium oxide at the bottom of the composite material is less than 2 nm, which may be about G. 5 to 2 nm in one or two examples, and may be small / 1.5 nm in another embodiment. In the intermediate layer of the composite material, the thickness of the oxidized stone is 2 nm. In one embodiment, it may be about ... nanometer, and in the uppermost layer of the composite material, the oxidation degree is less than 2 nm. In the embodiment, 1338365 P950162 22261twf.doc/n I is thought to be about 1.5 to 2 nanometers. For example, a dielectric layer 153 is disposed between the sidewalls of the second gate 145 and the third electrical drain layer 155a and the fourth charge trap layer 155b. The material of the dielectric layer 153 is, for example, germanium telluride. Referring to FIG. 1B', in another embodiment, the pass-through dielectric layer 143 is disposed between the second gate 145 and the semiconductor layer 14A, for example. The dielectric layer 153 is provided between the sidewalls and the bottom of the third charge trapping layer 155a and the fourth charge trapping layer 155b, and between the gate 145 and the semiconductor layer 14A. During the operation of the memory, the charge may pass through the dielectric layer 153 (especially the portion under the charge trapping layer IMa'IHb) and the pass-through dielectric layer 143 to discharge the charge trapping layers 155a, 15b. The π-doped region 165 is disposed on both sides of the semiconductor layer 14 , that is, in the semiconductor layer 14 第 on the sides of the first unit=160 and the first unit 12 , and is shared by the first unit τ 120 and the second unit 160 . Source/bungee area. In the embodiment, the substrate 1 is, for example, a p-type substrate, and the doped region 165 is, for example, a doped type heavily doped region doped with a dish or a stone. The first charge trapping layer ma, the second charge trapping layer mb, the third charge trapping layer 155a, and the fourth charge trapping layer 155b may each store data. That is to say, in a memory cell 1^(:, it is possible to store data of a plurality of bits. Referring to FIG. 2, a plurality of memory cells MC may be arranged in a row/column array on the substrate 1〇〇. These memory cells Mc in the same-line (X direction) are adjacently arranged in a mirror symmetrical manner. These adjacent two memory cells MC can share the doped region 165. Among the memory cell arrays, there are also multiple bottoms. Word line 20 1338365 P950162 22261twf.doc/n BWU, BWL2, BWL3, a plurality of top word lines TWU, TWL2, TWL3, and a plurality of bit lines BL1, BL2, BL3. Each bottom word line BWL1, BWL2 BWL3 is connected to the first gate 130 of the memory cell MC of the same row (χ direction); each top word line is connected to the second gate 145 of the memory cell MC of the same row (X direction) by TWL2 and TWL3; The bit lines BL1, BL2, and BL3 are, for example, doped regions 165 in which the memory cells MC of the same column (Y direction) are connected by interpolating 175.
請參照圖1B,在一實施例中,底字元線11〇例如是設 置於與基底100與第一單元120之間,電性連接第一問極 130’且底字元線110與基底1〇〇之間還設置有—層絕緣層 105’使底字元線110與基底1〇0隔離。頂字元線17〇則言^ 置於弟一單元160上,與第二閘極145電性連接。底字元 線110與頂子元線170的材質例如是換雜多晶石夕、銘、銘 合金、金屬矽化物等導體材料。Referring to FIG. 1B , in an embodiment, the bottom word line 11 〇 is disposed between the substrate 100 and the first unit 120 , electrically connected to the first gate 130 ′ and the bottom word line 110 and the substrate 1 . A layer of insulating layer 105' is also disposed between the turns to isolate the bottom word line 110 from the substrate 1〇0. The top word line 17 is placed on the cell 160 and electrically connected to the second gate 145. The material of the bottom character line 110 and the top sub-element 170 is, for example, a conductor material such as a polycrystalline spine, an alloy, a metal alloy or a metal halide.
在本實施例之非揮發性記憶體中,單一記憶胞内具有 四個電荷陷入層,而得以儲存多位元的資料,也就是二兒, 本發明之記憶胞可以在單位面積中儲存更多的資料疋= 於提高元件的積集度相當地有幫助。 这 力,由於冤 .η旧八乂罝於闸桠的兩側,因此 荷陷入層中的電荷不會有互相顿的問題,進 s己憶體的可靠度與電性表現。 本發明提出一種非揮發性記憶體的製造方法。 至圖3G是繪示本發明一實施例之一種 性^咅 製造流程剖關。其中 21 1338365 P950162 22261 twf, doc/n 者^圖^中H’線所繪示出來的製造流程剖面圖。而圖 則疋二著如圖2中Ιΐ-π’線所繪示出來的製造流程剖面圖。 0印參照圖3^1與圖3Α-2,本實施例之方法例如是先 提供基底200,基底200可以是石夕基底,且基底2〇〇中形 成有凹陷203。此凹陷203之形成方法例如是先於基底2〇〇 上形成—層圖案化光阻層(未繪示),然後移除部分基底 2〇〇,之後再移除圖案化光阻層而形成的。 承—接著,依序形成一層絕緣層2〇5與一層底導體層21〇, 覆盍住基底200’並且填滿凹陷2〇3。而後以化學機械研磨 法進行平坦化製程,移除基底2〇〇上的底導體層與絕 緣層205。 繼而,請參照圖3B’於底導體層21〇上形成一層介電 層a215。介電層215的材質例如是氧化矽,其形成方法例 如疋化學氣相沈積法。其後,於介制215中形成開口 2口’裸路出底導體層210。開^ 217例如是利用微影、蝕 刻製程而形成的。 再來’於基底200上依序形成—層電荷陷入材料層221 與層;I電材料層223。電荷陷入材料層221的材質例如 是氛化梦、奈米結晶、錄切、氧心、鈦祕或氧化 給等’能夠阻限電荷的材質,其形成方法例如是化學氣相 沈積法。介電材料層223的材質例如是氧化石夕,其形成方 法例如是化學氣相沈積法。 〜接下去,請參照圖3C ’移除部分介電材料層奶與電 何陷入層221,而於開口 217兩側壁形成電荷陷入層2仏、 22 1338365 P950162 22261 twf.doc/n 222b與介電層225 ’並且裸露出底導體層2I〇。移八 介電材料層223與電荷陷入層221的方法例如是乾式^ 法或是濕式㈣法。紐,㈣σ 217中填滿閘極21 連接底導體層210。形成閘極23〇的方法例如是於基底2㈧ •^形成-層共形的導體層(未繪示),導體層的^質例如 是摻雜多晶矽,然後利用化學機械研磨法等平坦化製程, 移除介電層215上的導體層。閘極23〇與電荷層 222a、222b組成了此記憶胞之第一單元22〇。 曰 繼之,請參照圖3D,於基底200上形成另—層介電屏 232。介電層232的材質例如是氧化矽,其形成方法例:^ 化學氣相沈積法。之後,於介電層232中形成另—個開: 2M ’裸露出第一單元22〇。開口 234的形成方法例如&二 衫钱刻製私。開口 234的橫向尺寸例如是大於第—單元22〇 的橫向尺寸,而裸露出介電層215。 而後’於開口 234中形成一層穿隧介電層235,穿隨 介電層235可以是單層或是多層的結構,其材質例如是氧 化矽或是氧化矽/氮化矽、氧化矽/氮化矽、氧化= (〇NO,〇SO)等的複合材料,其形成方法例如是化學氣相'六 積法’此方法形成的穿隧介電層235具有較佳的薄棋: 質。當然’這一層穿隧介電層235也可以是在形成開口之二 的時候’預留部分介電層232而形成之。 接著’於開口 234中填滿半導體層240。半導體層24〇 的材質例如是矽,其形成方法例如是磊晶橫向成長、去 (Epitaxial Lateral Overgrowth)。 23 1338365 P950162 22261twf.doc/n 然後,請參照圖3E,於基底2〇〇上形成一層 :43與閘極245。介電層243與閘極245的形成方法例如: (序於基底20G上形成介電材料層(未繪示)與間極= ^(未緣示)。然後利用微影钱刻技術,圖案化上述材料 =形成之。介電材料層可以是單層或是多層的結構,^ 材質例如是氧切或是氧切/氮化梦、氧切/氮化石/、 氧化矽(0N0,0S0)等的複合材料,其形成方法例 氣相沈積法;閘極材料層的材質例如是摻料轉 ίΓ:如ί利用化學氣相沈積法形成-層未摻雜多晶碎 2二:Π植入步驟以形成之’或者也可以採用臨場 植入4貝之方式’以化學氣相沈積法形成之。 之後’請參照圖3F,於基底上依 的介電材料層247與—層共形的電荷陷人材料層249 ; 電材料層247可以是單層或是多層的結構 ^ 氧化石夕U氧切/氮切、氧化 、^ 層249的材質例如是奈米結晶、氮化 二广材料如氧化残切、氧化魏化石夕 /乳化夕、乳化鈕、鈦酸鎇或氧化鈴等材 如是化學氣相沈積法。 、八域方細 八=Γί參照圖3G,移除部分電荷陷入材料層249 陷入層放、勝r/=52f的部分1成電荷 盛Λ 電層 問極245與電荷陷 入層 、,且成了此記憶胞之第二單元260。其中, 24 1338365 P950162 22261 twf.d〇c/n 介電層253 (尤其是電荷陷入層255a、⑽下方 與介電層243例如是作為第二單元遍之穿随介雷:了 操作的時候,電荷會經由這些介電層而穿:在 層255a、255b。 廷出电何陷入In the non-volatile memory of the embodiment, the single memory cell has four charge trapping layers, and the multi-bit data is stored, that is, the two memory cells of the present invention can store more in a unit area. The data 疋 = is quite helpful in improving the accumulation of components. This force, because the old gossip on both sides of the gate, so the charge trapped in the layer will not have mutual problems, the reliability and electrical performance of the memory. The present invention provides a method of manufacturing a non-volatile memory. FIG. 3G is a cross-sectional view showing a manufacturing process according to an embodiment of the present invention. Among them, 21 1338365 P950162 22261 twf, doc/n is a cross-sectional view of the manufacturing process depicted by the H' line. The plan is a cross-sectional view of the manufacturing process as depicted by the Ιΐ-π' line in Figure 2. Referring to Fig. 3^1 and Fig. 3Α-2, the method of the present embodiment is, for example, first providing a substrate 200, the substrate 200 may be a stone substrate, and a recess 203 is formed in the substrate 2〇〇. The recess 203 is formed by, for example, forming a layer patterned photoresist layer (not shown) on the substrate 2, then removing a portion of the substrate 2, and then removing the patterned photoresist layer. . Next, an insulating layer 2〇5 and a bottom conductor layer 21〇 are sequentially formed to cover the substrate 200' and fill the recess 2〇3. Then, a planarization process is performed by a chemical mechanical polishing method to remove the bottom conductor layer and the insulating layer 205 on the substrate 2. Then, a dielectric layer a215 is formed on the bottom conductor layer 21A with reference to Fig. 3B'. The material of the dielectric layer 215 is, for example, ruthenium oxide, and its formation method is, for example, ruthenium chemical vapor deposition. Thereafter, an opening 2 port' bare bottom conductor layer 210 is formed in the dielectric 215. The opening 217 is formed, for example, by a lithography or etching process. Further, a layer of charge trapping material layer 221 and a layer are formed on the substrate 200; an I electrical material layer 223. The material of the charge trapping material layer 221 is, for example, a material which is capable of blocking a charge, such as a scented dream, a nanocrystal, a recording, an oxygen core, a titanium, or an oxidizing, and is formed by a chemical vapor deposition method. The material of the dielectric material layer 223 is, for example, oxidized stone, and the method of forming it is, for example, a chemical vapor deposition method. ~ Next, please refer to FIG. 3C 'Removing part of the dielectric material layer milk and electricity into the layer 221, and forming a charge trapping layer on both sidewalls of the opening 217 2, 22 1338365 P950162 22261 twf.doc/n 222b and dielectric Layer 225' and bare bottom conductor layer 2I〇. The method of shifting the dielectric material layer 223 and the charge trapping layer 221 is, for example, a dry method or a wet method. New, (4) σ 217 fills the gate 21 to connect the bottom conductor layer 210. The method of forming the gate 23〇 is, for example, a substrate (2) forming a layer-conformed conductor layer (not shown), and the conductor layer is, for example, doped polysilicon, and then planarized by a chemical mechanical polishing method or the like. The conductor layer on the dielectric layer 215 is removed. The gate 23 〇 and the charge layers 222a, 222b constitute the first unit 22 of the memory cell. Next, referring to FIG. 3D, another layer of dielectric screen 232 is formed on the substrate 200. The material of the dielectric layer 232 is, for example, ruthenium oxide, and a method of forming the same is: chemical vapor deposition. Thereafter, another opening is formed in the dielectric layer 232: 2M' exposes the first unit 22A. The method of forming the opening 234 is, for example, & The lateral dimension of the opening 234 is, for example, greater than the lateral dimension of the first cell 22, while the dielectric layer 215 is exposed. Then, a tunneling dielectric layer 235 is formed in the opening 234. The dielectric layer 235 may be a single layer or a multilayer structure, and the material thereof is, for example, hafnium oxide or hafnium oxide/tantalum nitride or hafnium oxide/nitrogen. A composite material such as ruthenium oxide, oxidation = (〇NO, 〇SO), and the like is formed by a chemical vapor phase 'six-product method'. The tunneling dielectric layer 235 formed by this method has a better thinness. Of course, this layer of tunneling dielectric layer 235 may also be formed by leaving a portion of dielectric layer 232 when forming the opening. The semiconductor layer 240 is then filled in the opening 234. The material of the semiconductor layer 24A is, for example, germanium, and the formation method thereof is, for example, Epitaxial Lateral Overgrowth. 23 1338365 P950162 22261twf.doc/n Then, referring to FIG. 3E, a layer: 43 and a gate 245 are formed on the substrate 2A. The method for forming the dielectric layer 243 and the gate 245 is as follows: (Preferred to form a dielectric material layer (not shown) on the substrate 20G and the interpole = ^ (not shown). Then use the lithography technique to pattern The above material = formed. The dielectric material layer may be a single layer or a multilayer structure, and the material is, for example, oxygen cutting or oxygen cutting/nitriding dream, oxygen cutting/nitriding stone, yttrium oxide (0N0, 0S0), etc. The composite material is formed by a vapor deposition method; the material of the gate material layer is, for example, a doped material: if it is formed by chemical vapor deposition, the layer is undoped polycrystalline 2 2: the implantation step It can be formed by chemical vapor deposition by the method of forming '4 implants in the field'. After that, please refer to FIG. 3F, and the dielectric material layer 247 on the substrate conforms to the charge of the layer. The material layer 249; the material layer 247 may be a single layer or a multilayer structure. ^ Oxide oxide O/cut, oxidation, layer 249 is made of, for example, nanocrystals, nitrided materials such as oxidized residues. Cutting, oxidizing Weihuashi Xi/Emulsifying eve, emulsifying button, barium titanate or oxidized bell, etc. Referring to FIG. 3G, a portion of the charge trapping material layer 249 is removed, and the portion of the layer that is trapped in the layer r/=52f is charged into the layer 245 and the charge trapping layer. And forming the second unit 260 of the memory cell, wherein 24 1338365 P950162 22261 twf.d〇c/n dielectric layer 253 (especially under the charge trapping layers 255a, (10) and the dielectric layer 243 is, for example, the second unit Throughout the ray: When operating, the charge will pass through these dielectric layers: in layers 255a, 255b.
接著,在半導體層240兩側之中形成摻雜區 雜區265例如是以碟離子、珅離子等N型摻質進行換: 入製程所形成的。摻雜區265位於第二單元鳩與第二 元220兩側之半導體層24〇中,可以作為第二开、'^早 第一單元220的源極/汲極區。 與 然後在基底200上形成介電層263與頂導體層 頂導體層270連接閘極245,作為記憶體之頂字元I 。 至於記憶體底部、連接閘極23G之底導體層21Q ^ 元憶體之底字元線之用。後續形成減、位元^〜 此記憶,至製程,為熟知本馳者賴知,於此不再資二: 本實施例中所提出之非揮發性記憶體的製造方a °Next, the doped region 265 is formed on both sides of the semiconductor layer 240, for example, by an N-type dopant such as a dish ion or a cesium ion. The doped region 265 is located in the semiconductor layer 24A on both sides of the second cell and the second cell 220, and can serve as the source/drain region of the first cell 220 in the second opening. And then forming a dielectric layer 263 on the substrate 200 and a top conductor layer 270 connecting the gate 245 as the top word I of the memory. As for the bottom of the memory, the bottom conductor layer of the bottom conductor layer 21Q ^ yuan of the gate 23G is connected. Subsequent formation of subtraction, bit ^~ This memory, to the process, is known to the locals, but no longer the second: the manufacturer of the non-volatile memory proposed in this embodiment a °
用自行對準方式與形成間隙壁的方法,於開極现兩側= f電荷陷入層222a、222b,於閘極245兩側形成電= 曰255a、255b。所形成之單—記憶胞多位元的結構 了記憶體在“上所需佔據的佈局空間,大 、了小 件的積集度。 一了凡 以下說明本發明之非揮發性記憶體的操作方法 至圖扣是繪示本發明一實施例之非揮發性記憶體 記憶胞之第-位元的操作方法示意圖。圖认至圖 不本發明-實施例之-種非揮發性記憶體,單—記,^'·曰 25 1338365 P950162 22261 twf.doc/n 第二位元的操作示意圖。圖6A至圖6C是繪示本發明一實 施例之一種非揮發性記憶體,單一記憶胞之第三位元的操 作示意圖。圖7A至圖7C是繪示本發明一實施例之一種非 揮發性s己憶體,單一記憶胞之第四位元的操作示意圖。圖 . 8是繪示本發明一實施例之一種非揮發性記憶體的電路簡 ,·. 圖。 本實施例中之記憶胞的結構與圖2相同,為了能夠凸 顯本實施例之記憶胞的操作方法,圖4A至圖4C、圖5A 至圖5C、圖6A至圖6C、圖7A至圖7C所示之記憶胞, 是擷取圖2中第一單元、第二單元、半導體層與摻雜區繪 製而成的。所使用的元件符號與圖2相同,此處便省略關 於§己憶胞結構之說明。特別注意的是,圖2之摻雜區165 於本實施例中,即分別標示為源極區16元與汲極區 165b。 請參照圖4A,進行程式化操作時,於閘極13〇施加電 , 壓’源極區165&施加電壓Vs,汲極區165b施加電 壓Vd,閘極〗45施加電壓vCg2。其中,電壓vCgi大於 • 賴Vs,電壓%大於電壓Vd與電壓Vcg2,利用通道熱 電子(Channel Hot Electron)注入模式’使電子進入電荷陷入 . 層122a之中,以於記憶胞中存入第一位元B1。在一實施 例中,電壓Vcgl例如是介於約5〜1〇伏特之間,較佳為8 ’ 伏特;電愿Vs例如是介於約3〜6伏特之間’較佳為4伏 特;^壓Vd與電壓Vcg2例如是〇伏特。 請參照圖4B ’進行抹除操作時,於問極13〇施加電壓 Vcgl ’源極區165a施加電壓Vs,汲極區165b施加電壓 26 1338365 P950162 2226 ] twf.doc/nIn a self-aligned manner and a method of forming a spacer, on both sides of the open-circuit = f charge-trapping layers 222a, 222b, electric = 255a, 255b are formed on both sides of the gate 245. The formed single-memory multi-bit structure constitutes the layout space that the memory needs to occupy, and the large and small pieces of accumulation. The following describes the operation of the non-volatile memory of the present invention. The method to the figure is a schematic diagram showing the operation method of the first bit of the non-volatile memory cell of an embodiment of the present invention. The figure is not the non-volatile memory of the present invention. — ,, ^ 曰 1 25 1338365 P950162 22261 twf.doc / n operation diagram of the second bit. FIG. 6A to FIG. 6C are diagrams showing a non-volatile memory, a single memory cell according to an embodiment of the invention. FIG. 7A to FIG. 7C are schematic diagrams showing the operation of a non-volatile simon memory, a fourth bit of a single memory cell according to an embodiment of the present invention. FIG. 8 is a diagram showing the present invention. A circuit diagram of a non-volatile memory of an embodiment is shown in Fig. 2. The structure of the memory cell in this embodiment is the same as that of Fig. 2, in order to highlight the operation method of the memory cell of the embodiment, Figs. 4A to 4C. 5A to 5C, 6A to 6C, and 7A to 7C The memory cell is drawn by taking the first unit, the second unit, the semiconductor layer and the doped region in Fig. 2. The symbol used is the same as in Fig. 2, and the description about the § memory structure is omitted here. It is to be noted that the doped regions 165 of FIG. 2 are respectively labeled as the source region 16 and the drain region 165b in the present embodiment. Referring to FIG. 4A, when performing the stylization operation, the gate 13〇 Applying electricity, pressing 'source region 165' and applying voltage Vs, drain region 165b applies voltage Vd, and gate 45 applies voltage vCg2. Among them, voltage vCgi is greater than • Vs, voltage % is greater than voltage Vd and voltage Vcg2, using channel The channel hot electron (injection mode) causes electrons to enter the charge trapping layer 122a to store the first bit B1 in the memory cell. In one embodiment, the voltage Vcgl is, for example, between about 5 and 1 Between volts, preferably 8 ' volts; for example, Vs is between about 3 and 6 volts, preferably 4 volts; ^Vd and voltage Vcg2 are, for example, volts. Please refer to FIG. 4B' When the erase operation is performed, the voltage is applied to the source electrode region 165a. Voltage Vs, voltage applied to the drain region 165b 26 1338365 P950162 2226 ] twf.doc/n
Vd ’閘極145施加電壓Vcg2。其中,電壓Vcgl小於電壓 Vs、Vd與電壓Vcg2’電壓Vs高於電壓刈與電壓Vcg2, 利用4貝页-導帶熱電洞(BTBHH,Band To Band Hot Hole ) ,入模式,將電洞注入電荷陷入層122a,抹除先前存入之 第一位元在一實施例中,電壓Vcgl例如是介於約_5 〜-10伏特之間,較佳為-8伏特;電壓Vs例如是介於約+3 〜+6伏特之間,較佳為+4伏特;電壓Vd與電壓Vcg2例 如是〇伏特。 請參照圖4C,進行讀取操作時,於閘極13〇施加電壓 Vcgl,源極區165a施加電壓Vs,汲極區]6外施加電壓 Vd,閘極145施加電壓Vcg2。其中,電壓Vcgl大於電壓 vd’電壓vd大於電壓%與電壓Veg2,以逆向讀取( read)的方式讀取電荷陷人層ma t第—位sBi的儲存狀 態。在一實施例中’電壓Vcgl例如是介於3〜5伏特之間, 較佳為3伏特;電壓Vd例如是介於丨〜2伏特之間,較佳 為1.6伏特;電壓Vs與電壓Vcg2例如是〇伏特。 “本發明之非揮發性記憶體在單一記憶胞中具有四個電 荷陷入層,分別用以儲存資/料,上述圖4八至圖忙說明了 電何陷入層122a中第—位元B1之程式化、抹除與讀取操 作的方法。而電荷陷人層122b中之第二位元B2、電荷陷 入層B5a中之第三位元B3,以及電荷陷入層15北中之第 四位兀B4的#作機制與上述第—位元B1讀作機制相 似’以下進一步說明之。 請參照圖5A至圖5C ’程式化、抹除與讀取於電荷陷 27 1338365 P950162 2226itwf.doc/n 入層122b中之第二位元B2的方法,與上述第—位元m 之細作的不同僅在於將施加於雜區165&之電壓與施加 於及極區165b之电壓相互調換,如此便能夠使電子或電洞 改而進入%荷人層122b而程式化、抹除與讀取第二位元 B2。 請參照圖6A至圖6C,電荷陷入層咖之第三位元 B3的操作方法與第一位元⑴之操作方法的不同則在於, 將施加於閘極145之電壓與施加於閘極13〇之電壓對調, 從而使得電子、電洞可以注入於電荷陷入層155a之中,進 行此第三位元B3之操作。 凊參,¾圖7A至圖7C,至於在操作電荷陷入層〗55b 之第四位元B4的時候,則是將操作第—位元β1時,施加 於閘極145之電壓與施加於閘極130之電壓對調,以及調 換細<加於源極區165a之電壓Vs與施加於汲極區i65b之 電壓Vd ’如此偏壓的施加下’便可以程式化、抹除與讀取 記憶胞之第四位元B4。 上述實施例說明了單一個記憶胞之操作方法,但這些 記憶胞也可以排列成行/列陣列之記憶體。此記憶體之上視 圖可參照圖1所示,圖8則繪示了此記憶體之電路簡圖。 请參照圖8 ’以^己憶胞MC之弟一位元b 1為例,在進 行程式化操作時,於底字元線BWL1施加電壓Vcgl,位 元線BL】施加電壓Vs ’位元線BL2施加電壓vd,頂字元 線TWL1施加電壓Vcg2。其中,電壓Vcgl大於電壓Vs, 電壓Vs大於電壓Vd與電壓Vcg2,利用通道熱電子 28 1338365 P950162 22261 twf.doc/π (Channel Hot E以她)注入模式,以於記憶胞Mc中存 -位元B】。在-實施例中,電麼㈣例如是介於5〜⑺ 伏特之間’較佳為8伏特;電壓Vs例如是介於3〜6伏 之間’較佳為4伏特;電壓Vd與電壓Vcg2例如是〇伏特。 進行抹除猶時,於底字⑽BWL1施力 位το線BL1施加電壓Vs’位元線BL2施加電壓刈,頂字 元線TWL1施加電壓Vcg2,電壓Vcgl小於電壓%、刈 與電壓Vcg2,電壓Vs高於電壓vd與電壓乂啦,利用價 帶-導帶熱電洞(BTBHH,BandT()BandHc)tHGle)注入模 式,抹除㈣存人之第—位元B卜在—實施例中,電壓 Vcgl例如是介於-5〜_1〇伏特之間,較佳為,8伏特電壓The Vd' gate 145 applies a voltage Vcg2. Wherein, the voltage Vcgl is smaller than the voltages Vs, Vd and the voltage Vcg2', and the voltage Vs is higher than the voltage 刈 and the voltage Vcg2, and the hole is injected into the electric field by using a 4B-BBHB (Band To Band Hot Hole). Into the layer 122a, erasing the previously stored first bit. In an embodiment, the voltage Vcgl is, for example, between about _5 and -10 volts, preferably -8 volts; the voltage Vs is, for example, about Between +3 and +6 volts, preferably +4 volts; voltage Vd and voltage Vcg2 are, for example, volts. Referring to Fig. 4C, when a read operation is performed, a voltage Vcgl is applied to the gate 13A, a voltage Vs is applied to the source region 165a, a voltage Vd is applied outside the drain region 6, and a voltage Vcg2 is applied to the gate 145. Wherein, the voltage Vcgl is greater than the voltage vd' voltage vd is greater than the voltage % and the voltage Veg2, and the storage state of the charge trap layer ma t first bit sBi is read in a reverse read manner. In one embodiment, the voltage Vcgl is, for example, between 3 and 5 volts, preferably 3 volts; the voltage Vd is, for example, between 丨 and 2 volts, preferably 1.6 volts; for example, voltage Vs and voltage Vcg2 It is a volt. "The non-volatile memory of the present invention has four charge trapping layers in a single memory cell for storing resources/materials. The above-mentioned Figure 4-8 to figure shows how the electricity is trapped in the first bit B1 of the layer 122a. A method of stylizing, erasing, and reading operations, and a second bit B2 in the charge trapping layer 122b, a third bit B3 in the charge trapping layer B5a, and a fourth bit in the north of the charge trapping layer 15 The #4 mechanism of B4 is similar to the above-mentioned first-order B1 read mechanism. 'The following is further explained. Please refer to FIG. 5A to FIG. 5C' for stylization, erasing and reading in charge trap 27 1338365 P950162 2226itwf.doc/n The method of the second bit B2 in the layer 122b is different from the above-described detail of the first bit m only in that the voltage applied to the impurity region 165 & and the voltage applied to the polar region 165b are mutually exchanged, so that The electronic or electric hole is changed to enter the %Hole layer 122b to program, erase and read the second bit B2. Referring to FIG. 6A to FIG. 6C, the operation method and the third bit B3 of the charge trapping layer The operation method of one bit (1) is different in that the voltage applied to the gate 145 is applied. The voltage applied to the gate 13〇 is reversed, so that electrons and holes can be injected into the charge trapping layer 155a to perform the operation of the third bit B3. 凊, 3⁄4, FIG. 7A to FIG. 7C, as for operation When the charge is trapped in the fourth bit B4 of the layer 55b, when the first bit β1 is operated, the voltage applied to the gate 145 is reversed with the voltage applied to the gate 130, and the thinning is applied to the source. The voltage Vs of the polar region 165a and the voltage Vd applied to the drain region i65b are applied under such a bias voltage to program, erase and read the fourth bit B4 of the memory cell. The above embodiment illustrates a single one. The operation method of the memory cells, but these memory cells can also be arranged in a row/column array memory. The upper view of the memory can be referred to FIG. 1, and the circuit diagram of the memory is shown in FIG. 8 is an example of a cell b 1 of the cell MC, and a voltage Vcgl is applied to the bottom word line BWL1 during the stylization operation, and the bit line BL is applied with a voltage Vs 'bit line BL2. The voltage vd, the top word line TWL1 applies a voltage Vcg2, wherein the voltage Vcgl is greater than Voltage Vs, voltage Vs is greater than voltage Vd and voltage Vcg2, using channel hot electron 28 1338365 P950162 22261 twf.doc / π (Channel Hot E in her) injection mode, in memory cell Mc - bit B]. In the embodiment, the electric quantity (4) is, for example, between 5 and (7) volts, preferably 8 volts; the voltage Vs is, for example, between 3 and 6 volts, preferably 4 volts; the voltage Vd and the voltage Vcg2 are, for example,抹伏特。 When erasing, the bottom word (10) BWL1 force bit το line BL1 applies voltage Vs' bit line BL2 applies voltage 刈, top word line TWL1 applies voltage Vcg2, voltage Vcgl is less than voltage %, 刈 and voltage Vcg2 The voltage Vs is higher than the voltage vd and the voltage ,, using the valence band-guide band thermoelectric hole (BTBHH, BandT() BandHc) tHGle) injection mode, erasing (4) the first bit of the depositor B - in the embodiment The voltage Vcgl is, for example, between -5 and 1 〇 volt, preferably, 8 volts.
Vs例如是介於+3〜+6伏特之間,較佳為+4伏特;電壓刈 與電壓Vcg2例如是〇伏特。 進行讀取操作時,於底字元線施加電壓Vcgl,位元線 BU施加電壓Vs ’位元線犯施加電壓Vd,頂字元線 TWL1施加電愿Vcg2 ’電壓Vcg】大於電壓vd,電壓vd 電壓Vs與電壓Vcg2,以逆向讀取(reverse read)的方 式讀取記憶胞MC之第-位元Bi的儲存狀態。在一實施 例中’電壓Vcgl例如是介於3〜5伏特之間,較佳為3伏 =’·電M Vd例如是介於卜2伏特之間’較佳為16伏特; 電壓Vs與電壓Vcg2例如是〇伏特。 ^至於記憶胞MC中第二位元至第四位元的操作方法, 熟知^技藝者當可由上述單一記憶胞中第二位元至第四位 兀的操作方法而推知,於此不贅述。 29 P950162 22261twf.doc/n no 乂 Π揮發性冗憶體的操作方法中’分別於閘極 、^和5、源極區16兄與源極區165b施加適當的偏 制電荷進行的方法,進而操作此記憶體,操 作上十分簡單。且由於電荷陷人層是設置於閘極的兩側, 因,’各錄TL的操作*會造絲此互相干擾,從而能夠 提高記憶體的可靠度與電性表現。 ,圖9疋繪示應用本發明一實施例的一個積體電路的簡 =電路方塊圖。電路990包括-齡於半導體基底之上, 單一記憶胞具有多位元之非揮發性記憶體(記憶胞陣列) 900。一個列解碼器(r〇w dec〇der)9i〇搞接至多條字元線 905,並沿著記憶胞陣列9〇〇中的各列而排列。一個行 解碼器(column decoder)920耦接至多條位元線915,這些 位元線915係沿著記憶胞陣列9〇〇中的各行而排列,並 用以從記憶胞陣列900中的多位元記憶胞讀取並程式 化資料。在匯流排960上會有位址供應給行解碼器920及 列解碼器910。在方塊(bl〇ck)930中的感應放大器及資料輸 入結構(sense amplifiers and data-in structures),係經由匯流 排925而耗接至行解碼器920 資料會經由資料輸入線 (data-in line)933,從電路 990 上的輸入/輸出埠(input/output P〇rt) ’或是從電路990的其他内部或外部資料源,輸入於 方塊930中的資料輸入結構。在所述之實施例中,此電路 990可以包括其他電路’如泛用目的處理器、特定目的的 應用電路,或以非揮發性記憶體(記憶胞陣列)所支持 之整合模組。資料會經由資料輸出線(data-out line)935, 1338365 P950162 22261twf.doc/n 從方塊930 _的感測放大器,輸出至位於電路990上的輸 入/輸出埠’或是電路990的其他内部或外部資料目的地。 在本實施例中’使用偏壓配置狀態器(bias arrangement state machme)950的一控制器’控制了偏壓配置供應電壓 (bias arrangement supply voltages)940 的應用,例如讀取、Vs is, for example, between +3 and +6 volts, preferably +4 volts; voltage 刈 and voltage Vcg2 are, for example, volts. When the read operation is performed, the voltage Vcgl is applied to the bottom word line, the bit line BU is applied with the voltage Vs' bit line, and the applied voltage Vd is applied. The top word line TWL1 applies the electric force Vcg2 'voltage Vcg} is greater than the voltage vd, the voltage vd The voltage Vs and the voltage Vcg2 read the storage state of the first bit Bi of the memory cell MC in a reverse read manner. In one embodiment, the voltage Vcgl is, for example, between 3 and 5 volts, preferably 3 volts = '. The electrical M Vd is, for example, between 2 volts, preferably 16 volts; the voltage Vs and voltage Vcg2 is, for example, a volt. ^ As for the operation method of the second to fourth bits in the memory cell MC, it is well known that the skilled artisan can be inferred from the operation method of the second to fourth bits in the single memory cell, and will not be described here. 29 P950162 22261twf.doc/n no 乂Π The method of operating the volatile memory in 'the gate, ^ and 5, the source region 16 and the source region 165b respectively apply appropriate bias charge, and then Operating this memory is very simple to operate. Moreover, since the charge trapping layer is disposed on both sides of the gate, the operation of each recorded TL can cause mutual interference, thereby improving the reliability and electrical performance of the memory. FIG. 9 is a block diagram of a simplified circuit diagram of an integrated circuit to which an embodiment of the present invention is applied. Circuitry 990 includes a non-volatile memory (memory cell array) 900 having a multi-bit cell over a semiconductor substrate. A column decoder (r〇w dec〇der) 9i is connected to the plurality of word lines 905 and arranged along the columns in the memory cell array 9. A row decoder 920 is coupled to a plurality of bit lines 915 which are arranged along the rows in the memory cell array 9 and are used to multi-bit from the memory cell array 900. The memory cell reads and programs the data. An address is supplied to the row decoder 920 and the column decoder 910 on the bus 960. The sense amplifiers and data-in structures in the block 930 are consumed by the bus 925 to the row decoder 920. The data is input via the data input line (data-in line). 933, input/output P〇rt from circuit 990 or other internal or external data source from circuit 990, input to the data input structure in block 930. In the illustrated embodiment, the circuit 990 can include other circuitry such as a general purpose processor, a special purpose application circuit, or an integrated module supported by a non-volatile memory (memory cell array). The data is output from the sense amplifier of block 930 _ to the input/output port ’ on circuit 990 or other internals of circuit 990 via data-out line 935, 1338365 P950162 22261 twf.doc/n. External data destination. In the present embodiment, 'a controller using a bias arrangement state machme 950' controls the application of bias arrangement supply voltages 940, such as reading,
程式化、抹除、抹除確認與程式化確認電壓等。凡仅利 斋可使用習知之特定目的邏輯電路。在替代實施例中 此控制器包括一泛用目的處理器,係執行一電腦程式而 控制,元件之刼作。在又一實施例中,此控制器係使用 了特疋目的邏輯電路以及一泛用目的處理器之組合。 ml然本發明6以實施例揭露如上,然其並非用以限定 何所屬技術領域中具有通f知識者,在不脫離 神和範圍内,#可作些許之更動與潤飾,因此 保護範圍當視後附之巾請專利範圍所界定者為 【圖式簡單說明】Stylize, erase, erase confirmation, and stylize confirmation voltage. Any specific purpose logic circuit can be used for the benefit of only Lizhai. In an alternate embodiment, the controller includes a general purpose processor that performs a computer program to control the operation of the components. In yet another embodiment, the controller uses a combination of special purpose logic circuitry and a general purpose destination processor. The present invention 6 is disclosed above by way of example, but it is not intended to limit the knowledge of those skilled in the art, and it is possible to make some changes and refinements without departing from the scope of the gods. The attached towel should be defined by the scope of patents [simplified description of the drawings]
的結:二ί綠示本發明-實施例之-種非揮發性記憶體 圖1Β是繪示本發明另一實施 — 體的結構剖_。 ㉟轉發性錢 結構纷示本發明—實施例之—種非揮發性記憶體的 示之:二1!及圖3δ至圖3(}是沿著圖2中㈣* 灵靶例之一種非揮發性記憶體的製造流程剖 31 1338365 P950162 2226] twf.doc/n 面圖。 圖3A-2是沿著圖2中ΙΙ-ΙΓ線所繪示之本發明一實施 - 例之一種非揮發性記憶體的製造流程剖面圖。 、 圖4 Α至圖4 C是繪示本發明一實施例之—種非揮發性 . §己憶體,單一 s己憶胞之第一位元的操作示意圖。 ** 圖至圖5C是繪示本發明一實施例之—種非揮發性 記憶體,單一記憶胞之第二位元的操作示意圖。 圖6A至圖6C是繪示本發明一實施例之—種非揮發性 記憶體’單一記憶胞之第三位元的操作示意圖。 圖7A至圖7C是繪示本發明一實施例之—種非揮發性 記憶體,單一記憶胞之第四位元的操作示意圖。 圖8疋繪示本發明一實施例之一種非揮發性記憶體的 電路簡圖。 一 圖9是繪示應用本發明一實施例之一種積體電路之簡 化電路方塊圖。 * 【主要元件符號說明】 • 100、200 :基底 105、205 :絕緣層 110、BWU、BWL2、BWL3 :底字元線 170、TWU、TWL2、TWL3 :頂字元線 . 115、125、132、153、163、215、232、243、263 :介 電層 117、119 :保護層 120、220 :第一單元 32 1338365 P950162 22261 twf.doc/n 122a :第一電荷陷入層 122b :第二電荷陷入層 130 :第一閘極 135、143、235 :穿隧介電層 140 :半導體層 145 :第二閘極 155a :第三電荷陷入層 155b :第四電荷陷入層 160、260 :第二單元 165、265 :摻雜區 165a :源極區 16 5 b ·》及極區 175 :插塞 203 :凹陷 210 :底導體層 217、234 :開口 221、249 :電荷陷入材料層 222a、222b、255a、255b :電荷陷入層 223、247 :介電材料層 230、245 :閘極 240 :半導體層 270 :頂導體層 900 :非揮發性記憶體(記憶胞陣列) 905 :字元線 33 1338365 P950162 22261 twf.doc/n 910 :列解碼器 915、BL1、BL2、BL3 :位元線 920 :行解碼器 925、960 :匯流排 930 :方塊 933 ··資料輸入線 935 :資料輸出線 940 :偏壓配置供應電壓 950 :偏壓配置狀態器 990 :電路 MC :記憶胞。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 35 Forwarding money structure shows the present invention - an example of a non-volatile memory: two 1! and Figure 3 δ to Figure 3 (} is a non-volatile one along the (4) * 灵 target of Figure 2 Manufacturing process of sexual memory section 31 1338365 P950162 2226] twf.doc/n face view. Fig. 3A-2 is a non-volatile memory of an embodiment of the present invention taken along the ΙΙ-ΙΓ line in Fig. 2 FIG. 4 is a cross-sectional view showing the operation of the first bit of a single singular cell in accordance with an embodiment of the present invention. FIG. 5C is a schematic diagram showing the operation of a non-volatile memory, a second bit of a single memory cell according to an embodiment of the present invention. FIG. 6A to FIG. 6C are diagrams showing an embodiment of the present invention. Schematic diagram of the operation of the third bit of a non-volatile memory 'single memory cell. FIG. 7A to FIG. 7C are diagrams showing the operation of a non-volatile memory, the fourth bit of a single memory cell according to an embodiment of the invention. Figure 8 is a schematic circuit diagram of a non-volatile memory according to an embodiment of the present invention. A simplified circuit block diagram of an integrated circuit according to an embodiment of the present invention. * [Description of main component symbols] • 100, 200: substrate 105, 205: insulating layer 110, BWU, BWL2, BWL3: bottom word line 170, TWU, TWL2, TWL3: top word line. 115, 125, 132, 153, 163, 215, 232, 243, 263: dielectric layer 117, 119: protective layer 120, 220: first unit 32 1338365 P950162 22261 twf .doc/n 122a: first charge trapping layer 122b: second charge trapping layer 130: first gate 135, 143, 235: tunneling dielectric layer 140: semiconductor layer 145: second gate 155a: third charge The trapping layer 155b: the fourth charge trapping layer 160, 260: the second unit 165, 265: the doping region 165a: the source region 16 5 b · and the polar region 175: the plug 203: the recess 210: the bottom conductor layer 217, 234: openings 221, 249: charge trapping material layers 222a, 222b, 255a, 255b: charge trapping layers 223, 247: dielectric material layers 230, 245: gate 240: semiconductor layer 270: top conductor layer 900: non-volatile Memory (memory cell array) 905: word line 33 1338365 P950162 22261 twf.doc/n 910 : column decoder 915, BL1, B L2, BL3: bit line 920: row decoder 925, 960: bus 930: block 933 · data input line 935: data output line 940: bias configuration supply voltage 950: bias configuration state 990: circuit MC : memory cell
3434
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