TWI338228B - Computer system having bios function - Google Patents

Computer system having bios function Download PDF

Info

Publication number
TWI338228B
TWI338228B TW96133193A TW96133193A TWI338228B TW I338228 B TWI338228 B TW I338228B TW 96133193 A TW96133193 A TW 96133193A TW 96133193 A TW96133193 A TW 96133193A TW I338228 B TWI338228 B TW I338228B
Authority
TW
Taiwan
Prior art keywords
basic input
output system
selection signal
computer device
bus
Prior art date
Application number
TW96133193A
Other languages
Chinese (zh)
Other versions
TW200912659A (en
Inventor
Hui Lin
Eric Chiou
Original Assignee
Inventec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inventec Corp filed Critical Inventec Corp
Priority to TW96133193A priority Critical patent/TWI338228B/en
Publication of TW200912659A publication Critical patent/TW200912659A/en
Application granted granted Critical
Publication of TWI338228B publication Critical patent/TWI338228B/en

Links

Landscapes

  • Stored Programmes (AREA)

Description

1338228 』九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種電腦設備’更詳而言之,係關於 種具有基本輸入輸出系統(BIOS)選擇功能而可選擇 BIOS來啓動作業之電腦設備。 【先前技術】 電腦用戶在使用電腦設備的過程中,都會接觸到 BI〇S’它在電腦設備中起著非常重要的作用。BIOS,完整 而言應該是ROM—BIOS,是唯讀記,憶體基本輸入/輸出系 統(Basic Input/Output System)的簡寫,它實際上 是被燒錄到電腦中的一組程式,為電腦提供最初級的、最 直接的硬體控制。準確而言,BI〇s係用以作為硬體與軟 體程式之間的一個“轉換器,,,或者說是介面(雖然它本身 也只疋一個程式),負責解決硬體的即時需求,並按軟體 對硬體的操作要求具體執行。1338228 』 Nine, invention description: [Technical field of the invention] The present invention relates to a computer device. More specifically, it is possible to select a BIOS to start a job with a basic input/output system (BIOS) selection function. Computer equipment. [Prior Art] Computer users will be exposed to BI〇S’ during the use of computer equipment, which plays a very important role in computer equipment. The BIOS, in its entirety, should be ROM-BIOS, which is a shorthand for the Basic Input/Output System. It is actually a set of programs that are burned into a computer. Provides the first level of the most direct hardware control. To be precise, BI〇s is used as a "converter," or interface between hardware and software (although it is only a program in itself), responsible for solving the real-time needs of the hardware, and According to the software requirements for the operation of the hardware.

傳統電腦設備之主機板上通常都只具有一個基本輸 人輸出系統(iegacyBI〇S)晶片’一旦這顆_5晶片出現 問題’比如說被GIH病毒破壞或者是意外造成遞升級 失敗或者H0M物理損毀,整個電腦設備就無法使用。雖 然目前已經具有雙_(dualBI〇s)之類的技術,即於 主機板上Μ設1備用_晶片,且其連接方式與原 無異,俾當原讓出現問題時,即可自動啓動該備 用之晶片。 現有技術中’卩臺灣專利公告號為545637為例,該 110356 5 利係提供種T防止BIOS資料存取失敗之裝置以及 二有備伤BIOS之電腦設備,,,係為—種可防止bi〇s資料 子取失敗之裳置,可在BI〇s資料取失敗之時,由使用者 刀換或由電路系統自行切換至另一個備用之則S裝置, 如此使用者不必為了進行補救,而去採用軟體程式取代 BI〇S裝置、或是拆卸機器直接更換BIOS裝置,如此可達 到進一步之防護效果等。 # / :而該專利之説明書中所揭示之技術實際應用時有 著很大的限制,原因在於該專利係透過使用相同類型之數 據匯飢排、地址匯流排以分別連接一優先使用之Μ⑽晶 片以及-備用BIOS晶片;換言之,其請s晶片以及備用 之BI〇S晶片係連接於同一匯流排。因此,該兩顆BIOS 晶片亦必需是同類型;惟,目前已出現的擴展軔體介面 (Extensible Firmware lnterface,EFI )技術,係用以 取代該BIOS的下一代BIOS軔體技術,但是由於EFI係採 籲用全新的架構及連接方式,考慮到穩定性和相容性而無法 在售型機β上使用,因此上述專利技術之舊有雙BI 架 構會因介面不同或連接匯流排不同等原因,而無法達成可 選擇使用EFI或者傳統基本輸入輸出系統晶片等不同 BIOS晶片以完成硬體初始化等作業之效果,實為缺撼。 此外,於該類雙BIOS系統中,兩個BI0S晶片由於架 構及連接方式一致,一般均使用同一個基本引導記錄 (BootBlock),如果該基本引導記錄亦損壞的話,則該 備用B10S同樣無法使用。 ]10356 6 因此,如何找到一 選擇之方式,並可 於不同或者相同BIOS間進行 待解決之問題。 π决上述之種種弊端,實為目前亟 【發明内容】 -種本發明之,在於提供 備,使電腦設備中存在。選=:擇功能之電腦設 ⑺簡are)。在^擇任心換之_拿刀體 系统目的在於提供—種具有基本輸入輸出 …&擇功月b之電腦設備’可依據實際需要切換不同 BIOS並加以使用,功能更為強大。 〃本發明之又-目的在於提供—種具有基本輸入輸出 系.先選擇功旎之電腦設備,以極小成本來實現該選 擇功能,大大提升產業利益^ 為達上述及其它目的,本發明係提供一種具有基本輸 入輸出系統選擇功能之電腦設備,係包括:主機系統,係 至少具有第一匯流排、第二匯流排、以及用以控制該第一 匯流排及該第二匯流排之控制裝置;第一基本輸入輸出系 統裝置,係連接於該第一匯流排;第二基本輸入輸出系統 裝置,係連接於該第二匯流排;以及選擇訊號產生裝置, 係連接於該控制裝置,用以產生對應該第一匯流排之第一 選擇訊號及對應該第二匯流排之第二選擇訊號之其中一 者,以供該控制裝置接收到該第一與該第二選擇訊號之其 中一者,而可控制該第一與該第二匯流排之其中一者來致 110356 7 1338228 一能該第一與該第二基本輸入輸出系統裝置之其中一者。 。 於一個貫施例中’該控制裝置係為南橋晶片(South ' Bndge Chip),該第一匯流排係為低接腳計數(L〇w pin :Count ; LPC)匯流排,而該第二匯流排係為周邊元件互連 (Peripheral Comp0nent Interc〇nnect ; pCI)匯流排。 並且,該控制裝置係透過復用接腳(Strap pin)來 接收該第一選擇訊號及第二選擇訊號。 此外,該選擇訊號產生裝置係包括開關單元,一端連 #接於接地端,另一端連接於電源端,用以於該接地端及電 源端間切換連接,以分別產生該第一選擇訊號及第二選擇 说旒,其中,該第一選擇訊號係為低電位訊號,該第二選 擇訊號係為高電位訊號。此外,該開關單元係可外露於該 電腦設備,以供使用者主動切換BI〇s功能。於一實施例 中,該第一基本輸入輸出系統裝置係為傳統基本輸入輸出 系統(legacy BIOS)晶片,第二基本輸入輸出系統裝置係 籲為擴展軔體介面(EFI)晶片;抑或,於另一實施例中,該 第一基本輸入輸出系統裝置係為擴展軔體介面(I)晶 片,第二基本輸入輸出系統裝置係為傳統基本輸入輸出系 統(legacy BIOS)晶片。 相較於習知技術,本發明之具有基本輸入輸出系統選 擇功月b之電腦設備,係由兩個β I 連接於兩個不同之匯 流排,透過連接於該控制裝置之選擇訊號產生裝置來發出 不同之選擇訊號,以致能以不同匯流排連接於該控制裝置 之相同或者不同之BIOS裝置以進行作業,突破了習知技 110356 8 1338228 術需使用相同類型匯流排所連接之兩顆同類型晶片 -之限制’功能更為強大。 【實施方式】 • 以下係藉由特定的具體實例說明本發明之實施方 式,熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本,明之其他優點與功效。本發明亦可藉由其他不同 的具體實例加以施行或應用,本說明書中的各項細節亦可 基於不同觀點與應用,在不悖離本發明之精神下進行各種 #修飾與變更。 請參閲第1圖,係為本發明之具有基本輸入輸出系統 選擇功能之電腦設備!之架構示意圖,電腦設備i包括·· 主機系統1卜第一基本輸入輸出系統裝置112、第二基本 輸入輸出系統裝置113、以及選擇訊號產生裝置114。 該主機系統11係至少具有第一匯流排、第二匯流 排、以及用以控制該第一匯流排及該第二匯流排之控制裝 鲁置11卜應注意的是,該主機系統J i即包括常見電腦設 備中所有構成硬體,例如顯示器、cpu、主機板、顯示卡 等構件,由於該些構件及其作用原理均為習知者,且非本 毛月之主要特徵’故不另作贊述。於本實施例中,該主機 系統11可具有主機板,而控制裝置111係為電性連接於 該主機系統u之主機板的南橋晶片(s〇uth BridgeTraditional computer equipment motherboards usually only have a basic input output system (iegacyBI〇S) chip 'once this _5 chip has problems', such as being destroyed by the GIH virus or accidentally causing the upgrade failure or H0M physical damage The entire computer device cannot be used. Although there is currently a technology such as dual_(dualBI〇s), that is, a spare_chip is set on the motherboard, and the connection method is the same as the original, and when the problem occurs, the automatic startup is started. Spare wafer. In the prior art, 'Taiwan Patent Publication No. 545637 is taken as an example. The 110356 5 provides a device for preventing the failure of BIOS data access and a computer device for preventing the BIOS from being damaged, and is a type that can prevent bi〇. s data failure failed, when the BI〇s data fails, the user switches or the circuit system switches to another standby S device, so the user does not have to go for remediation. Replacing the BI〇S device with a software program, or disassembling the machine to directly replace the BIOS device, can achieve further protection effects. # / : The technical application disclosed in the specification of the patent has a great limitation because the patent uses the same type of data sinking and address bus to respectively connect a preferred (10) wafer. And - a spare BIOS chip; in other words, the s chip and the spare BI 〇 S chip are connected to the same bus. Therefore, the two BIOS chips must be of the same type; however, the Extensible Firmware Interface (EFI) technology that has emerged to replace the BIOS's next-generation BIOS firmware, but because of the EFI system. The new architecture and connection method are adopted, and the stability and compatibility cannot be used on the sales model β. Therefore, the old BI architecture of the above patented technology may be different due to different interfaces or different bus bars. It is not enough to achieve the effect of using different BIOS chips such as EFI or traditional basic input/output system chips to complete hardware initialization. In addition, in this type of dual BIOS system, the two BI0S chips generally use the same basic boot record (BootBlock) because of the same architecture and connection mode. If the basic boot record is also damaged, the spare B10S is also unusable. ] 10356 6 Therefore, how to find a way to choose, and to solve the problem between different or the same BIOS. π 决 决 决 决 决 决 决 决 决 决 亟 亟 亟 发明 发明 亟 发明 发明 亟 亟 亟 亟 亟 亟 亟 亟 亟 亟 发明 发明 发明 发明 发明 发明Select =: Select the function of the computer set (7) Jane are). The purpose of the system is to provide a computer device with basic input and output ... & The present invention is also directed to providing a computer device having a basic input/output system and selecting a function first, which realizes the selection function at a very low cost, and greatly enhances industrial interests. To achieve the above and other objects, the present invention provides A computer device having a basic input/output system selection function includes: a host system having at least a first bus bar, a second bus bar, and a control device for controlling the first bus bar and the second bus bar; a first basic input/output system device connected to the first bus bar; a second basic input/output system device connected to the second bus bar; and a selection signal generating device connected to the control device for generating Corresponding to one of the first selection signal of the first bus and the second selection signal corresponding to the second bus for the control device to receive one of the first and second selection signals, and Controlling one of the first and second bus bars to 110356 7 1338228 - the first and second basic input output system devices One person. . In one embodiment, the control device is a South 'Bndge Chip, and the first bus bar is a low pin count (L〇w pin :Count; LPC) bus bar, and the second bus bar is The platoon is a peripheral component interconnect (Peripheral Comp0nent Interc〇nnect; pCI) busbar. Moreover, the control device receives the first selection signal and the second selection signal through a multiplex pin (Strap pin). In addition, the selection signal generating device includes a switch unit, one end connected to the ground end and the other end connected to the power end for switching between the ground end and the power end to respectively generate the first selection signal and the first In the second option, the first selection signal is a low potential signal, and the second selection signal is a high potential signal. In addition, the switch unit can be exposed to the computer device for the user to actively switch the BI〇s function. In one embodiment, the first basic input/output system device is a conventional basic input/output system (legacy BIOS) chip, and the second basic input/output system device is called an extended media interface (EFI) chip; or In one embodiment, the first basic input output system device is an extended media interface (I) chip, and the second basic input output system device is a conventional basic input/output system (legacy BIOS) chip. Compared with the prior art, the computer device with the basic input/output system selection function of the present invention is connected to two different bus bars by two β I, through the selection signal generating device connected to the control device. Different selection signals are issued so that the same or different BIOS devices connected to the control device can be operated with different bus bars, which breaks through the two types of the same type of busbars connected by the same type of busbar 110356 8 1338228 The chip-to-limit feature is more powerful. [Embodiment] The following embodiments of the present invention are described by way of specific examples, and those skilled in the art can readily understand the other advantages and advantages of the present disclosure. The present invention may be embodied or applied in various other specific embodiments. The details of the present invention can be variously modified and modified without departing from the spirit and scope of the invention. Please refer to Fig. 1, which is a computer device with the basic input/output system selection function of the present invention! The architecture of the computer device i includes a host system 1 including a first basic input/output system device 112, a second basic input/output system device 113, and a selection signal generating device 114. The host system 11 has at least a first bus bar, a second bus bar, and a control device for controlling the first bus bar and the second bus bar. It should be noted that the host system J i is Including all the hardware components in common computer equipment, such as monitors, cpu, motherboards, display cards, etc., because these components and their working principles are well-known, and not the main features of this month, so do not make another Praise. In this embodiment, the host system 11 can have a motherboard, and the control device 111 is a south bridge chip (s〇uth Bridge) electrically connected to the motherboard of the host system u.

Chip) ’且該控制裝置1U具有用於接收訊號之復用接腳 (StraPpin)(未圖示,容後陳述)。該第一匯流排係 為低接腳計數(L〇wPinCount; Lpc)匯流排,而該第二 9 110356 1338228 4匯流排係為周邊元件互連(Peripheral Component .Interconnect ; PCI)匯流排。 第一基本輸入輸出系統裝置112係連接於主機系統 :1 1之第匯流排,而第二基本輸入輸出系統裝置1 1 3係 連接於主機系統11之第二匯流排。於本實施例中,第一 基本輸入輸出系統裝置112及第二基本輸入輸出系統裝 置113可為相同之例如傳統基本輸入輸出系統晶片 (legacy BI〇S)或擴展軔體介面(EFI)晶片,抑或其中之 •一者為傳統基本輸入輸出系統晶片而另一者為擴展軔體 介面晶片皆可,而該第一基本輸入輸出系統裝置1丨2與第 二基本輸入輸出系統裝置113係插設於該主機系統Η中 例如主機板(未圖示)上以進行作業。易言之,該第一兵 本輸入輸出系統裝置112與第二基本輸入輸出系°統裝置 113可為不同晶片類型之基本輸入輸出系統裝置,且、可為 燒錄内容不同之基本輸入輸出系統裝置。 • 須說明者,如前所述,控制裝置111係為南橋晶片, 而南樣晶片於電腦設備i中—般係用以控制級別^較 低=匯流排(BUS) ’例如PCI、LPC匯流排等,因而,於 本貫施例中,該第一匯流排係為Lpc匯流排,而該第二匯 流排係為pci匯流排,但並非以此限制本發明。Λ 一 基於南橋晶片之特點’故將第一基本輸入輸出系 置112及第二基本輸入輸出系統裝置113分別連接於泫^ -匯流排(即LPC匯流排)及該第二匯流排(即pci:、& 排),構成控制裝置πι(亦即南橋晶片)至該二bi〇s f ίο 110356 1338228 片(亦即第一基本輸入輸出系統裝置112及第二基本輸入 •輸出系統裝置113)之通路。 而本發明之選擇訊號產生裝置114則可配合控制裝 :置U1以透過該通路於該二BIOS晶片間加以擇取之作業。 選擇訊號產生裝置114係連接於控制裝置ill,用以 產生對應該第一匯流排之第一選擇訊號或對應該第二匯 μ排之第二選擇訊號;其中,當控制裝置1U接收到選擇 讯號產生裝置114所發出之第一選擇訊號時,透過該主機 籲板之LPC匯流排以致能第一基本輸入輸出系統裝置112 ; 當控制裝置111接收到選擇訊號產生裝置丨丨4所發出之第 二選擇訊號時,則透過該主機板之pci匯流排以致能第二 基本輸入輸出系統裝置113。 於本實施例中,如第2圖所示,該選擇訊號產生裝置 114係包括開關單元,該開關單元係將該選擇訊號產生裝 置114 一端連接於電源端221,另一端則連接於接地端 鲁220而其輸出端則連接至該控制裝置in之復用接腳 222,而其所發出之選擇訊號即為“LpcjrRAME—n,,。如此, 便可由該選擇訊號產生裝置丨丨4發出切換訊號給該復用 接腳222’而透過該控制裝置U1本身之復用接腳222來 接收切換匯流排之訊號。例如,當該開關單元連接至接地 端220,則產生該第一選擇訊號(亦即低電位訊號)送入復 用接腳222,此時,控制裝置U1即依據該低電位訊號透 過内部之邏輯電路啓動該LPC匯流排所連接之第一基本 輸入輸出系統裝置Π2 ;反之,若該開關單元係連接至電 110356 11 1338228 2 22卜則發出該第二選擇訊號(亦即高電位訊號)至復 用—接腳m’控制裝置⑴則啓動該ρπ㈣排所連接之 弟-基本輸人輸出系統裝置113,達到了選擇職晶片 之目的。 由此可知’本發明僅需設置一個簡單的選擇訊號產生 裝置(開關單元),即可切換電路而達成任意切換題 韌體之功能,所需成本相當低廉,具有成本效益。 雖本實施例中之選擇訊號產生裝置114係顯示設於 電腦設備之内,但於實際情況中,該開關單元可設計成外 露於電腦設備機殼之開關,例如設置於機箱面板,以供使 用者方便操作以選擇使用哪個BIOS來進行啓動作業,藉 此提供使用者主動切換B10S之功能。 須説明者,該選擇訊號產生裝置114復可為其他現有 可依需分別產生尚、低電平訊號之裝置,例如設於主機板 上之基板管理控制器控制(BMC)等亦可,非以本實施例為 限。 相較於習知技術,本發明之具有基本輸入輸出系統選 擇功能之電腦設備,係透過連接於該控制裝置之選擇訊號 產生裝置來發出不同之選擇訊號,以致能以不同匯流排連 接於該控制裝置之相同或者不同之BIOS裝置進行啓動作 業’突破了習知技術之雙BIOS系統中需使用相同類型匯 流排所連接之兩顆同類型B10S晶片之限制,功能更為強 大0 同時’應用本發明可讓系統中存在兩種相同或不同架 110356 12 1338228 構之BIOS韌體’並且在開機時可由使用者自由切換;因 此’在不同之BIOS傘刃體切換時,如果其中一個拿刃體損壞, 可切換使用另一個韋刃體;而且’一個主機系統中可設置不 同架構之B10S餘體,除提供相容性以提升產品功铲外, 亦具有可供使用者選擇之使用彈性。此外,本發明1透過 增設一選擇訊號產生裝置即實現該BI〇s之選擇功能,成 本極小而效用顯著,大大利於提升產業利益。 上述實施例僅例示性說明本發明之原理及盆 非用於限制本發明。任何熟習此項技藝之人 ^力效, J本發明之精神及範訂,對上述實施例進行修飾座改延 ^因此’本發明之權利賴範圍’應專 範圍所列。 、、甲叫寻利 【圖式簡單說明】 第1圖’係為本發明之具有基 能之電腦設備之架構示意圖;m ^糸統、擇功 第2圖,係為本發明之選擇訊號產生裝置 【主要元件符號說明】 I王展罝之電路圖。 11 輸入輸出系統選擇功能之電腦設備 111 112 113 114 220 221 222 控制裝置 ,一基本輸入輸出系統裝置 第二基本輸入輪出系統裝置 選擇訊號產生裝置 接地端 電源端 復用接腳 Π0356 13Chip)' and the control device 1U has a multiplex pin (StraPpin) for receiving signals (not shown, later stated). The first bus is a low pin count (L〇wPinCount; Lpc) bus, and the second 9 110356 1338228 4 bus is a Peripheral Component Interconnect (PCI) bus. The first basic input/output system device 112 is connected to the first busbar of the host system: 1 1 and the second basic input/output system device 1 1 3 is connected to the second busbar of the host system 11. In this embodiment, the first basic input/output system device 112 and the second basic input/output system device 113 may be the same, for example, a conventional basic input/output system chip (legacy BI〇S) or an extended media interface (EFI) chip. Or one of them is a conventional basic input/output system chip and the other is an extended body interface chip, and the first basic input/output system device 1丨2 and the second basic input/output system device 113 are interposed. The host system is, for example, a motherboard (not shown) for work. In other words, the first data input/output system device 112 and the second basic input/output system device 113 can be basic input/output system devices of different chip types, and can be basic input/output systems with different programming contents. Device. • It should be noted that, as mentioned before, the control device 111 is a south bridge chip, and the south sample chip is generally used in the computer device i to control the level ^ lower = bus bar (BUS) 'such as PCI, LPC bus bar And so, in the present embodiment, the first bus bar is an Lpc bus bar, and the second bus bar is a pci bus bar, but the present invention is not limited thereto. Λ Based on the characteristics of the south bridge chip, the first basic input/output system 112 and the second basic input/output system device 113 are respectively connected to the bus bar (ie, the LPC bus bar) and the second bus bar (ie, pci). :, & row, constitutes a control device πι (i.e., south bridge wafer) to the second 〇sf ίο 110356 1338228 chip (that is, the first basic input/output system device 112 and the second basic input/output system device 113) path. The selection signal generating device 114 of the present invention can cooperate with the control device to set U1 to select the operation between the two BIOS chips through the path. The selection signal generating device 114 is connected to the control device ill for generating a first selection signal corresponding to the first bus or a second selection signal corresponding to the second channel; wherein, when the control device 1U receives the selection message When the first selection signal sent by the device 114 is generated, the first basic input/output system device 112 is enabled through the LPC bus of the host board; when the control device 111 receives the selection signal generation device 丨丨4 When the signal is selected, the second basic input/output system device 113 is enabled through the pci bus of the motherboard. In the embodiment, as shown in FIG. 2, the selection signal generating device 114 includes a switching unit that connects one end of the selection signal generating device 114 to the power terminal 221 and the other end to the ground terminal. 220, the output terminal is connected to the multiplexing pin 222 of the control device in, and the selection signal sent by the control device is "LpcjrRAME-n,". Thus, the selection signal generating device 丨丨4 can issue the switching signal. The multiplexing pin 222' is used to receive the signal of the switching bus through the multiplexing pin 222 of the control device U1. For example, when the switching unit is connected to the ground terminal 220, the first selection signal is generated (also That is, the low potential signal is sent to the multiplexing pin 222. At this time, the control device U1 activates the first basic input/output system device Π2 connected to the LPC bus through the internal logic circuit according to the low potential signal; The switch unit is connected to the electric 110356 11 1338228 2 22 to send the second selection signal (that is, the high potential signal) to the multiplexing-pin m' control device (1) to start the connection of the ρπ (four) row The younger brother-input output system device 113 achieves the purpose of selecting a job chip. It can be seen that 'the invention only needs to set a simple selection signal generating device (switching unit), and can switch the circuit to achieve arbitrary switching problem toughness. The function of the body is relatively low in cost and cost-effective. Although the selection signal generating device 114 in the embodiment is displayed in the computer device, in actual situations, the switch unit can be designed to be exposed to the computer device. The switch of the casing is, for example, disposed on the chassis panel for the user to conveniently operate to select which BIOS to use for the startup operation, thereby providing the user with the function of actively switching the B10S. It should be noted that the selection signal generating device 114 can be re-enabled. For other existing devices that can generate a low-level signal, such as a substrate management controller control (BMC) provided on a motherboard, the present invention is not limited to the prior art. The computer device with the basic input/output system selection function of the present invention generates the device through the selection signal connected to the control device. The different selection signals are sent to enable the same or different BIOS devices connected to the control device to start the operation. The two BIOS systems that break through the conventional technology need to use the same type of bus bar to connect. The limitation of the same type of B10S chip is more powerful. At the same time, 'the invention can be used to have two identical or different BIOS firmwares of 110356 12 1338228 in the system' and can be freely switched by the user when booting; therefore' When switching between different BIOS umbrellas, if one of the blades is damaged, another blade can be switched; and 'B10S body can be set in different systems in one host system, in addition to providing compatibility to enhance the product. In addition to the power shovel, there is also flexibility for the user to choose. In addition, the present invention 1 realizes the selection function of the BI〇s by adding a selection signal generating device, and the cost is extremely small and the utility is remarkable, which greatly contributes to the improvement of industrial interests. The above examples are merely illustrative of the principles and pots of the invention and are not intended to limit the invention. Any person skilled in the art will be able to modify the above-described embodiments. Therefore, the scope of the present invention is set forth in the scope of the invention. , A called for profit [simplified description of the diagram] Figure 1 is a schematic diagram of the architecture of the computer device with the basic energy of the invention; m ^ 糸 system, selection of the second diagram, is the selection signal generated by the invention Device [Main component symbol description] I Wang Zhanyi's circuit diagram. 11 I/O system selection function computer equipment 111 112 113 114 220 221 222 Control unit, a basic input/output system unit 2nd basic input wheel-out system unit Select signal generation unit Ground terminal Power terminal Multiplexed pin Π0356 13

Claims (1)

ΖΖό 十、申請專利範圍: 1. 一種具有基本輸入輪出 包括: 系統選擇功能之電腦設備,係 主機系統,至少且古蝥厂士 m 具有弟一匯流排、第二匯流排 以及用以控制該第一 #苗. 遮仙·排及該第二匯流排之控制 裝置, 第基本輸入輸出系統裝置,係連接於該匯 流排; 第基本輸入輪出系統裝置,係連接於該第二匯 流排;以及 k擇》fl號產生裝置’係連接於該控制裝置,用以 產生對應該該第-匯流排之第一選擇訊號及對應該 第一匯机排之第二選擇訊號之其中一者,以供該控制 裝置接收到該第一與該第二選擇訊號之其中一者,而 可控制該第-與該第二匯流排之其中一者來致能該 第一與該第二基本輸入輸出系統裝置之其中一者。 2. 如申請專利範圍第1項之電腦設備,其中,該第-匯 流排係為低接腳計數(L〇wPinC〇unt;LPC)匯流排, 而該第二匯流排係為周邊元件互連(Peripheral Component Interconnect ; PCI)匯流排。 3. 如申請專利範圍第1項之電腦設備,其中,該控制裝 置係為南橋晶片(South Bridge Chip)。 4. 如申請專利範圍第2項之電腦設備,其中,該控制裝 置係透過復用接腳(Strap pin)來接收該第一選擇 14 110356 1338228 •, 訊號及第二選擇訊號。 5. 如申請專利範圍第1項之電腦設備,其中,該選擇訊 ,· 號產生裝置係包括開關單元,該開關單元一端連接於 :接地端’另一端連接於電源端,用以於該接地端及電 源端間切換連接,以分別產生該第一選擇訊號及第二 選擇訊號。 6. 如申請專利範圍第5項之電腦設備,其中,該開關單 元係外露於該電腦設備。 #7.如申請專利範圍第5項之電腦設備,其中,該第一選 擇訊號係為低電位訊號’而該第二選擇訊號係為高電 位訊號。 8.如申請專利範圍第1項之電腦設備,其中,該第一基 本輸入輸出系統裝置係為傳統基本輸入輸出系統 (legacy BIOS)晶片,第二基本輸入輸出系統裝置係 為擴展軔體介面(EFI)晶片。 鲁9.如申請專利範圍第1項之電腦設備,其中,該第一基 本輸入輸出系統裝置係為擴展軔體介面(EFI)晶片, 第二基本輸入輸出系統裝置係為傳統基本輸入輸出 系統(legacy BIOS)晶片。 10.如申請專利範圍第丨項之電腦設備,其中,該選擇訊 號產生裝置係為基板管理控制器 15 110356ΖΖό X. Patent application scope: 1. A computer device with basic input rotation including: system selection function, which is a host system, at least and the ancient factory has a bus, a second bus, and is used to control the The first #苗. the cemetery and the second busbar control device, the first basic input and output system device is connected to the busbar; the basic input wheeling system device is connected to the second busbar; And a k-type "fl" generating device is coupled to the control device for generating one of a first selection signal corresponding to the first bus bar and a second selection signal corresponding to the first bus bar, Receiving, by the control device, one of the first and second selection signals, and controlling one of the first and the second bus to enable the first and second basic input and output systems One of the devices. 2. The computer device of claim 1, wherein the first bus bar is a low pin count (L〇wPinC〇unt; LPC) bus bar, and the second bus bar is a peripheral component interconnect. (Peripheral Component Interconnect; PCI) bus. 3. The computer device of claim 1, wherein the control device is a South Bridge Chip. 4. The computer device of claim 2, wherein the control device receives the first selection 14 110356 1338228 •, a signal, and a second selection signal through a multiplex pin (Strap pin). 5. The computer device of claim 1, wherein the selection device comprises a switch unit, one end of the switch unit being connected to: the ground end and the other end connected to the power terminal for the grounding The terminal and the power terminal switch connection to respectively generate the first selection signal and the second selection signal. 6. The computer device of claim 5, wherein the switch unit is exposed to the computer device. #7. The computer device of claim 5, wherein the first selection signal is a low potential signal and the second selection signal is a high potential signal. 8. The computer device of claim 1, wherein the first basic input/output system device is a conventional basic input/output system (legacy BIOS) chip, and the second basic input/output system device is an extended media interface ( EFI) wafer. The computer device of claim 1, wherein the first basic input/output system device is an extended body interface (EFI) chip, and the second basic input/output system device is a conventional basic input/output system ( Legacy BIOS) chip. 10. The computer device of claim 2, wherein the selection signal generating device is a substrate management controller 15 110356
TW96133193A 2007-09-06 2007-09-06 Computer system having bios function TWI338228B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW96133193A TWI338228B (en) 2007-09-06 2007-09-06 Computer system having bios function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW96133193A TWI338228B (en) 2007-09-06 2007-09-06 Computer system having bios function

Publications (2)

Publication Number Publication Date
TW200912659A TW200912659A (en) 2009-03-16
TWI338228B true TWI338228B (en) 2011-03-01

Family

ID=44724957

Family Applications (1)

Application Number Title Priority Date Filing Date
TW96133193A TWI338228B (en) 2007-09-06 2007-09-06 Computer system having bios function

Country Status (1)

Country Link
TW (1) TWI338228B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10055296B2 (en) * 2015-10-30 2018-08-21 Quanta Computer Inc. System and method for selective BIOS restoration
TWI666556B (en) * 2018-03-27 2019-07-21 緯創資通股份有限公司 Electronic device and operating method thereof

Also Published As

Publication number Publication date
TW200912659A (en) 2009-03-16

Similar Documents

Publication Publication Date Title
US9965367B2 (en) Automatic hardware recovery system
TWI502366B (en) Cloud cluster system and booting and deployment method using for the same
US8805983B2 (en) Local externally accessible managed virtual network interface controller
TW201110025A (en) Power management in a virtual machine farm at the local virtual machine platform level by a platform hypervisor extended with farm management server functions
US20080043769A1 (en) Clustering system and system management architecture thereof
US20110113426A1 (en) Apparatuses for switching the running of a virtual machine between multiple computer devices belonging to the same computer platform and the associated switching methods
US10656676B2 (en) Docking device, electrical device, and MAC address cloning method
CN106155970B (en) automatic hardware recovery method and automatic hardware recovery system
WO2006129138A1 (en) Method of connecting hard disk
US10176030B2 (en) Runtime mechanism to correct incomplete namespace in persistent memory
US20190056773A1 (en) Peripheral device expansion card system
TWI338228B (en) Computer system having bios function
US7117353B2 (en) Methods and apparatus to enable console redirection in a multiple execution environment
CN112868013A (en) System and method for restoring field programmable gate array firmware via sideband interface
US7568091B2 (en) Computer platform system control unit data programming control method and system
JP2010218449A (en) Resource allocation system and resource allocation method
US10310575B2 (en) Virtual AC cycling within an information handling system
JP2010146087A (en) Method of managing system switching computer system
TWI444817B (en) Computer device
TWI750215B (en) Bios switching device
US20090276616A1 (en) Servo device and method of shared basic input/output system
CN102736908A (en) System, device and method for remotely setting CMOS (Complementary Metal-Oxide-Semiconductor Transistor) parameters
US20140317368A1 (en) Device information backup method, device, and system
Intel
Intel

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees