1336897 玖、發明說明：. 【發明所屬之技術領域】 本發明實施例係有關於積體電路的製造。更明確 說，本發明之實施例係有關於沉積及圖案化一低k介電 在一基材上的製程。 【先前技術】 從積體電路裝置在幾十年前被引入以來，積體電路 何已經在大小上劇烈地降低。從那時開始，積體電路大 遵循兩年/ 一半尺寸規則（經常稱摩爾定律），這表示在晶 上之裝置數每兩年增加一倍。今日製造設備現行生產具 0.13微米、甚至0.1微米特徵尺寸之裝置，明曰之設備 快生產具有更小特徵尺寸之裝置。 於裝置幾何中之持續降低已經產生具有較低k值之 需求，因為在相鄰金屬線間之電容耦合必須降低，以進 步降低在積體電路上之裝置尺寸。更明確地說，想要具 低介電常數（k)，低於約4.0之絕緣體。 一種降低k值之有效方法為引入多數孔在介電膜中 結果，低k膜經常具有低機械強度（例如硬度），這阻礙 將諸膜整合入裝置的製造的情形。後電漿處理係現行被 以增加低k值膜之機械強度。然而，電漿處置造成k值 增力σ 。 因此，有需要一方法，用以形成具有良好機械強度 低k介電層，及將之作出圖案。 地 層 幾 致 片 有 很 膜 有 〇 了 用 之 的 3 1336897 【發明内容】 本發明大致提供一種形成一導電特徵的方法，該 包含一基材上形成一觸媒種層；沉積一層包含碳之奈 於該觸媒種層上；在該奈米管中，形成一内連線開口 沉積一導電材料，在該内連線開口中。 於一實施例中，在一層奈米管沉積於一基材的一 種層上後，沉積一低k介電材料，使得該低k介電材 至少一部份係分散於該等奈米管間。該等奈米管及低 電材料形成一低k介電層，其然後被作出圖案與蝕刻 形成一内連線開口。導電材料被沉積於内連線開口中 形成一導電特徵。 於另一實施例中，一犧牲層係沉積在一基材之觸 層上。該犧牲層係被作出圖案並蝕刻，以在該犧牲層 形成一開口，其曝露出觸媒種層之曝露區。一層奈米 選擇地沉積在該觸媒種層之曝露區上，及一低k介電 係沉積在該基材上，使得至少一部份之低k介電材料 散於諸奈米管間。犧牲層然後被移除，在其位置留下 連線開口。一導電材料被沉積在内連線開口中。 一種形成雙鑲嵌結構的方法，該結構包含一或多 電層，其係為包含一層奈米管及一低k介電材料分散 奈米管間。 也提供一結構，其包含一低k介電層，該介電層 一層奈米管，其中該層奈米管係在低k介電材料的 方法 米管 :及 觸媒 料的 k介 ，以 ，以 媒種 中， 管係 材料 被分 一内 數介 於諸 包含 基質 4 1336897 中。， 【實施方式】 本發明之上述特徵可以參考實施例及本發明之詳 明加以詳細了解。部份實施例係示於附圖中。然而， 解的是，附圖只例示本發明之典型實施例，因此，並 以限定本發明之範圍，因本發明可以採用其他等效 例0 本發明之態樣提供一種形成低k介電膜之方法， 含一層包含碳之奈米管，並在該低k介電膜中，形成 電特徵。於此所用，”基材”用以表示基層，其上沉積 續之諸層，及包含該基層之結構。一層包含碳之奈米管 係沉積在基材1 00上之觸媒種層1 02上，如第1 A圖所 一内連線開口 1 0 6係形成在該層奈米管1 0 4中，如負 圖所示。内連線開口 1 0 6可以藉由沉積一抗触層，例 阻108在該層奈米管104上；圖案化該光阻108;及 該光阻作為一遮罩以蝕刻該層奈米管1 〇 4加以形成。 電材料1 1 0可以沉積在該内連線開口中，並選用地， 蓋層112可以沉積在該層奈米管104及導電材料110 如第1 C圖所示。 基材100可以為一半導體層，例如包含矽之一層 者，例如包含銅之一層的導電層。該觸媒種層102可 一層過渡金屬或過渡金屬之組合。例如，觸媒種層可 含鈷（Co)、鐵（Fe)、鎳（Ni)、鈦（Ti)、或其組合。觸媒 細說 應了 不用 實施 其包 一導 有後 104 示。 I 1 B 如光 使用 一導 一覆 上， ，或 以為 以包 種層 1336897 可以藉由.化學氣相·沉積（CVD)、物理氣相沉積（pvD)、一旋 塗製程、或其组合加以沉積。較佳地，觸媒種層可以藉由 Co、Ni、或Fe的CVD或PVD加以沉積。 可以相信觸媒種層成核該沉積在觸媒種層上之該層奈 米管104之成長。典型地，該層奈米管係為一 cvd製程所 沉積，例如一電漿加強CVD(PECVD)。該層奈米管可以由 包含碳氫化合物之混合物所沉積。例如CH4、C2H2、（：2H4 或其組合可以用作為該碳氩化合物。該混合物可以包含一 氮源，例如N2、N Η3、或其組合，及一載氣，例如氫、氬、 或氦。奈米管之高度及密度可以藉由改變製程條件加以控 制。 於一實施例中’觸媒種層及該層奈米管係沉積在一 Endura或Producer系統内，該兩系統均可以由美國加州聖 塔卡拉之應用材料公司購得。例如Co、Ni、或Fe的過渡 金屬可以以氬加以濺射，於低於2 0 0。(：之溫度，及於約 1 xl (Γ5托耳至約1 X1 〇-6托耳之壓力，以沉積該觸媒種層在 一室之基材上。該基材可以被傳送至另一室，用以PECVD έ玄層奈米管，例如藉由使用約1 〇 s c c m至約 1 〇 〇 s c c m之 C2H2、約5sccni至約50sccm之NH3、於約0.2至約0.4之 C2H2/NH3之流量比、約1 〇毫托耳至約3 000毫托耳之壓 力、及約3 50。(：至約475。〇之溫度。較佳地，奈米管具有約 2 0奈米至約5 〇奈米的直徑。 雖然第1 B及1 C圖顯示在奈米管10層沉積後，觸媒 種層1 02保持不動，但吾人相信觸媒種層可以至少部份遷 6 1336897 移入或通7過奈米管·。例如，來自鈷觸媒種層之鈷可以由 米管的基部移動至奈米管的尖端。或者，至少部份之鈷 以向上並通過奈米管的尖端，使得部份之鈷不再相關於 米管。因此，雖然第1 B及1 C圖及後續圖顯示在奈米管 積後，觸媒種層保持不動，但觸媒層可以更動態，如上 討論。 示於第1B圖中之有圖案光組108可以使用傳統光 沉積及圖案化技術加以沉積並圖案化。奈米管層然後被 刻，以建立一内連線開口。典型地，光阻10 8被移除。 例如包含銅之材料的導電材料1 1 0然後被沉積於内連線 口 1 06中，如第1 C圖所示。導電材料可以藉由CVD、PVD 電鍍法、無電電鍍、或其組合加以沉積。或者，在導電 料沉積前，一阻障層及/或一種層係沉積於内連線開口中 例如，可以沉積一组或氣化组阻障層及/或一銅種層。一 而言，在導電材料沉積後，基材被例如化學機械平坦法 以平坦化。或者，一覆蓋層11 2然後被沉積在基材上。 蓋層可以為一氧化矽層或另一介電層。於此所述之沉積 電材料、阻障層、及種層之方法與材料可以使用於以上 一實施例中。 於一較佳實施例中，上述針對第1 A -1 C圖所述之方 包含沉積一低k介電材料，使得在形成内連線開口前， k介電材料之至少一部份係沉積在鄰近奈米管之間。 此，形成一包含一層含碳之奈米管的低k介電膜，其中 該層奈米管係在低k介電材料之基質中。此一實施例將 奈 可 奈 沉 所 阻 Ί虫 開 、 材 〇 般 加 覆 導 任 法 低 因 > 針 7 1336897 對第2及‘ 3圖 一觸媒種 之奈米管204 示，並說明第 該層奈米管可 奈米管104之 料205然後沉 圖之步驟320 沉積，使得低 間，例如在相 製程所沉積。 如包含矽之多 之多孔低k材 學公司購得、 LKD5 109，其 t 多孔低k材料 1 . 8 至約 2.6 { 典型地， 者，基材可以 積在基材上之 束處理，以強 低k介電膜被 之真空。一用 同受讓之美國 加以‘說明。 層2〇2係、沉積在_基材· i，及_層含碳 係沉積在該觸媒種層2〇2上，如第圖所 3圖之步驟300及31〇中。觸媒種層2〇2及 以使用與上述第1A圖之觸媒層102及該層 相同之材料與方法加以沉積。一低k介電材 積在基材上，如第2B圖所示，並說明於第3 t。如第2B圖所示’低k介電材料2〇5係 k介電材料之至少一部份係沉積於奈米管 鄰奈米管間。較佳地，低k介電材料為旋塗 較佳地，該低k介電材料為一多孔材料’例 孔氧化物，例如多孔摻碳氧化矽。可以使用 料例包含p-SiLK介電材料，其係可由杜耳化 Orion絕緣材料，其係由可Trik〇n購得、 巨JSR購得、及XPX，其係可由Asahi購得。 可以為一乾凝膠及/或極端低k(eLK，例如約 '電常數）之介電材料。 在低k介電材料沉積後，基材被平坦化。或 以一反應離子敍刻製程加以處理，以移除p 過量材料。同時，或者，基材也可以以電子 化該層奈米管及該低k介電材料。較佳地， 傳送至另一室，而不必破壞用以電子束處理 於低k介電膜之電子束處理及室係描述於共 專利申請第1 0/302，3 75號案，名為，，使用電 8 1336897 子束之形成超低k·膜的方法”之案中，該案係申請於2 Ο Ο 2 年十一月2日，該案係併入作為參考。於一實施例中，電 子束處置具有於約 5 0至約 2 0 0 0微庫倫每平方公分（μ c/cm2)之劑量，於約1至20千電子伏（KeV)。電子束處置 典型操作於約室溫至約4 5 0 °C間之一溫度，持續1分鐘至 約1 5分鐘，例如約2分鐘。較佳地，電子束處理係執行於 約4 0 0 °C，持續2分鐘。於一態樣中，電子束處理條件包 含 4.5KV、1.5mA、及 500/zc/cm2 於 400°C。雖然，任一 電子束裝置均可以使用，但一例示裝置為E B K室，其可以 由應用材料公司購得。 該層奈米管然後被圖案化並蝕刻，以形成一内連線開 口 ，如第3圖之步驟3 3 0所述。該層奈米管可以藉由沉積 及圖案化一抗触劑，例如在該層奈米管上之光阻208，如 第 2 C圖所示，並蝕刻通過該層奈米管，以建立内連線開 口 206，如第2D圖所示。若有的話，觸媒種層202可以藉 由一氣為主電漿蝕刻製程加以蝕刻穿過。典型地，光阻2 0 8 被移除。一例如包含銅之材料的導電材料2 1 0然後被沉積 在如第2E圖所示之内連線開口 206中，並如第3圖之步 驟340所述。或者，在導電材枓沉積前，一阻障層及/或種 層（未示出）係沉積在内連線開口中，如上參考第1 A-1 C圖 實施例所述。一般而言，在導電材料沉積後，基材被例如 化學機械平坦法加以平坦化。或者，一覆蓋層21 2然後被 沉積在基材上。覆蓋層可以為一氧化石夕層或另一介電層。 如上針對第2A-2E圖及第3圖所示之實施例係為一製 1336897 程例， 而，於 觸媒種 處理可 選擇沉 4 A-4F 4〇3係 圖之步· 程所沉 犧牲層 σ 407 圖之步 藉由沉 該犧牲 然後被 並說明 沉積在 相鄰奈 驟540 典 者，基 在基材 處理， 其包含在-.觸媒種層上，全面沉積一層奈米管。然 此所述之實施例可以使用一層奈米管選擇沉積在— 層上加以執行。針對全面沉積之上述之相同材料及 以用以沉積觸媒種層、該層之奈米管、及在下述之 積實施例中之低k介電材料。此一實施例將參考第 圖及第5圖加以說明》 觸媒種層402係沉積4 _基材4〇〇上，及一犧牲層 >儿積在觸媒種層上，性 λ 咽保徑席 如第4Α圖所示並說明於第5 驟5 00 & 5 1〇。犧牲層可以為一抗蝕劑、為旋塗製 積之有❹玻璃、或為PEcVD/5i沉積之氧化石夕層。 4。3然後被圖案化及钱刻，以在犧牲層中 ，其曝露觸媒種層’如第4B圖所示 形成開 驟52°中。犧牲層可以使用傳統抗钱及：:：第5 積一抗蚀層在犧牲層上'圖案化該抗轴層’ 層，加以圖案化及钱刻。一層包含及姓刻 沉積在觸媒種層之曝露區409上，如第4(^管4〇4 於第5圓之步驟53"。一低 圖所示’ a u , 览材枓405缺後 基材上，使得至少_部份之低k介 …、後 米管之間，如第4D ϋ m ^ 係沉積在 中。 第D圖所不，並說明於第5圖之步 :地：在沉積低k介電材料後，基材被平坦化 可以破以—反應離子蝕刻製程處理， 2 上之過量材料。或者，選擇地，基材可：沉積 以強化該層奈米管及^介電材料。 電子束 10 1336897 犧牲層4 Ο 3可以然後被移除，以形成内連線開口 4 1 3 ’ 如第4Ε圖所示並說明於第5圖之步驟550中。犧牲層可 以為一濕蝕刻製程或一反應離子蝕刻製程所移除，以移除 犧牲層但不移除相當量之低k介電材料及該層奈米管。若 有的話，該在犧牲層下之觸媒種層可以為一濕蝕刻製程所 移除。一例如包含銅或鋁之材料的導電材料層420然後沉 積在内連線開口 413中’如第4F圖所示並說明在第5圖 之步驟560中。或者，在導電材料沉積前，一阻障層及/ 或一種層422可以沉積在内連線開口中。一般而言，在導 電材料被沉積後，基材被平坦化，例如藉由化學機械平坦 化。或者，一覆蓋層430然後沉積在基材上。該覆蓋層可 以為一氧化石夕詹或另一介電層。 該包含奈米管及低k介電材料之層可以用以作為在雙 鑲嵌結構中之一或多數介電層。第6圖顯示一雙鑲嵌結構 600之例子’其中兩介電層包含奈米管及於此所述之低k 介電材料。一第一層包含碳之奈米管604係沉積在一第一 觸媒種層602上’其係沉積在一基材6〇1上，及一第一低 k材料605係沉積在基材上，如參考第2A-2E圖及第3圖 所述。一蝕刻步驟6 0 6係沉積在基材並被作出圖案’以定 義一垂直内連線開口 607。蝕刻停止層6〇6可以為一氮化 石夕層，一氧化梦層’或具有沉積在蝕刻停止層上及下與介 電層不同之蝕刻特徵的一層。一第二觸媒種層608，一第 二層奈米管6 1 〇 ’及一第二低k介電材料6丨4係然後被沉 積在基材上’如參考第2 A-2E圖及第3圖所述。同時，如 1336897 上所述，'在每一低· k介電材料沉積後，基材可以平坦 被處理以反應離子蝕刻製程，及/或以電子束處置。 一水平内連線開口 6 1 5係然後在第二層奈米管及 低k介電材料中作出圖案，例如藉由沉積及圖案化一 層（未示出）或硬罩616，經過第二層奈米管及第二低 電材料。基材然後被蝕刻以形成一水平内連線及一垂 連線。較佳地，若一抗蝕劑被用以圖案化第二低k介 料時，則在蝕刻後，抗蝕劑被移除，以形成内連線。 如包含銅之材料的導電材料6 2 0然後被沉積在内連線 中。或者，一阻障層及/或種層 622係在導電材料被 前，被沉積在内連線開口中。一般而言，在導電材料 積後，基材被例如化學機械平坦法加以平坦化。或者 覆蓋層624被沉積在基材上。覆蓋層可以為一氧化石夕 另一介電層。 吾人相信包含低k介電材料分佈於一層奈米管中 k介電層提供低k介電膜，其具有想要組合之低k及 機械特性。吾人相信作為強化元件之奈米管以強化可 弱之低k材料，例如多孔低k材料。吾人相信在低奈 間之低k介電材料可以最小化電流洩漏，其可能發生 電層中之奈米管間，其只包含奈米管。 雖然前述係有關本發明實施例，本發明之其他實 可以在不脫離本發明基本範圍下加以導出，其範圍係 下之申請專利範圍所決定。 化， 第二 抗蝕 k介 直内 電材 一例 206 沉積 被沉 y —— 層或 之低 良好 能較 米管 在介 施例 由以 12 1336897 【圖式簡單說明】‘ 第1 A-1 C圖為一基材處理順序之第一實施例。 第2 A - 2 E圖為一基材處理順序之第二實施例。 第3圖為例示基材處理順序之第二實施例流程圖。 第4 A - 4 F圖為基材處理順序之第三實施例。 第5圖為例示基材處理順序之第三實施例之流程圖 第6圖為一雙鑲嵌結構之實施例。 【元件代表符號簡單說明】 100 基 材 102 觸 媒 種 層 1 04 奈 米 管 106 内 連 線 開口 108 光 阻 110 導 電 材 料 112 覆 蓋 層 200 基 材 202 觸 媒 種 層 204 奈 米 管 205 低 k 介 電 材 料 208 光 阻 2 10 導 電 材 料 2 12 覆 蓋 層 400 基 材 402 觸 媒 種 層 403 犧 牲 層 404 奈 米 管 405 低 k 介 電 材 料 407 開 σ 409 曝 露 區 4 13 内 連 線 開口 420 導 電 材 料 430 覆 蓋 層 600 雙 鑲 嵌 結 構 60 1 基 材 602 觸 媒 種 層 604 奈 米 管 605 低 k 介 電 材 料 606 钱 刻 停 止層 13 1336897 607 内 連 線 開口· 608 觸 媒 種 層 610 奈 米 管 614 低 k 介 電材料 6 15 内 連 線 開口 616 硬 罩 620 導 電 材 料 622 種 層 624 覆 蓋 層 141336897 发明, invention description: [Technical field to which the invention pertains] Embodiments of the invention relate to the manufacture of an integrated circuit. More specifically, embodiments of the present invention relate to a process for depositing and patterning a low-k dielectric on a substrate. [Prior Art] Since the integrated circuit device was introduced decades ago, the integrated circuit has been drastically reduced in size. Since then, integrated circuits have followed the two-year/half size rule (often called Moore's Law), which means that the number of devices on the crystal doubles every two years. Today's manufacturing equipment currently produces devices with feature sizes of 0.13 micrometers or even 0.1 micrometers, and alum equipment quickly produces devices with smaller feature sizes. The continued reduction in device geometry has created a need for lower k values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of the device on the integrated circuit. More specifically, it is desirable to have an insulator having a low dielectric constant (k) of less than about 4.0. One effective way to reduce the value of k is to introduce a majority of the pores in the dielectric film. Low-k films often have low mechanical strength (e.g., hardness), which hinders the integration of the films into the fabrication of the device. Post-plasma processing is currently used to increase the mechanical strength of low-k film. However, the plasma treatment causes a k-value increase σ. Therefore, there is a need for a method for forming a low-k dielectric layer with good mechanical strength and patterning it. The present invention generally provides a method of forming a conductive feature comprising forming a catalyst seed layer on a substrate; depositing a layer comprising carbon nene On the catalyst seed layer; in the nanotube, an interconnecting opening is formed to deposit a conductive material in the interconnect opening. In one embodiment, after depositing a layer of nanotubes on a layer of a substrate, depositing a low-k dielectric material such that at least a portion of the low-k dielectric is dispersed between the nanotubes . The nanotubes and the low-voltage material form a low-k dielectric layer which is then patterned and etched to form an interconnect opening. A conductive material is deposited in the interconnect opening to form a conductive feature. In another embodiment, a sacrificial layer is deposited on the contact layer of a substrate. The sacrificial layer is patterned and etched to form an opening in the sacrificial layer that exposes the exposed regions of the catalyst layer. A layer of nano is selectively deposited on the exposed region of the catalyst layer and a low-k dielectric is deposited on the substrate such that at least a portion of the low-k dielectric material is interspersed between the nanotubes. The sacrificial layer is then removed leaving a wire opening at its location. A conductive material is deposited in the interconnect openings. A method of forming a dual damascene structure comprising one or more electrical layers comprising a layer of nanotubes and a low-k dielectric material dispersed between the nanotubes. A structure is also provided comprising a low-k dielectric layer, the dielectric layer being a layer of nanotubes, wherein the layer of nanotubes is in the form of a low-k dielectric material: In the medium, the tube material is divided into a number of inclusions in the matrix 4 1336897. [Embodiment] The above features of the present invention can be understood in detail with reference to the embodiments and the details of the present invention. Some embodiments are shown in the drawings. However, the drawings are merely illustrative of typical embodiments of the present invention, and thus, to limit the scope of the present invention, other equivalents can be employed in the present invention. Aspects of the present invention provide a low-k dielectric film. The method comprises a layer of carbon nanotubes comprising carbon and forming electrical features in the low k dielectric film. As used herein, "substrate" is used to denote a base layer, layers deposited thereon, and structures comprising the base layer. A layer of carbon nanotubes is deposited on the catalyst layer 102 on the substrate 100. As shown in Fig. 1A, an interconnect opening 106 is formed in the layer of nanotubes 104. , as shown in the negative image. The interconnect opening 106 can be formed by depositing a resist layer on the layer of nanotubes 104; patterning the photoresist 108; and the photoresist acts as a mask to etch the layer of nanotubes 1 〇 4 is formed. An electrical material 110 may be deposited in the interconnect opening and, optionally, a cap layer 112 may be deposited on the layer of nanotubes 104 and conductive material 110 as shown in FIG. Substrate 100 can be a semiconductor layer, such as a layer comprising germanium, such as a conductive layer comprising one layer of copper. The catalyst seed layer 102 can be a combination of a transition metal or a transition metal. For example, the catalyst seed layer may contain cobalt (Co), iron (Fe), nickel (Ni), titanium (Ti), or a combination thereof. The catalyst is detailed. It should be done without the implementation of its package. I 1 B is coated with light, or it is thought that the cladding layer 1336897 can be formed by chemical vapor deposition (CVD), physical vapor deposition (pvD), a spin coating process, or a combination thereof. Deposition. Preferably, the seed layer can be deposited by CVD or PVD of Co, Ni, or Fe. It is believed that the catalyst seed layer nucleates the growth of the layer of nanotubes 104 deposited on the catalyst seed layer. Typically, the layer of nanotubes is deposited by a cvd process, such as a plasma enhanced CVD (PECVD). The layer of nanotubes can be deposited from a mixture comprising hydrocarbons. For example, CH4, C2H2, (:2H4 or a combination thereof may be used as the carbon argon compound. The mixture may comprise a nitrogen source such as N2, N Η 3, or a combination thereof, and a carrier gas such as hydrogen, argon, or helium. The height and density of the nanotubes can be controlled by changing the process conditions. In one embodiment, the 'catalyst seed layer and the layer of nanotubes are deposited in an Endura or Producer system, both of which can be used by California. A commercially available transition material such as Co, Ni, or Fe can be sputtered with argon at a temperature below 20,000. (: temperature, and about 1 xl (Γ5 Torr to about 1 X1 〇-6 Torr pressure to deposit the catalyst layer on a substrate of the chamber. The substrate can be transferred to another chamber for PECVD έ 层 奈 nanotubes, for example by using From about 1 〇sccm to about 1 〇〇sccm of C2H2, from about 5 sccni to about 50 sccm of NH3, at a flow ratio of from about 0.2 to about 0.4 C2H2/NH3, from about 1 Torr to about 3,000 mTorr. And about 3 50. (: to about 475. The temperature of the crucible. Preferably, the nanotube has about 20 nm to about 5 The diameter of the nanometer. Although the first B and 1 C diagrams show that the catalyst layer 02 remains untouched after the 10 layers of the nanotubes are deposited, we believe that the catalyst layer can be moved at least partially 1 1336897 or Passing through the nanotube. For example, cobalt from the cobalt catalyst layer can be moved from the base of the rice tube to the tip of the nanotube. Alternatively, at least a portion of the cobalt can pass up and through the tip of the nanotube. Part of the cobalt is no longer related to the rice tube. Therefore, although the first and second C and subsequent figures show that the catalyst layer remains intact after the tube is filled, the catalyst layer can be more dynamic, as discussed above. The patterned light set 108, shown in Figure 1B, can be deposited and patterned using conventional photodeposition and patterning techniques. The nanotube layer is then engraved to create an interconnect opening. Typically, the photoresist 10 8 The conductive material 110, such as a material containing copper, is then deposited in the interconnect port 106 as shown in Figure 1 C. The conductive material can be electroplated by CVD, PVD, electroless plating, or The combination is deposited. Alternatively, a barrier layer and/or prior to deposition of the conductive material The seed layer is deposited in the interconnect opening, for example, a set of gasification group barrier layers and/or a copper seed layer may be deposited. First, after the conductive material is deposited, the substrate is subjected to, for example, chemical mechanical flattening. Or planarization. A cover layer 11 2 is then deposited on the substrate. The cap layer may be a hafnium oxide layer or another dielectric layer. The deposited electrical material, barrier layer, and seed layer are described herein. The method and material can be used in the above embodiment. In a preferred embodiment, the above-described method for the first A-1C includes depositing a low-k dielectric material such that before forming the interconnect opening At least a portion of the k dielectric material is deposited between adjacent nanotubes. Thus, a low-k dielectric film comprising a layer of carbon-containing nanotubes is formed, wherein the layer of nanotubes is in a matrix of low-k dielectric material. In this embodiment, the snails are blocked by the snails, and the sputum is covered by the sputum. The needle 7 1336897 is shown in the second and third graphs of the catalyst of the nanotube 204, and the description The layer of nanotube nanotubes 104 is then deposited 205 and then deposited in a lower portion, such as in a phase process. For example, LKD5 109, which has a porous low-k material company, contains a porous low-k material of 1.8 to about 2.6. [Typically, the substrate can be deposited on a substrate to be strong. The low-k dielectric film is vacuumed. Use the same as the United States of the United States to ‘describe. The layer 2〇2, deposited on the _substrate·i, and _ layer carbonaceous layer are deposited on the catalyst seed layer 2〇2, as shown in steps 300 and 31 of Figure 3 of the accompanying drawings. The catalyst seed layer 2〇2 is deposited using the same materials and methods as the catalyst layer 102 of FIG. 1A above and the layer. A low-k dielectric material is deposited on the substrate as shown in Figure 2B and illustrated in the third t. As shown in Fig. 2B, at least a portion of the low-k dielectric material 2〇5-k dielectric material is deposited between the nanotubes and the adjacent nanotubes. Preferably, the low-k dielectric material is spin-coated. Preferably, the low-k dielectric material is a porous material, such as a porous carbon-doped cerium oxide. A material may be used which comprises a p-SiLK dielectric material which is available from Duer Orion insulating material available from Trik〇n, JSR, and XPX, which are commercially available from Asahi. It may be a dry gel and/or an extremely low k (eLK, such as about 'electric constant) dielectric material. After deposition of the low-k dielectric material, the substrate is planarized. Or treated with a reactive ion characterization process to remove excess material from p. Also, alternatively, the substrate may also electronically laminate the layer of nanotubes and the low-k dielectric material. Preferably, the transfer to another chamber without destroying the electron beam processing and chambers for electron beam processing on the low-k dielectric film is described in co-pending application No. 10/302,357, entitled In the case of using the method of forming an ultra-low k·film by a beam of electricity, the case is filed on November 2, 2, the disclosure of which is incorporated herein by reference. The electron beam treatment has a dose of from about 50 to about 2,000 microcoulombs per square centimeter (μ c/cm 2 ) at about 1 to 20 kiloelectron volts (KeV). Electron beam treatment typically operates at about room temperature. To a temperature between about 45 ° C for 1 minute to about 15 minutes, for example about 2 minutes. Preferably, the electron beam treatment is performed at about 40 ° C for 2 minutes. In the sample, the electron beam processing conditions include 4.5 KV, 1.5 mA, and 500/zc/cm 2 at 400 ° C. Although any electron beam device can be used, an exemplary device is an EBK chamber, which can be applied by Applied Materials. The layer of nanotubes is then patterned and etched to form an interconnect opening as described in step 3 3 0 of Figure 3. The rice tube can be formed by depositing and patterning an anti-contact agent, such as a photoresist 208 on the layer of nanotubes, as shown in Figure 2C, and etching through the layer of nanotubes to establish an interconnect opening. 206, as shown in Figure 2D. If present, the catalyst seed layer 202 can be etched through a gas-based plasma etching process. Typically, the photoresist 2 0 8 is removed. The conductive material 210 of the material is then deposited in the interconnect opening 206 as shown in FIG. 2E and as described in step 340 of Figure 3. Alternatively, a barrier layer is formed prior to deposition of the conductive material. And/or seed layers (not shown) are deposited in the interconnect openings as described above with reference to the embodiment of Figures 1 A-1 C. In general, after deposition of the conductive material, the substrate is, for example, chemically mechanically flattened. The method is planarized. Alternatively, a cover layer 21 2 is then deposited on the substrate. The cover layer may be a layer of oxidized stone or another dielectric layer as described above for Figures 2A-2E and 3 The embodiment is a system of 1336,897, and the process of the catalyst can be selected as the step of the 4 A-4F 4〇3 system. The step of sinking the sacrificial layer σ 407 is performed by sinking the sacrifice and then being deposited and deposited on the adjacent substrate. The substrate is processed on the substrate, which is contained on the layer of the catalyst, and a layer of nanotubes is deposited. However, the embodiments described herein can be performed by depositing a layer of nanotubes on the layer. The same materials as described above are fully deposited and used to deposit the catalyst layer, the nanotubes of the layer, and underneath The low-k dielectric material in the embodiment is described. This embodiment will be described with reference to the first and fifth figures. The catalyst seed layer 402 is deposited on the substrate 4, and a sacrificial layer is > The product is on the layer of the catalyst, and the sexual λ throat guard is shown in Figure 4 and described in the 5th step 5 00 & 5 1〇. The sacrificial layer may be a resist, a spin-on-glass formed by spin coating, or a oxidized layer of PEcVD/5i deposited. 4. 3 is then patterned and engraved to expose the catalyst seed layer in the sacrificial layer as shown in Fig. 4B to form a 52° opening. The sacrificial layer can be patterned and etched using a conventional anti-money and::: 5th anti-corrosion layer on the sacrificial layer 'patterning the anti-axial layer' layer. A layer containing and surname is deposited on the exposed area 409 of the catalyst seed layer, such as step 4 (^ tube 4〇4 in step 5 of step 5". A low figure shows 'au, view material 405 missing base On the material, at least some of the low-k... and between the rear rice tubes, such as the 4D ϋ m ^ system, are deposited. Figure D is not, and is illustrated in the step of Figure 5: Ground: in the deposition After the low-k dielectric material, the substrate is planarized to break the excess material on the reactive ion etching process, or alternatively, the substrate can be deposited to strengthen the layer of nanotubes and dielectric materials. Electron beam 10 1336897 Sacrificial layer 4 Ο 3 can then be removed to form interconnect opening 4 1 3 ' as shown in FIG. 4 and illustrated in step 550 of Figure 5. The sacrificial layer can be a wet etch. The process or a reactive ion etching process is removed to remove the sacrificial layer but does not remove a substantial amount of the low-k dielectric material and the layer of nanotubes. If any, the catalyst layer under the sacrificial layer It can be removed for a wet etch process. A layer 420 of conductive material, such as a material comprising copper or aluminum, is then deposited in the interconnect opening 4 13 is shown in Figure 4F and illustrated in step 560 of Figure 5. Alternatively, a barrier layer and/or a layer 422 may be deposited in the interconnect opening prior to deposition of the conductive material. After the conductive material is deposited, the substrate is planarized, for example by chemical mechanical planarization. Alternatively, a cover layer 430 is then deposited on the substrate. The cover layer may be a oxidized stone or another dielectric. The layer comprising the nanotube and the low-k dielectric material can be used as one or a plurality of dielectric layers in the dual damascene structure. Figure 6 shows an example of a dual damascene structure 600 in which two dielectric layers are included A nanotube and a low-k dielectric material as described herein. A first layer comprising a carbon nanotube 604 is deposited on a first catalyst seed layer 602' which is deposited on a substrate 6〇1 And a first low-k material 605 is deposited on the substrate as described in reference to Figures 2A-2E and Figure 3. An etching step 6 6 is deposited on the substrate and patterned to define a vertical The interconnect opening 607. The etch stop layer 6 〇 6 may be a nitride layer, a oxidized dream layer ' or have a deposition a layer of etching features on the etch stop layer and under the dielectric layer. A second catalyst layer 608, a second layer of nanotubes 6 1 〇 ' and a second low-k dielectric material 6 丨 4 The substrate is then deposited on the substrate as described in reference to Figures 2A-2E and Figure 3. At the same time, as described in 1336897, 'after deposition of each low-k dielectric material, the substrate can be flattened Processing is performed by a reactive ion etching process and/or by electron beam processing. A horizontal interconnect opening 6 1 5 is then patterned in the second layer of nanotubes and low-k dielectric material, for example by deposition and patterning A layer (not shown) or a hard mask 616 passes through the second layer of nanotubes and the second low electrical material. The substrate is then etched to form a horizontal interconnect and a vertical line. Preferably, if a resist is used to pattern the second low-k dielectric, the resist is removed after etching to form interconnects. A conductive material such as a material containing copper is then deposited in the interconnect. Alternatively, a barrier layer and/or seed layer 622 is deposited in the interconnect opening before the conductive material is applied. Generally, after the conductive material is deposited, the substrate is planarized by, for example, chemical mechanical flattening. Or a cover layer 624 is deposited on the substrate. The cover layer may be a monohydrate or another dielectric layer. We believe that the inclusion of a low-k dielectric material in a layer of nanotubes provides a low-k dielectric film with a low-k and mechanical properties that it is desired to combine. We believe that nanotubes act as strengthening elements to strengthen weak, low-k materials, such as porous low-k materials. We believe that low-k dielectric materials at low temperatures can minimize current leakage, which may occur between nanotubes in the electrical layer, which only contains nanotubes. While the foregoing is a description of the embodiments of the present invention, the invention may be inferred by the scope of the invention. a second resist k-internal electrical material, an example of 206 deposition is sinking y - layer or low good energy compared to the rice tube in the case of the application by 12 1336897 [simple description of the diagram] '1 A-1 C A first embodiment of a substrate processing sequence. 2A-2E is a second embodiment of a substrate processing sequence. Figure 3 is a flow chart illustrating a second embodiment of the substrate processing sequence. The 4A - 4F figure is a third embodiment of the substrate processing sequence. Fig. 5 is a flow chart illustrating a third embodiment of the substrate processing sequence. Fig. 6 is an embodiment of a dual damascene structure. [Simplified description of component symbol] 100 substrate 102 catalyst layer 10 04 nanotube 106 interconnect opening 108 photoresist 110 conductive material 112 covering layer 200 substrate 202 catalyst layer 204 nano tube 205 low k Electrical material 208 photoresist 2 10 conductive material 2 12 cover layer 400 substrate 402 catalyst layer 403 sacrificial layer 404 nano tube 405 low k dielectric material 407 open σ 409 exposed area 4 13 interconnect opening 420 conductive material 430 Overlay 600 Double damascene structure 60 1 Substrate 602 Catalyst layer 604 Nano tube 605 Low k Dielectric material 606 Money engraving stop layer 13 1336897 607 Interconnection opening · 608 Catalyst layer 610 Nano tube 614 Low k Dielectric material 6 15 interconnect opening 616 hard cover 620 conductive material 622 seed layer 624 cover layer 14