TWI336188B - Method and apparatus for sub-slot packets in wireless communication - Google Patents
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1336188 九、發明說明: 【發明所屬之技術領域】 本揭示案大體而言係關於通信,且更具體言之,本揭示 案係關於用於無線通信系統之傳輸技術。 【先前技術】 廣泛採用無線通信系統來提供諸如語音、視訊、封包資 料、訊息傳遞、廣播等的各種通信服務。此等系統可為能 夠藉由共用可用的系統資源來支援多個使用者之多重存取 系統。該等多重存取系統之實例包含分碼多重存取(cdma) 系統、分時多重存取(丽句系統、分頻多重存取(fdma) 糸統、正交FDma(ofdma)系統及單载波fdma(sc fdma) 糸統。 夕重存取系統可利用諸如分碼多工(cdm)、分時多工 (TDM)等的-或多個多工機制。系統可經採用且可词服現 存的終端機。此等多重存取系統可習知地包含在傳輸中佔 用-或多個槽之封包。可需要改良系統之效能,同時保持 對於現存終端機之回溯相容性(backward⑺叫祕吻)。 舉例而吕’可需要採用諸如多入多出(MIM〇)及分域多重 存取(SDMA)之空間技術來藉由開拓使用多個天線所提供 之額外空間維度來改良通量及/或可靠性。 因此,在此項技術中存在對可支援佔用一個以下之習知 槽之封包的用於前向鏈路封包之傳輸技術之需要。此外, 存在對可支援空間技術同時保持對現存終端機之回溯相容 性的傳輸技術之需要。 H8974.doc 1336188 【發明内容】 本文中描述用於在無線通信系統中有效地發送且接收資 料之技術。該等技術利用與現存設計回溯相容之槽結構。 該等技術包含發送且接收佔用槽結構之一個以下之全槽的 前向鏈路封包。該等技術亦選擇性地採用正交分頻多工 (OFDM)來有效地支援空間技術及/或其他進階通信技術。 根據一態樣,一存取點包含一接收器、至少一處理器、 耦接至該至少一處理器之記憶體,及一經組態以傳輸輸 出波形之發射器。接收器經組態以自一遠端台接收通道資 訊,且該通道資訊包含ACK/NACK(確認/否定確認)資訊。 至少一處理器經組態以產生一包括至少一槽之輸出波形。 每一槽經分段為兩個半槽,其中至少一半槽包含—封包之 一資料單元。至少一處理器亦經組態以解譯Ack/NACK資 Λ以確定是否應將資料單元重發至遠端台。 根據另一態樣,一終端機裝置包含至少一處理器、一耦 接至該至少一處理器之記憶體,及一用於傳輸包括 ACK/NACK資訊之通道資訊的發射器。至少一處理器經組 態以處理一包括至少一槽之輸入波形。每一槽經分段為兩 個半槽’其中至少一半槽包含一封包之一資料單元。至少 一處理器進一步經組態以處理該資料單元以確定該資料單 元是否準確’且回應於處理該資料單元之結果而產生 ACK/NACK資訊。 根據另一態樣,一通信系統包含以上均已描述之存取點 及終端機,存取點與終端機彼此通信以在一前向鏈路中通 118974.doc 1336188 信輸出波形且在一反向鏈路中通信ACK/N ACK資訊。 根據又一態樣,一方法包含在一存取點處產生一輸出波 形。該輸出波形包含至少一槽。每一槽經分段為兩個半 槽,其中至少一半槽包含一封包之一資料單元。該方法亦 包含:在一終端機處處理該輸出波形以擷取資料單元,及 處理該資料單元以確定該資料單元是否準確。亦藉由終端 機執行回應於處理資料單元之結果而產生ACK/NACK資訊 的過程及傳輸包括ACK/NACK資訊之通道資訊的過程。該 方法亦包含在存取點處解譯ACK/NACK資訊以確定是否應 重發該資料單元。 以下進一步詳細地描述本揭示案之各種態樣及特徵》 【實施方式】 本文中所述之傳輸技術可用於諸如CDMA、TDMA、 FDMA、OFDMA及SC-FDMA系統之各種無線通信系統。 經常可互換地使用術語"系統”及"網路”。CDMA系統可實 施諸如cdma2000、通用地面無線電存取(UTRA)、演進之 UTRA(E-UTRA)等的無線電技術。cdma2000涵蓋IS-2000、IS-95 及 IS-856 標準。UTRA 包含寬頻 CDMA(W-CDMA)及低碼片速率(LCR)。TDMA系統可實施諸如全球 行動通信系統(GSM)之無線電技術。OFDMA系統可實施諸 如長期演進(LTE)、IEEE 802.20、快閃 OFDM(Flash-OFDM) 等的無線電技術。UTRA、E-UTRA、GSM及LTE 描述於來自名為"第三代合作夥伴計劃"(3GPP)之組織的文 獻中。cdma2000描述於來自名為"第三代合作夥伴計劃 118974.doc 1336188 2"(3GPP2)之組織的文獻中。此等各種無線電技術及標準 係此項技術中已知的。 為清晰起見,以下對於實施IS-856之高速率封包資料 (HRPD)系統描述該等技術之各種態樣。HRPD亦被稱作演 進資料最佳化(EV-DO)、資料最佳化(DO)、高資料速率 (HDR)等。經常可互換地使用術語"HRPD"及"EV-DO”。目 前,已標準化HRPD修訂版(Rev.)O、A及B,採用HRPD修 訂版0及A,且正在研發HRPD修訂版C。HRPD修訂版0及A 涵蓋單載波HRPD(lxHRPD)。HRPD修訂版B涵蓋多載波 HRPD且與HRPD修訂版0及A回溯相容。本文中所述之技 術可併入於任何HRPD修訂版中。為清晰起見,在大部分 以下許多描述中使用HRPD術語。 圖1展示一具有多個存取點110及多個終端機120之HRPD 通信系統100。存取點通常為與終端機通信之固定台,且 亦可被稱作基地台、節點B等。每一存取點110為一特別地 理區域提供通信覆蓋,且支援位於覆蓋區域内之終端機之 通信。存取點11 〇可耦接至一為此等存取點提供協調及控 制之系統控制器130。系統控制器130可包含諸如基地台控 制器(BSC)、封包控制功能(PCF)、封包資料伺服節點 (PDSN)等的網路實體。 終端機120可分散於整個系統中,且每一終端機可為固 定或行動終端機。終端機亦可被稱作存取終端機、行動 台、使用者裝備(user equipment)、用戶單元、台等。終端 機可為蜂巢式電話、個人數位助理(PDA)、無線設備 118974.doc Y ⑻deV1Ce)、掌上型設備、無線數據機、膝上型電腦 等、、端機可支援任何抓⑽修訂版。在中,終端機 可在任何給;t時刻卜存取點接收前向鏈路上之傳輸,且 可在反向鏈路上將傳輸發送至―或多個存取點。前向鍵路 (或下行鏈路)係指自存取點至終端機之通信鏈路,且反向 鏈路(或上行鏈路)係指自終端機至存取點之通信鏈路。 圖2展不支援HRPD中前向鏈路上iCDM的單載波槽結 構200傳輸時間線經分割為若干個槽。每一槽具有1 gw 毫秒(ms)之持續時間且跨越2〇48個碼片。對於1 2288百萬 碼片/秒(MCps)之竭片速率,每一碼片具有8138奈秒㈣之 持續時間。每一槽經分割為兩個相同的半槽。每一半槽包 ^⑴耗用區段(overhead segment),其包括在半槽中心 處之導頻區段(pilot segment)及在導頻區段兩側上之兩個 媒體存取控制(MAC)區段;及(丨卩兩個訊務區段,其在該耗 用區段兩側上。訊務區段亦可被稱作訊務通道區段、資料 區段、資料域等。導頻區段載運導頻且具有96碼片之持續 時間。每一 MAC區段載運信號(例如,反向功率控制(Rpc) 資訊)且具有64碼片之持續時間。每一訊務區段載運訊務 鞅料(例如,用於特又終端機之單播(unicast)資料、廣播資 料等)且具有400碼片之持續時間。 HRPD修訂版0、A及B對在訊務區段中發送之資料使用 CDM。一訊務區段可載運用於由一存取點伺服之一或多個 終端機的CDM資料。可基於編碼及調變參數來處理用於該 終端機之訊務資料以產生資料符號,該等編碼及調變參數 I18974.doc -10· 1336188 係根據自每一終端機接收到之通道反饋所確定。可解多工 用於該或該等終端機之資料符號且用16碼片之沃爾什函數 (Walsh function)或碼覆蓋該等資料符號以產生用於訊務區 段之CDM資料。因此使用沃爾什函數在時域中產生CDM 資料。CDM訊務區段係載運CDM資料之訊務區段。 可需要對在訊務區段中發送之資料使用OFDM及/或單載 波分頻多工(SC-FDM)。OFDM及SC-FDM將可用頻寬分割 為多個正交副載波,其亦被稱作音調、區間(bin)等。可用 資料來調變每一副載波。一般而言,藉由OFDM在頻域中 發送調變符號及藉由SC-FDM在時域中發送調變符號。 OFDM及SC-FDM具有某些所要的特性,諸如易於對抗由 頻率選擇性衰落引起之符號間干擾(ISI)的能力。OFDM亦 可有效地支援ΜΙΜΟ及SDMA,ΜΙΜΟ及SDMA可獨立地應 用於每一副載波上且可因此在頻率選擇通道中提供良好的 效能。為清晰起見,以下描述使用OFDM來發送資料。 可需要支援OFDM,同時保持與HRPD修訂版0、A及B之 回溯相容性。在HRPD中,導頻區段及MAC區段可在任何 時間由所有作用中終端機予以解調變,而訊務區段僅可由 被伺服之終端機予以解調變。因此,可藉由保持導頻及 MAC區段且修改訊務區段而達成回溯相容性。可藉由以具 有400碼片或更少之總持續時間的一或多個OFDM符號替換 一給定的400碼片之訊務區段中之CDM資料而在一 HRPD波 形中發送OFDM資料。 圖3A展示一支援HRPD中之OFDM之單載波槽結構300。 1 l8974.doc 11 為簡單起見,圖3A中僅展示一個半槽。該半槽包含:(i) 一 耗用區段,其包括一在半槽中心處之96碼片之導頻區段及 在該導頻區段兩側上之兩個64碼片之MAC區段;及(ii)兩 個訊務區段,其在該耗用區段兩側上。一般而言,每一訊 務區段可載運一或多個OFDM符號。在圖3A中所示之實例 中,每一訊務區段載運兩個OFDM符號,且每一OFDM符 號具有200碼片之持續時間且係在一個為200碼片之OFDM 符號週期中予以發送。 圖3B展示一支援HRPD中之CDM及OFDM之單載波槽結 構302。一半槽包含:⑴一耗用區段,其包括一 96碼片之 導頻區段及兩個64碼片之MAC區段,及(ii)兩個訊務區 段,其在該耗用區段兩側上。在一設計中,可為每一訊務 區段選擇CDM或OFDM。在此設計中,在選擇CDM時,每 一訊務區段可載運CDM資料,或在選擇OFDM時,每一訊 務區段可載運一或多個OFDM符號。在其他設計中,一訊 務區段可載運CDM資料與OFDM資料。舉例而言,一訊務 區段可在該訊務區段之一半中載運CDM資料且在該訊務區 段之另一半中載運一或多個OFDM符號。 一般而言,可基於各種OFDM符號數字學(numerology) 或設計而產生OFDM符號。每一 OFDM符號數字學與有關 的參數(諸如OFDM符號持續時間、副載波之數目、循環前 置項長度等)之特定值相關聯。OFDM符號持續時間應為 400碼片訊務區段之整數除數(integer divisor)以便充分利 用訊務區段。此外,OFDM符號之樣本速率應為CDM資料 118974.doc 12 1336188 之碼片速率的整數倍,以便簡化在存取點及終端機處之處 理。 列出用於HRPD之三個實例OFDM符號數字學。此等數 字學經選擇以與HRPD槽結構及碼片速率相容,以使得⑴ 在一訊務區段中發送整數數目之OFDM符號且(ii)OFDM符 號之樣本速率為CDM資料之碼片速率的整數倍。該等數字 學進一步經選擇以致副載波之總數目(其確定離散傅立葉 變換(DFT)大小)允許有效產生OFDM符號。對於此等數字 學,副載波之總數目並非2的冪而是具有小的質因數。舉 例而言,可以2、3、3及5之質因數獲得90個副載波。小的 質因數可允許有效的混合基數快速傅立葉變換(FFT)實施 以產生OFDM符號。 表1中所示之數字學允許在HRPD前向鏈路波形中有效嵌 入OFDM資料。 表1 參數 正常OFDM符號數 字學1 正常OFDM符號數 字學2 正常OFDM符號數 字學3 單位 樣本速率 1·2288χ« 1.2288χ« 1.2288χη Msps 副載波之數 i 9〇χ« 18〇xaj 36〇x/7 副載波間距 13.65333.. 6.82666.. 3.41333.. KHz 有用部分 90 (73.2421875 με) 180 (146.484375 μβ) 360 (292.96875 μβ) 碼片 循環前置項 長度 7.5 («6.10 με) 16 («13.02 μδ) 36 («29.30 με) 碼片 窗口化之保 護時間 2.5 (»2.03 ps) 4 («3.26 με) 4 («3.26 μ$ 碼片 OFDM符號 持續時間 100 («81.38 με) 200 («162.76 ps) 400 (»325.52 μδ) 碼片 表1中之任何OFDM符號數字學可用來以OFDM資料替換 118974.doc •13· 1336188 訊務區段中之CDM資料。 此等OFDM符號數字學提供關於都蔔勒擴展(D〇ppler spread)及多路徑延遲容許度的不同取捨。數字學1與數字 學2及3相比具有最大的副載波間距及最短的循環前置項。 因此,數字學1可提供更佳的都萄勒容許度(歸因於較大的 副載波間距)且可以較低的延遲容許度(歸因於較短的循環 刖置項)為代彳貝致能南速車輛通道中之高頻譜效率。數字 學3與數字學1及2相比具有最小的副載波間距及最長的循 環前置項。因此,數字學3可提供較低的都蔔勒容許度(歸 因於較小的副載波間距)但較高的延遲容許度(歸因於較長 的循環前置項),其可致能在大的多路徑延遲(諸如由中繼 器誘發之多路徑延遲)存在之情況下的高頻譜效率。 其他OFDM符號數字學亦可用於訊務區段。一般而言, OFDM符號數字學可經選擇以致:(i)〇FDM符號持續時間 及樣本速率分別與HRPD槽格式及碼片速率相容,且 (ii)DFT大小允許有效0FDM符號產生。此可隨後允許以有 效且回溯相容之方式用〇FDM資料替換HRpD前向鏈路波 形中之CDM資料。在每一訊務區段中可用〇FDM資料選擇 性地替換CDM資料。可為了回溯相容性而保持耗用區段。 在一設計中,一固定之〇FDM符號數字學係用於載運 OFDM資料之所有訊務區段。終端機可先驗地已知此 OFDM符號數字學且可能夠解調變〇FDM資料而無需關於 數字學之任何信號傳輸。 在另β又什中,可組態之OFDM符號數字學可用於一載 118974.doc •14· 運0FDMf料之給定訊務區段。可支援-組數字學(例如, 列於表1中之數字學)。 不同數字學可用於不同終端機。可基於每一終端機之通 道條件為該終端機選擇一適合之數字學。舉例而言,數字 學1可用於高速行進之終端機,數字學3可用於具有大的多 路徑延遲擴展之終端機,且數字學2可用於具有中等速度 及/或中等多路徑延遲擴展之終端機。 圖4展示一支援HRPD中之cdm之多載波槽結構400。在 HRPD修訂版b中,多個1 xhrpd波形可在頻域中經多工以 獲得一填補一給定頻譜配置之多載波HRPD波形。在圖4中 所示之實例中,用於三個HRPD載波1、2及3之三個 1 xHRPD波形在5 MHz頻譜配置中經頻率多工。每— lxHRPD波形係為了 一不同載波產生且佔用大致125 MHz。三個lxHRPD波形佔用大致3x1.25 = 3.75 MHz,其可 在5 MHz頻譜配置之兩個邊緣處留下相對大之保護帶。 HRPD中並未規定相鄰載波之間的間距但通常選擇該間距 以在相鄰的lxHRPD波形之間提供小的過渡帶。 如圖4中所示,多載波HRPD波形包含用於每一半槽中之 三個載波的三個耗用區段及六個訊務區段。如圖4中所 示,每一訊務區段可載運CDM資料。多載波HRPD波形中 的每一訊務區段中之CDM資料可由OFDM資料選擇性地替 換。此外,多載波HRPD波形中之訊務及耗用區段可經排 列以有效地利用頻譜配置。 圖5展示一支援HRPD中之CDM及OFDM之多載波槽結構 118974.doc •15· 1336188 5 00。在圖5中所示之實例中,在5 MHz頻譜配置中發送三 個HRPD載波且盡可能緊密地間隔該·等載波以便改良頻寬 利用。對於每一 HRPD載波,每一半槽包含:⑴一耗用區 段,其包括導頻區段及MAC區段;及(ii)兩個訊務區段, 其在該耗用區段兩側上。HRPD載波1包含在耗用區段左側 及右側之訊務區段(TS) la及lb,HRPD載波2包含在耗用區 段左側及右側之訊務區段2a及2b,且HRPD載波3包含在耗 用區段左侧及右側之訊務區段3a及3b。用於每一 HRPD載 波之每一訊務區段可載運CDM資料或OFDM資料。 對於5 MHz頻譜配置中之3載波HRPD,如圖5中所示, 可以4x1.2288=4.9152 Mcps〇=4)之樣本速率產生OFDM符 號。OFDM符號於是可佔用5 MHz頻譜配置的大部分。或 者,可以3 X 1.2288 = 3.6864 Mcps(«=3)之樣本速率產生 OFDM符號,其未展示於圖5中。 可在一訊務時間間隔中為每一 OFDM符號週期產生一 OFDM符號。每一 OFDM符號週期在表1中之OFDM符號數 字學2的情況下為200碼片。 OFDM符號可在(i)對應於用於OFDM之訊務區段的副載 波及(ii)在頻譜配置之兩個邊緣處的剩餘可用副載波上載 運OFDM資料。亦可使OFDM符號在對應於具有CDM資料 之訊務區段的副載波上為空值。OFDM符號可因此載運可 選擇性地替換用於零或多個HRPD載波之零或多個訊務區 段中之CDM資料的OFDM資料。OFDM允許對5 MHz頻譜 配置中之可用頻譜的更佳利用。 H8974.doc -16- 1336188 可基於諸如用於CDM之脈衝成形濾波器、產生CDM資 料及/或OFDM資料之方式等的各種因素而選擇HRPD載波 之間的間距。可在頻譜配置之兩個邊緣處使用保護副載 波,該等保護副載波為不具有傳輸之副載波。可基於混附 發射(spurious emission)要求及/或其他因素而選擇在帶邊 緣處之保護副載波之數目。 圖6展示一支援HRPD中之CDM及OFDM且更充分地利用 可用頻寬之多載波槽結構600。槽結構600包含圖5中之槽 結構500中的所有訊務區段及耗用區段。槽結構600進一步 包含在未用於224碼片之耗用時間間隔中之導頻區段或 MAC區段之頻譜部分中的OFDM資料。 可為涵蓋導頻區段及MAC區段之224碼片之耗用時間間 隔界定額外的OFDM符號數字學。此等數字學可經選擇以 致(i)可在耗用時間間隔中發送整數數目個OFDM符號且 (ii)OFDM符號之樣本速率為碼片速率之整數倍。列出用於 耗用時間間隔之兩個實例OFDM符號數字學。在耗用時間 間隔中發送之OFDM符號被稱作"長"OFDM符號,因為其 持續時間比在表1中之對應數字學的情況下在訊務時間間 隔中發送之"正常"OFDM符號的持續時間長。 表2 參數 長OFDM符號數 字學1 長OFDM符號數 字學2 單位 樣本速率 1.2288χη 1.2288χ” Msps 副載波之數目 10〇χ« 20〇xn 副載波間距 12.288.. 6.144.. KHz 有用部分 100 (=81.38 as) 200 (-162.76 μ8) 碼片 118974.doc 17 循環前置項長度 8 0=6.51 ps) 20 (-16.28 ^s) 碼片 窗口化之保護時 間 4 (-3.26 μβ) 4 (二3.26 ps) 碼片 ◦FDM符號持續 時間 112 (-91.15 με) 224 (=182.29 ps 碼片 1336188 其他OFDM符號數字學亦可用於耗用時間間隔。一般而 言,OFDM符號數字學可經選擇以致(i)OFDM符號持續時 間及樣本速率分別與HRPD槽格式及碼片速率相容,且 (ii)DFT大小允許有效OFDM符號產生。 如以下所述,可在耗用時間間隔中為每一 OFDM符號週 期產生一 OFDM符號。OFDM符號可在對應於頻寬之未用 於導頻區段及MAC區段之部分之副載波中載運OFDM資 料。可使OFDM符號在對應於導頻區段及MAC區段之副載 波上為空值。可藉由在耗用時間間隔中使用一或多個長 OFDM符號來改良總頻譜利用。 在圖5及6中所示之設計中,可為訊務區段界定四個邏輯 通道Chi、Ch2、Ch3及Ch4。此等邏輯通道亦可被稱作資 料通道、訊務通道等。邏輯通道Chi可包含在HRPD載波1 上發送之訊務區段la及lb,邏輯通道Ch2可包含在HRPD載 波2上發送之訊務區段2a及2b,邏輯通道Ch3可包含在 HRPD載波3上發送之訊務區段3 a及3b,且邏輯通道Ch4可 包含在剩餘可用頻譜上發送之訊務區段4a、4b及4c。邏輯 通道Chi、Ch2及Ch3因此對應於分別與HRPD載波1、2及3 重疊之副載波。邏輯通道Chi、Ch2及Ch3可在每一槽、每 一半槽等中在CDM與OFDM之間切換。邏輯通道Ch4不具 有相關聯之HRPD載波且可用以改良頻寬利用。邏輯通道 118974.doc •18· 13361881336188 IX. INSTRUCTIONS: TECHNICAL FIELD OF THE INVENTION The present disclosure relates generally to communications, and more particularly to transmission techniques for wireless communication systems. [Prior Art] A wireless communication system is widely used to provide various communication services such as voice, video, packet information, message transmission, broadcasting, and the like. Such systems may be multiple access systems capable of supporting multiple users by sharing available system resources. Examples of such multiple access systems include a code division multiple access (cdma) system, time-sharing multiple access (Phase system, frequency division multiple access (fdma) system, orthogonal FDma (ofdma) system, and single carrier Fdma(sc fdma) 。. The re-access system can utilize - or multiple multiplex mechanisms such as code division multiplexing (cdm), time division multiplexing (TDM), etc. The system can be adopted and can be used as an existing one. Terminals. These multiple access systems may conventionally include packets occupying - or multiple slots in transmission. It may be desirable to improve the performance of the system while maintaining backward compatibility with existing terminals (backward (7) called secret kisses). For example, Lu's need to use space technologies such as Multiple Input Multiple Output (MIM〇) and Multiple Domain Multiple Access (SDMA) to improve throughput by exploiting the additional spatial dimensions provided by multiple antennas. Or reliability. Therefore, there is a need in the art for a transmission technique for forward link packets that can support packets occupying one of the following conventional slots. In addition, there is support for space technology while maintaining the existing Backhaul compatibility transmission of terminal The need for technology. H8974.doc 1336188 SUMMARY OF THE INVENTION Techniques for efficiently transmitting and receiving data in a wireless communication system are described herein. The techniques utilize slot structures that are compatible with existing design tracebacks. And receiving a full-slot forward link packet occupying one or less of the slot structure. The techniques also selectively employ orthogonal frequency division multiplexing (OFDM) to effectively support spatial techniques and/or other advanced communication techniques. According to one aspect, an access point includes a receiver, at least one processor, a memory coupled to the at least one processor, and a transmitter configured to transmit an output waveform. The receiver is configured to self A remote station receives channel information, and the channel information includes ACK/NACK (acknowledgement/negative acknowledgement) information. At least one processor is configured to generate an output waveform comprising at least one slot. Each slot is segmented into two One half of the slots, at least one of which contains one of the data units of the packet. At least one processor is also configured to interpret the Ack/NACK resource to determine whether the data unit should be retransmitted to the remote station. In another aspect, a terminal device includes at least one processor, a memory coupled to the at least one processor, and a transmitter for transmitting channel information including ACK/NACK information. Configuring to process an input waveform comprising at least one slot. Each slot is segmented into two half slots, at least one of which includes a data unit of one packet. At least one processor is further configured to process the data unit Determining whether the data unit is accurate 'and generating ACK/NACK information in response to processing the data unit. According to another aspect, a communication system includes the access points and terminals described above, the access point and The terminals communicate with each other to pass the 118974.doc 1336188 signal output waveform in a forward link and communicate ACK/N ACK information in a reverse link. According to yet another aspect, a method includes generating an output waveform at an access point. The output waveform contains at least one slot. Each slot is segmented into two half slots, at least half of which contain a data unit of one packet. The method also includes processing the output waveform at a terminal to retrieve the data unit, and processing the data unit to determine whether the data unit is accurate. The process of generating ACK/NACK information in response to the result of processing the data unit and the process of transmitting channel information including ACK/NACK information are also performed by the terminal. The method also includes interpreting the ACK/NACK information at the access point to determine if the data unit should be retransmitted. Various aspects and features of the present disclosure are described in further detail below. [Embodiment] The transmission techniques described herein are applicable to various wireless communication systems such as CDMA, TDMA, FDMA, OFDMA, and SC-FDMA systems. The terms "system" and "network" are often used interchangeably. The CDMA system can implement radio technologies such as cdma2000, Universal Terrestrial Radio Access (UTRA), Evolved UTRA (E-UTRA), and the like. Cdma2000 covers the IS-2000, IS-95, and IS-856 standards. UTRA includes Wideband CDMA (W-CDMA) and Low Chip Rate (LCR). A TDMA system can implement a radio technology such as the Global System for Mobile Communications (GSM). The OFDMA system can implement radio technologies such as Long Term Evolution (LTE), IEEE 802.20, Flash OFDM, and the like. UTRA, E-UTRA, GSM, and LTE are described in a document from an organization named "3rd Generation Partnership Project" (3GPP). Cdma2000 is described in documents from an organization named "3rd Generation Partnership Project 118974.doc 1336188 2" (3GPP2). These various radio technologies and standards are known in the art. For the sake of clarity, the following describes various aspects of such techniques for implementing the High Rate Packet Data (HRPD) system of IS-856. HRPD is also known as Evolution Data Optimization (EV-DO), Data Optimization (DO), and High Data Rate (HDR). The terms "HRPD" and "EV-DO" are often used interchangeably. Currently, HRPD revisions (Rev.) O, A and B have been standardized, HRPD revisions 0 and A have been adopted, and HRPD revision C is being developed. HRPD Revisions 0 and A cover single-carrier HRPD (lxHRPD). HRPD Revision B covers multi-carrier HRPD and is compatible with HRPD Revision 0 and A backtracking. The techniques described herein can be incorporated into any HRPD revision. For clarity, the HRPD terminology is used in most of the following descriptions. Figure 1 shows an HRPD communication system 100 having multiple access points 110 and a plurality of terminals 120. The access point is typically in communication with the terminal. Fixed stations, and may also be referred to as base stations, Node B, etc. Each access point 110 provides communication coverage for a particular geographic area and supports communication of terminals located within the coverage area. Access point 11 Connected to a system controller 130 that provides coordination and control for such access points. System controller 130 may include, for example, a base station controller (BSC), a packet control function (PCF), a packet data servo node (PDSN), and the like. Network entity. Terminal 120 can be dispersed throughout In the system, each terminal can be a fixed or mobile terminal. The terminal can also be called an access terminal, a mobile station, a user equipment, a subscriber unit, a station, etc. The terminal can be a hive. Telephone, personal digital assistant (PDA), wireless device 118974.doc Y (8) deV1Ce), handheld device, wireless data machine, laptop, etc., the terminal can support any scratch (10) revision. In the terminal, the terminal can The access point receives the transmission on the forward link at any time; and the transmission can be sent to the "or multiple access points" on the reverse link. The forward key (or downlink) refers to Access point to the communication link of the terminal, and the reverse link (or uplink) refers to the communication link from the terminal to the access point. Figure 2 does not support the iCDM single on the forward link in HRPD The carrier slot structure 200 transmission timeline is divided into slots. Each slot has a duration of 1 gw milliseconds (ms) and spans 2 〇 48 chips. For 1 2288 million chips per second (MCps) The chip rate, each chip has a duration of 8138 nanoseconds (four). It is two identical half slots. Each half slot contains (1) an overhead segment, which includes a pilot segment at the center of the half slot and two on both sides of the pilot segment. Media access control (MAC) segments; and (two traffic segments, which are on either side of the consumption segment. The traffic segment may also be referred to as a traffic channel segment, a data region Segment, data field, etc. The pilot segment carries the pilot and has a duration of 96 chips. Each MAC segment carries a signal (e.g., reverse power control (Rpc) information) and has a duration of 64 chips. Each traffic segment carries traffic information (e.g., unicast data for broadcasts, terminal broadcasts, etc.) and has a duration of 400 chips. HRPD Revisions 0, A, and B use CDM for materials sent in the Traffic Zone. A traffic segment can carry CDM data for one or more terminals served by an access point. The data symbols for the terminal can be processed based on the encoding and modulation parameters to generate data symbols. The encoding and modulation parameters I18974.doc -10· 1336188 are based on the channel feedback received from each terminal. determine. The multiplexable data symbol for the terminal or the terminals is overwritten with a 16-chip Walsh function or code to generate CDM data for the traffic segment. Therefore, the Walsh function is used to generate CDM data in the time domain. The CDM Traffic Zone is the traffic section that carries CDM data. It may be desirable to use OFDM and/or Single Carrier Frequency Division Multiplexing (SC-FDM) for data transmitted in the traffic section. OFDM and SC-FDM partition the available bandwidth into a plurality of orthogonal subcarriers, which are also referred to as tones, bins, and the like. The data can be used to modulate each subcarrier. In general, modulation symbols are transmitted in the frequency domain by OFDM and modulated symbols are transmitted in the time domain by SC-FDM. OFDM and SC-FDM have certain desirable characteristics, such as the ability to easily combat inter-symbol interference (ISI) caused by frequency selective fading. OFDM can also effectively support ΜΙΜΟ and SDMA, and SDMA can be applied independently to each subcarrier and can therefore provide good performance in the frequency selective channel. For clarity, the following description uses OFDM to transmit data. It may be necessary to support OFDM while maintaining backward compatibility with HRPD revisions 0, A, and B. In HRPD, the pilot and MAC segments can be demodulated by all active terminals at any time, and the traffic segments can only be demodulated by the servoed terminal. Therefore, backtracking compatibility can be achieved by maintaining the pilot and MAC segments and modifying the traffic segments. The OFDM data may be transmitted in an HRPD waveform by replacing the CDM data in a given 400 chip traffic segment with one or more OFDM symbols having a total duration of 400 chips or less. 3A shows a single carrier slot structure 300 that supports OFDM in HRPD. 1 l8974.doc 11 For the sake of simplicity, only one half slot is shown in Figure 3A. The half slot includes: (i) a consumable segment including a 96-chip pilot segment at the center of the half slot and two 64-chip MAC regions on either side of the pilot segment And (ii) two traffic segments on either side of the consumable segment. In general, each traffic segment can carry one or more OFDM symbols. In the example shown in Figure 3A, each traffic segment carries two OFDM symbols, and each OFDM symbol has a duration of 200 chips and is transmitted in an OFDM symbol period of 200 chips. Figure 3B shows a single carrier slot structure 302 that supports CDM and OFDM in HRPD. The half slot includes: (1) a consumption segment including a 96-chip pilot segment and two 64-chip MAC segments, and (ii) two traffic segments in the consumption zone On both sides of the segment. In one design, CDM or OFDM can be selected for each traffic segment. In this design, each CDC data can be carried by each of the traffic segments when CDM is selected, or one or more OFDM symbols can be carried by each of the traffic segments when OFDM is selected. In other designs, a traffic segment can carry CDM data and OFDM data. For example, a traffic segment can carry CDM data in one half of the traffic segment and carry one or more OFDM symbols in the other half of the traffic segment. In general, OFDM symbols can be generated based on various OFDM symbol numerologies or designs. Each OFDM symbol is digitally associated with a particular value of a related parameter, such as OFDM symbol duration, number of subcarriers, loop preamble length, and the like. The OFDM symbol duration should be an integer divisor of the 400 chip traffic segment in order to fully utilize the traffic segment. In addition, the sample rate of the OFDM symbol should be an integer multiple of the chip rate of the CDM data 118974.doc 12 1336188 to simplify the handling at the access point and the terminal. Three example OFDM symbolic digits for HRPD are listed. These digital studies are selected to be compatible with the HRPD slot structure and chip rate such that (1) an integer number of OFDM symbols are transmitted in a traffic segment and (ii) the sample rate of the OFDM symbol is the chip rate of the CDM data. Integer multiple. The digits are further selected such that the total number of subcarriers (which determines the discrete Fourier transform (DFT) size) allows efficient generation of OFDM symbols. For these digits, the total number of subcarriers is not a power of two but a small prime factor. For example, 90 subcarriers can be obtained with a quality factor of 2, 3, 3, and 5. A small prime factor may allow for efficient mixed base fast Fourier transform (FFT) implementation to produce OFDM symbols. The numerology shown in Table 1 allows for the efficient embedding of OFDM data in the HRPD forward link waveform. Table 1 Parameter Normal OFDM Symbol Digitology 1 Normal OFDM Symbol Digitology 2 Normal OFDM Symbol Digitology 3 Unit Sample Rate 1·2288χ« 1.2288χ« 1.2288χη Msps Number of Subcarriers i 9〇χ« 18〇xaj 36〇x/ 7 Subcarrier spacing 13.65333.. 6.82666.. 3.41333.. KHz Useful part 90 (73.2421875 με) 180 (146.484375 μβ) 360 (292.96875 μβ) Chip loop preamble length 7.5 («6.10 με) 16 («13.02 μδ) 36 («29.30 με) Chip window protection time 2.5 (»2.03 ps) 4 («3.26 με) 4 («3.26 μ$ chip OFDM symbol duration 100 («81.38 με) 200 («162.76 ps) 400 (»325.52 μδ) Chips Any OFDM symbolic digits in Table 1 can be used to replace CDM data in the 118974.doc •13· 1336188 traffic section with OFDM data. These OFDM symbolic digits provide information on Doppler extensions. (D〇ppler spread) and different tolerances for multipath delay tolerance. Digital 1 has the largest subcarrier spacing and the shortest cyclic preamble compared to digital 2 and 3. Therefore, Digital 1 can provide better Duller tolerance (attributable to Subcarrier spacing) and lower delay tolerance (due to shorter cyclical terms) is the high spectral efficiency in the submarine-enabled south speed vehicle channel. Digital Studies 3 and Digital Studies 1 and 2 Compared to having the smallest subcarrier spacing and the longest cyclic preamble. Therefore, Digital 3 can provide lower Doppler tolerance (due to smaller subcarrier spacing) but higher delay tolerance ( Due to the longer cyclic preamble), it can enable high spectral efficiency in the presence of large multipath delays (such as multipath delays induced by repeaters). Other OFDM symbolic digits can also be used. In the traffic segment. In general, OFDM symbolic digitization can be selected such that: (i) 〇 FDM symbol duration and sample rate are compatible with HRPD slot format and chip rate, respectively, and (ii) DFT size allows for validity 0FDM symbol generation. This can then be used to replace CDM data in the HRpD forward link waveform with 〇FDM data in a valid and backwards compatible manner. Selectively replace CDM data with 〇FDM data in each traffic segment For backward compatibility Consumption holding section. In one design, a fixed number of symbols 〇FDM Department for all segments carrying OFDM TVM information purposes. The terminal can know this OFDM symbolic digits a priori and can demodulate the transformed FDM data without any signal transmission with respect to digital. In another beta, configurable OFDM symbolic digits can be used for a given traffic segment of the FF. Supportable - group digits (for example, the numbers listed in Table 1). Different digital studies can be used for different terminals. A suitable digital science can be selected for the terminal based on the channel conditions of each terminal. For example, Digital 1 can be used for high speed traveling terminals, Digital 3 can be used for terminals with large multipath delay spread, and Digital 2 can be used for terminals with medium speed and/or medium multipath delay spread. machine. 4 shows a multi-carrier slot structure 400 that supports cdm in HRPD. In HRPD Revision b, multiple 1 xhrpd waveforms can be multiplexed in the frequency domain to obtain a multi-carrier HRPD waveform that fills a given spectrum configuration. In the example shown in Figure 4, the three 1 x HRPD waveforms for the three HRPD carriers 1, 2, and 3 are frequency multiplexed in a 5 MHz spectrum configuration. Each lxHRPD waveform is generated for a different carrier and occupies approximately 125 MHz. The three lxHRPD waveforms occupy approximately 3x1.25 = 3.75 MHz, which leaves a relatively large guard band at the two edges of the 5 MHz spectrum configuration. The spacing between adjacent carriers is not specified in the HRPD but is typically chosen to provide a small transition band between adjacent lxHRPD waveforms. As shown in Figure 4, the multi-carrier HRPD waveform contains three consumption segments and six traffic segments for three of the carriers in each half slot. As shown in Figure 4, each traffic segment can carry CDM data. The CDM data in each of the multi-carrier HRPD waveforms can be selectively replaced by OFDM data. In addition, the traffic and consumption segments in the multi-carrier HRPD waveform can be arranged to efficiently utilize the spectrum configuration. Figure 5 shows a multi-carrier slot structure supporting CDM and OFDM in HRPD. 118974.doc •15· 1336188 5 00. In the example shown in Figure 5, three HRPD carriers are transmitted in a 5 MHz spectrum configuration and the equal-equivalent carriers are spaced as closely as possible to improve bandwidth utilization. For each HRPD carrier, each half slot includes: (1) a consumable segment including a pilot segment and a MAC segment; and (ii) two traffic segments on both sides of the consumable segment . The HRPD carrier 1 is included in the traffic segments (TS) la and lb on the left and right sides of the consumption segment, and the HRPD carrier 2 is included in the traffic segments 2a and 2b on the left and right sides of the consumption segment, and the HRPD carrier 3 includes The traffic sections 3a and 3b on the left and right sides of the consumption section. Each of the traffic segments for each HRPD carrier can carry CDM data or OFDM data. For a 3-carrier HRPD in a 5 MHz spectrum configuration, as shown in Figure 5, an OFDM symbol can be generated at a sample rate of 4x1.2288 = 4.9152 Mcps 〇 = 4). The OFDM symbol can then occupy most of the 5 MHz spectrum configuration. Alternatively, an OFDM symbol can be generated at a sample rate of 3 X 1.2288 = 3.6864 Mcps («=3), which is not shown in FIG. An OFDM symbol can be generated for each OFDM symbol period in a traffic time interval. Each OFDM symbol period is 200 chips in the case of OFDM symbol number 2 in Table 1. The OFDM symbols may carry OFDM data in (i) subcarriers corresponding to the traffic segments for OFDM and (ii) remaining available subcarriers at both edges of the spectral configuration. The OFDM symbol can also be made to have a null value on the subcarrier corresponding to the traffic segment having the CDM data. The OFDM symbols can thus carry OFDM data that can selectively replace CDM data for zero or more traffic segments of zero or more HRPD carriers. OFDM allows for better utilization of the available spectrum in a 5 MHz spectrum configuration. H8974.doc -16- 1336188 may select the spacing between HRPD carriers based on various factors such as the pulse shaping filter for CDM, the manner in which CDM data is generated, and/or the OFDM data. The guard subcarriers can be used at both edges of the spectrum configuration, and the guard subcarriers are subcarriers that do not have transmission. The number of guard subcarriers at the edge of the strip can be selected based on spurious emission requirements and/or other factors. 6 shows a multi-carrier slot structure 600 that supports CDM and OFDM in HRPD and more fully utilizes available bandwidth. The trough structure 600 includes all of the traffic segments and consumable segments in the trough structure 500 of FIG. The slot structure 600 further includes OFDM data in a portion of the spectrum of the pilot or MAC segments that are not used in the elapsed time interval of 224 chips. Additional OFDM symbolic digits may be defined for the elapsed time interval covering the 224 chips of the pilot and MAC segments. Such numerology may be selected such that (i) an integer number of OFDM symbols can be transmitted in the elapsed time interval and (ii) the sample rate of the OFDM symbol is an integer multiple of the chip rate. Two examples of OFDM symbolic digitization for the time interval are listed. The OFDM symbol transmitted in the elapsed time interval is referred to as the "long" OFDM symbol because its duration is "normal" sent in the traffic interval than in the case of the corresponding digital science in Table 1. The duration of the OFDM symbol is long. Table 2 Parameter Long OFDM Symbol Digitology 1 Long OFDM Symbol Digitology 2 Unit sample rate 1.2288χη 1.2288χ” Msps Number of subcarriers 10〇χ« 20〇xn Subcarrier spacing 12.288.. 6.144.. KHz Useful part 100 (= 81.38 as) 200 (-162.76 μ8) Chip 118974.doc 17 Loop Preamble Length 8 0=6.51 ps) 20 (-16.28 ^s) Chip Windowing Protection Time 4 (-3.26 μβ) 4 (2.26) Ps) Chip ◦ FDM symbol duration 112 (-91.15 με) 224 (=182.29 ps Chip 1336188 Other OFDM symbolic digits can also be used to consume time intervals. In general, OFDM symbolic digitology can be chosen such that (i The OFDM symbol duration and sample rate are compatible with the HRPD slot format and the chip rate, respectively, and (ii) the DFT size allows for efficient OFDM symbol generation. As described below, each OFDM symbol period can be used in the elapsed time interval. Generating an OFDM symbol. The OFDM symbol can carry OFDM data in subcarriers corresponding to a portion of the bandwidth that is not used for the pilot segment and the MAC segment. The OFDM symbol can be corresponding to the pilot segment and the MAC segment. The subcarrier has a null value. One or more long OFDM symbols are used in the elapsed time interval to improve overall spectrum utilization.In the designs shown in Figures 5 and 6, four logical channels Chi, Ch2, Ch3, and Ch4 can be defined for the traffic segment. These logical channels may also be referred to as data channels, traffic channels, etc. The logical channel Chi may include the traffic segments 1a and 1b transmitted on the HRPD carrier 1, and the logical channel Ch2 may include the information transmitted on the HRPD carrier 2. For the traffic segments 2a and 2b, the logical channel Ch3 may include the traffic segments 3a and 3b transmitted on the HRPD carrier 3, and the logical channel Ch4 may include the traffic segments 4a, 4b and 4c transmitted on the remaining available spectrum. The logical channels Chi, Ch2, and Ch3 thus correspond to subcarriers that overlap with the HRPD carriers 1, 2, and 3. The logical channels Chi, Ch2, and Ch3 can be switched between CDM and OFDM in each slot, each half slot, and the like. Logical channel Ch4 does not have an associated HRPD carrier and can be used to improve bandwidth utilization. Logical Channel 118974.doc • 18· 1336188
Ch4亦可經分割為兩個邏輯次通道,例如,下部Ch4及上 部Ch4,且每一邏輯次通道包含一組相連的副載波。可獨 立地排程該等邏輯通道。舉例而言,每一邏輯通道可基於 自用於彼邏輯通道之終端機接收到的通道品質反饋予以排 程。 一般而言,可在一給定頻譜配置中發送任何數目個 HRPD載波。對於每一 HRPD載波,每一訊務區段可載運 CDM資料或OFDM資料。亦可未由HRPD載波使用之剩餘 可用頻譜中發送OFDM資料。 圖7展示一支援用於5 MHz頻譜配置中之單一 HRPD載波 之OFDM及CDM的槽結構700。在圖7中所示之實例中,單 一 HRPD載波位於5 MHz頻譜配置之一邊緣附近。如以上 在圖2至6中所述,在半槽之中心產生且發送用於HRPD載 波之導頻區段及MAC區段。HRPD載波之每一訊務區段可 載運CDM資料或OFDM資料。 一 OFDM頻譜可經界定以包含頻譜配置中之所有可用頻 譜(HRPD載波除外)。在圖7中所示之實例中,OFDM頻譜 包含在HRPD載波兩側上之可用頻譜。正常OFDM符號及 長OFDM符號可經擴展且用以在OFDM頻譜中載運資料。 可以任何方式(例如,使用通常用於僅採用OFDM或 OFDMA之系統中的任何技術)在OFDM頻譜中發送訊務資 料、信號傳輸及導頻。舉例而言,可在任何副載波及符號 週期上以任何方式發送導頻及信號傳輸。亦可將可用之副 載波及符號週期配置給任何數目個終端機,且可以任何方 118974.doc 19 1336188 式將資料發送至已排程之終端機。 在圖7中所示之設計中,界定兩個邏輯通道Ch 1及Ch2 ° 邏輯通道Chi包含在HRPD載波1上發送之訊務區段1a及 lb,且邏輯通道ch2包含在OFDM頻譜上發送之訊務區段 2a至2f。邏輯通道chi可在每一槽、每〆半槽等中在CDM 與OFDM之間切換。邏輯通道Ch2並不限於任何HRPD載波 且可以純OFDM模式予以操作以便僅載運OFDM資料。可 在邏輯通道Ch2上以任何方式用OFDM發送訊務資料、信 號傳輸及/或導頻。 圖8展示一支援5 MHz頻譜配置中之OFDM的HRPD槽結 構800。在圖8中所示之實例中,頻譜配置不含有HRPD載 波。正常OFDM符號及長OFDM符號可用以在整個可用頻 譜(在帶邊緣處之保護次帶除外)中發送資料。邏輯通道 Ch 1可經界定以涵蓋整個可用頻譜。可操作邏輯通道 Chl(仿佛其係用於OFDM/OFDMA系統般)且其可併有來自 諸如快閃 OFDM®、IEEE 802.20、LTE 等的其他 OFDM/ OFDMA技術之設計元素。邏輯通道Chi中之時間頻率資源 可經分割為用於訊務資料之訊務資源、用於信號傳輸之信 號傳輸資源、用於導頻之導頻資源等。信號傳輸資料可用 以排程終端機且指派訊務資源至已排程之終端機。信號傳 輸資料亦可用以促進混合式自動再傳輸(H-ARQ)反饋、功 率控制等。快閃OFDM®、IEEE 802.20 ' LTE及/或其他 OFDM/OFDMA系統之各種結構元件及實體層特徵可用於 邏輯通道Chi。 118974.doc •20- 1336188 圖9展示存取點110及終端機120之一設計之方塊圖,該 存取點及該終端機為圖1中之存取點及終端機中之一者。 為簡單起見,在圖9中僅展示用於在前向鏈路上之傳輸的 處理單元。 在存取點110處,TX CDM/OFDM處理器920如以下所述 接收且處理訊務資料及信號傳輸並提供輸出樣本。發射器 (TMTR)922處理(例如,轉換至類比、放大、過濾及升頻轉 換)輸出樣本且產生經由天線924傳輸之前向鏈路信號。在 終端機120處,天線952自存取點110接收前向鏈路信號且 提供已接收之信號至接收器(RCVR)954。接收器954處理 (例如,過濾、放大、降頻轉換及數位化)已接收之信號且 提供已接收之樣本。RX CDM/OFDM處理器960如以下所 述以與藉由TX CDM/OFDM 920進行之處理互補的方式處 理已接收之樣本,且為終端機120提供經解碼之資料及已 接收之信號傳輸。 控制器930及970分別指導存取點110及終端機120處之操 作。記憶體932及972分別為存取點110及終端機120儲存程 式碼及資料。 圖10展示TX CDM/OFDM處理器920a之方塊圖,該處理 器為圖1中之TX CDM/OFDM處理器920之一設計。處理器 920a包含⑴產生載運CDM資料及耗用資料之CDM波形的 CDM處理器1010及(ii)產生載運OFDM資料之OFDM波形的 OFDM處理器1050。 在CDM處理器1010内,編碼器/交錯器1012接收待使用 118974.doc -21 - 1336188 CDM予以發送之訊務資料’基於_編碼機制而編碼訊務資 料,且交錯(或重排序)已編碼之資料。符號映射器 (mapper)l〇14基於一調變機制而將已交錯資料映射至資料 符號。解多工器(Demux)1〇16將資料符號解多工為多個(例 如,16個)流。沃爾什覆蓋單元1〇18用不同的“碼片之沃 爾什碼覆蓋或通道化每一資料符號流,以獲得一對應之資 料碼片流。求和器1020對用於多個沃爾什碼之多個(例 如,16個)資料碼片流求和且以碼片速率提供CDM資料。 τχ耗用處理器1G22接收用mMAC區段之信號傳輸及用於 導頻區段之導頻資料且以碼片速率為耗用區段產生耗用資 料TDM夕工器(Mux)1024接收來自求和器1〇2〇之CDM資 料及來自處理器1〇22之耗用資料,在載運CDM資料之訊務 區段中提供CDM資料,且在耗用區段中提供耗用資料。乘 法器1026以用於存取點之偽雜訊(pN)序列乘多工器 1024之輸出且以碼片速率提供輸出碼片。脈衝成形濾波器 1028過濾輸出碼片且提供用於一HRpD載波之cdm波形。 可以CDM處理器1〇1〇之多個執行個體產生用於多個HRpD 載波之多個CDM波形。此等多個CDM波形可在數位域或 類比域中經升頻轉換至適當頻率。 在OFDM處理器1050内,編碼器/交錯器1〇52接收待使用 OFDM予α發送之訊務資#,基;^ —編碼機制而編碼訊務 資料,且交錯已編碼之資料。符號映射器1〇54將已交錯之 另料映射至寊料符號。符號至副載波映射器1〇56將資料符 號映射至用於OFDM之副載波。零插入單元1〇58在不用於 118974.doc -22- OFDM之副載波(例如,對應於CDM訊務區段及耗用區段之 副載波、空值副載波及保護副載波)上插入零符號(其具有 信號值零)。離散傅立葉逆變換(IDFT)單元1060對用於每 —OFDM符號週期中之K個總副載波之資料符號及零符號 執行K點IDFT且提供一含有K個時域樣本之有用部分。K取 決於OFDM符號數字學且在表1及2中對於正常OFDM符號 及長OFDM符號給出。循環前置項插入單元1062複製有用 部分之最後C個樣本且將此等C個樣本附加至有用部分之 前部,以便以樣本速率形成一含有K+C個樣本之OFDM符 號。樣本速率可為碼片速率之η倍,其中η可等於1、2、 3、4等。重複部分被稱作循環前置項且用以對抗由頻率選 擇性衰落引起之ISI。窗口化/脈衝成形濾波器1064窗口化 且過濾來自單元1062之樣本且提供一 OFDM波形。求和器 1〇7〇對來自CDM處理器1010之CDM波形及來自OFDM處理 器1050之OFDM波形求和且提供一輸出波形。 圖11展示TX CDM/OFDM處理器920b之方塊圖,該處理 器為圖1中之TX CDM/OFDM處理器920之另一設計。處理 器920b將CDM資料映射至用於CDM之副載波且將OFDM資 料映射至用於OFDM之副載波。處理器920b隨後基於已映 射之CDM資料及OFDM資料而產生一輸出波形。 在處理器920b内,TX CDM處理器1110接收立處理待使 用CDM予以發送之訊務資料、信號傳輸及導頻,且提供輸 出碼片。處理器1110可包含圖1〇中之單元1012至1026。 DFT單元m2對每一 OFDM符號週期中之輸出碼片執行L點 118974.doc •23- 1336188 DFT且提供用於L個副載波之L個頻域符號。L係對應於一 HRPD载波之副載波之數目且可取決於〇fdm符號數宇 學。 編碼器/交錯器1120及符號映射器1122處理待使用〇FDM 予以發送之訊務資料且提供資料符號。符號至副載波映射 器1130將來自DFT單元1Π2之頻域符號映射至用於cdm之 釗載波且進一步將來自符號映射器丨丨22之資料符號映射至 用於OFDM之副載波。零插入單元1132在不用於CDM或 OFDM之副载波(例如,空值及保護副載波)上插入零符 號。IDFT單元1134對用於每一 0Fdm符號週期之K個符號 執行K點1DFT且提供一含有K個時域樣本之有用部分。循 環前置項插入單元丨136將一循環前置項插入至有用部分且 以樣本速率提供一含有K+c個樣本之〇FDM符號。窗口化/ 脈衝成形濾波器1138窗口化且過濾來自單元1136之樣本且 提供一輸出波形。濾波器1138可比圖1〇中之濾波器1〇64提 供較急劇之頻譜衰減,其可允許對頻譜配置之更佳利用。 圖12展示RX CDM/〇fdm處理器960a之方塊圖,該處理 器為圖9中之rx CDM/OFDM處理器960之一設計。處理器 96〇a可用以接收藉由圖10中之TX CDM/OFDM處理器920a 產生之輸出波形。 為恢復CDM資料,濾波器1212自接收器954獲得已接收. 之樣本’過濾已接收之樣本以移除在所關心之HRPD載波 外部之頻譜分量,執行自樣本速率至碼片速率之轉換,且 提供已過濾之碼片。乘法器1214以由存取點使用之PN序列 118974.doc •24· 乘已過濾之碼片且提供耠 由认增μ 、輸入碼片。TDM解多工器ι216提供 用於導頻區段之輸入碼片 八 主通道估計器1218,提 MAC區段之輸入碼片至 ’、5 恭次 耗用處理器,且提供用於 載運CDM貝料之句欲p g 〇 ° °°段的輸入碼片至沃爾什解覆蓋 (decover)單元 1222。 汁器1218基於已接收之導頻而 導出一通道估計。單元122 _ 222解覆盍或解通道化(dechanneiiz 用於母一用於CDM資Μ夕、、本sb νι_ ^ 科之夭爾什碼的輪入樣本且提供已接 收之符號夕H224多ji用於所有沃爾什碼之已接收符 號y身料解調器(Demod)1226以通道估計值對已接收符號 執行相干偵測且提供杳立轴_ 從供貝科符唬估计,該等資料符號估計為 對以CDM發送之資料符號之估計。解交錯器 (^emterleaver)/解碼器1228解交錯且解碼資料符號估計且 提供用於⑽之經解碼資料。RX㈣處理器mo處理用 於MAC區段之輸人碼片且提供已接收之信號傳輸。 為恢復OFDM資料,循環前置項移除單元1252獲得每一 OFDM符號週期中之K+c個已接收之樣本,移除循環前置 項,且提供用於有用部分之K個已接收之樣本。DFT單元 1254對K個已接收之樣本執行〖點DFT且提供用於κ個總副 載波之Κ個已接收之符號。符號至副載波解映射器 (demappe〇1256獲得用於κ個總副載波之已接收之符號, 提供用於用於OFDM之副載波的已接收之資料符號至資料 解調器1258,且可提供已接收之導頻符號至通道估計器 1218。資料解調器1258以來自通道估計器1218之通道估計 對已接收之資料符號執行資料偵測(例如,匹配過濾、等 118974.doc •25· 1336188 化等)且提供資料符號估計,該等資料符號估計係對以 OFDM發送之資料符號之估計。解交錯器/解碼器1260解交 錯且解碼資料符號估計且提供用於OFDM之經解碼資料。 圖13展示RX CDM/OFDM處理器960b之方塊圖,該處理 器為圖9中之RX CDM/OFDM處理器960之另一設計。處理 器960b可用以接收藉由圖11中之TX CDM/OFDM處理器 920b產生之輸出波形。在處理器960b内,循環前置項移除 單元1312獲得每一 OFDM符號週期中之K+C個已接收之樣 本,移除循環前置項,且提供用於有用部分之K個已接收 之樣本。0?丁單元1314對1<:個已接收之樣本執行1^點0?丁且 提供用於K個總副載波之K個已接收之符號。符號至副載 波解映射器13 16獲得用於K個總副載波之已接收之符號, 提供用於用於CDM之副載波的已接收之符號至IDFT單元 1320,且提供用於用於OFDM之副載波的已接收之符號至 資料解調器1330。 為恢復CDM資料,IDFT單元1320對一 OFDM符號週期中 用於用於CDM之副載波的L個已接收之符號執行L點IDFT 且提供L個時域樣本^ RX CDM處理器1322處理時域樣本 且提供已接收之信號傳輸及用於CDM之經解碼資料。處理 器13 22可包含圖12中之單元1214至1228。為恢復OFDM資 料,資料解調器1330以一通道估計對來自解映射器13 16之 已接收之符號執行資料偵測且提供資料符號估計》解交錯 器/解碼器1332解交錯且解碼資料符號估計且提供用於 OFDM之經解碼資料〇 118974.doc -26 - 為凊晰起見,已對於在HRPD系统中以CDM及0FDM進 仃之别向鏈路傳輸特定地描述技術之各種態樣。該等技術 亦可用於夕工機制之其他組合,諸如及sc_FDM、 CDM及TDM及〇FDM、TDM及〇FDM等。該等技術亦可用 於其他無線通信系統且用於前向鏈路與反向鏈路。 在無線系統中,保證每一單個傳輸上之可靠的資料封包 傳遞可能效率低下。效率低下在基本通道條件自—傳輸至 另一傳輸激烈變化之系統中尤其明顯。舉例而言,在 OFDM系統中,在訊框/封包之間可能存在已接枚之信雜比 (SNR)之廣泛變化,從而使得保證每一封包傳輸之小訊框 誤差率(FER)係困難且效率低下的。該困難及效率低下亦 適用於採用包含(但不限於)TDMA、FDMA及CDM等的正 交多重存取技術之其他通信系統。 在該等通信系統中,諸如自動再傳輸/重複請求(ARQ)程 序之封包再傳輸機制可用以幫助減少此種效率低下。然 而,ARQ程序可能會引起較高的封包潛時,因為每一封包 可能平均要花費較長的時間才能通過β 一般而言,大的封 包潛時對於資料訊務而言可能並非顯著問題,但對於語音 訊務或需要資訊傳輸中之低潛時的其他類型之應用而言可 能係不利的。此外,預期封包傳輸潛時會隨系統中之使用 者之數目不斷增長而增加。因此,為改良系統容量(例 如’基於系統通量或同時使用系統之使用者之數目等), 應使傳輸潛時保持低或小。ARQ通常包含一確認/否定確 認(ACK/NACK)信號’其用以指示終端機是否已成功接收 118974.doc -27- 1336188 -封包。作為-非限制性實例,終端機 二檢查:的檢查演算法(諸如雜凑函數二:: 之封…此種雜凑函數係循環 c成功地評估,㈣以之所有位元係 可發出一指示終端機不需要封包重發之ACKe若CRC = 破地評估,則可能並非封包中 可*+ ;…々 匕中之所有位元均正確且終端機 了發出一各不終端機需要封包重發之NACKe 使用在前向鍵路上之封包傳輸,該傳輸 s 知Μ向鏈路巾所❹之全槽。半槽傳輸致 L之較大粒度及(結果)對於成功傳輸較小封包之 較大機會。雖然潛時可能相同,但較小粒度意謂每一子封 包(sub-paeket)之較小資料大小及將正4地傳輸每-子封包 而無需再傳輸任何給定子封包的較大機會。半槽可取決於 封包大小及半槽有效負載大小而傳輸封包或子封包(亦 即’封包之一部分)。如本文中所使用之"封包"通常係指槽 之有效負載或半槽之有效負載。-般熟習此項技術者將認 識到ifcb等槽界定之封包可包含習^口資料封包或習知資料 封包之子封包。 圖14A說明用於習知全槽封包協定之封包傳輸。圖i4B 說明根據本發明之實施例的使用半槽封包協定之封包傳 輸。在圖14A中,每一封包(或子封包)佔用一槽且傳輸通 道係以四個交錯予以組態’以說明在交錯内可存在指定至 相同或不同終端機的資料封包之四個不同的流。Ch4 can also be split into two logical sub-channels, for example, lower Ch4 and upper Ch4, and each logical sub-channel contains a set of connected sub-carriers. These logical channels can be scheduled independently. For example, each logical channel can be scheduled based on channel quality feedback received from the terminal used for the logical channel. In general, any number of HRPD carriers can be transmitted in a given spectrum configuration. For each HRPD carrier, each traffic segment can carry CDM data or OFDM data. The OFDM data may also be transmitted in the remaining available spectrum that is not used by the HRPD carrier. Figure 7 shows a slot structure 700 that supports OFDM and CDM for a single HRPD carrier in a 5 MHz spectrum configuration. In the example shown in Figure 7, a single HRPD carrier is located near one edge of the 5 MHz spectrum configuration. As described above in Figures 2 through 6, the pilot and MAC segments for the HRPD carrier are generated and transmitted at the center of the half-slot. Each traffic segment of the HRPD carrier can carry CDM data or OFDM data. An OFDM spectrum can be defined to include all of the available spectrum in the spectrum configuration (except for HRPD carriers). In the example shown in Figure 7, the OFDM spectrum contains the available spectrum on both sides of the HRPD carrier. Normal OFDM symbols and long OFDM symbols can be extended and used to carry data in the OFDM spectrum. The traffic data, signal transmissions, and pilots can be transmitted in the OFDM spectrum in any manner (e.g., using any of the techniques typically used in systems employing only OFDM or OFDMA). For example, pilot and signal transmissions can be transmitted in any manner over any subcarrier and symbol period. The available subcarriers and symbol periods can also be configured for any number of terminals, and any data can be sent to the scheduled terminal at 118974.doc 19 1336188. In the design shown in FIG. 7, two logical channels Ch 1 and Ch2 ° logical channel Chi are defined to include the traffic segments 1a and 1b transmitted on the HRPD carrier 1, and the logical channel ch2 is included in the OFDM spectrum. Traffic sections 2a to 2f. The logical channel chi can be switched between CDM and OFDM in each slot, every half slot, and the like. The logical channel Ch2 is not limited to any HRPD carrier and can operate in pure OFDM mode to carry only OFDM data. The traffic data, signal transmission, and/or pilot can be transmitted in OFDM in any manner on logical channel Ch2. Figure 8 shows an HRPD slot structure 800 supporting OFDM in a 5 MHz spectrum configuration. In the example shown in Figure 8, the spectrum configuration does not contain HRPD carriers. Normal OFDM symbols and long OFDM symbols can be used to transmit data throughout the available spectrum (except for the protection subband at the edge of the band). The logical channel Ch 1 can be defined to cover the entire available spectrum. The logical channel Chl can be operated (as if it were for an OFDM/OFDMA system) and it can have design elements from other OFDM/OFDMA technologies such as Flash OFDM®, IEEE 802.20, LTE, and the like. The time-frequency resources in the logical channel Chi can be divided into traffic resources for traffic data, signal transmission resources for signal transmission, pilot resources for pilots, and the like. Signal transmission data can be used to schedule terminals and assign traffic resources to scheduled terminals. Signal transmission data can also be used to facilitate hybrid automatic retransmission (H-ARQ) feedback, power control, and the like. Various structural elements and physical layer features of flash OFDM®, IEEE 802.20 'LTE and/or other OFDM/OFDMA systems can be used for the logical channel Chi. 118974.doc • 20- 1336188 FIG. 9 shows a block diagram of one of the access points 110 and the terminal 120, the access point and the terminal being one of the access points and terminals in FIG. For the sake of simplicity, only the processing unit for transmission on the forward link is shown in FIG. At access point 110, TX CDM/OFDM processor 920 receives and processes the traffic data and signal transmissions and provides output samples as described below. Transmitter (TMTR) 922 processes (e.g., converts to analog, amplifies, filters, and upconverts) the output samples and produces a forward link signal transmitted via antenna 924. At terminal 120, antenna 952 receives the forward link signal from access point 110 and provides the received signal to receiver (RCVR) 954. Receiver 954 processes (e. g., filters, amplifies, downconverts, and digitizes) the received signals and provides received samples. The RX CDM/OFDM processor 960 processes the received samples in a manner complementary to the processing by the TX CDM/OFDM 920, as described below, and provides the decoded data to the terminal 120 and the received signal transmission. Controllers 930 and 970 direct operations at access point 110 and terminal 120, respectively. The memory 932 and 972 store the program code and data for the access point 110 and the terminal device 120, respectively. Figure 10 shows a block diagram of a TX CDM/OFDM processor 920a, which is designed for one of the TX CDM/OFDM processors 920 of Figure 1. Processor 920a includes (1) a CDM processor 1010 that generates CDM waveforms that carry CDM data and consumes data, and (ii) an OFDM processor 1050 that generates OFDM waveforms that carry OFDM data. Within the CDM processor 1010, the encoder/interleaver 1012 receives the traffic data to be transmitted using the 118974.doc -21 - 1336188 CDM to encode the traffic data based on the _ encoding mechanism, and interleaves (or reorders) the encoded Information. The mapper mapper maps the interleaved data to the data symbols based on a modulation mechanism. The demultiplexer (Demux) 1〇16 demultiplexes the data symbols into multiple (for example, 16) streams. The Walsh cover unit 1 覆盖 18 covers or channels each data symbol stream with different "chip Walsh codes to obtain a corresponding data chip stream. The summer 1020 pair is used for multiple wales. Multiple (eg, 16) data chip streams are summed and the CDM data is provided at the chip rate. The τχ processor 1G22 receives the signal transmission with the mMAC segment and the pilot for the pilot segment. The data is generated at the chip rate for the consumption segment. The TDM multiplexer (Mux) 1024 receives the CDM data from the summer device and the consumption data from the processor 〇22, and carries the CDM. The CDM data is provided in the traffic section of the data, and the consumption data is provided in the consumption section. The multiplier 1026 multiplies the output of the multiplexer 1024 by the pseudo-noise (pN) sequence for the access point and encodes the code. The slice rate provides an output chip. The pulse shaping filter 1028 filters the output chips and provides a cdm waveform for an HRpD carrier. Multiple execution individuals of the CDM processor can generate multiple HRpD carriers for multiple CDM waveforms. These multiple CDM waveforms can be upconverted to the digital or analog domain to Appropriate frequency. Within the OFDM processor 1050, the encoder/interleaver 1 〇 52 receives the traffic information to be transmitted using OFDM to alpha, encodes the traffic data, and interleaves the encoded data. The symbol mapper 1〇54 maps the interleaved alternatives to the data symbols. The symbol-to-subcarrier mapper 1〇56 maps the data symbols to the subcarriers for OFDM. The zero insertion unit 1〇58 is not used for 118974. Doc -22- OFDM subcarriers (eg, subcarriers, null subcarriers, and guard subcarriers corresponding to the CDM traffic section and the consumption section) are inserted with a zero symbol (which has a signal value of zero). Discrete Fourier An inverse transform (IDFT) unit 1060 performs a K-point IDFT on the data symbols and zero symbols for the K total subcarriers in each OFDM symbol period and provides a useful portion containing K time domain samples. K depends on the OFDM symbol Digitally and given for normal OFDM symbols and long OFDM symbols in Tables 1 and 2. The Cyclic Preamble Insertion Unit 1062 copies the last C samples of the useful portion and appends these C samples to the front of the useful portion so that Form one at sample rate There are K+C samples of OFDM symbols. The sample rate can be n times the chip rate, where η can be equal to 1, 2, 3, 4, etc. The repeated part is called the cyclic preamble and is used against the frequency selection. The ISI caused by the fading. The windowing/pulse shaping filter 1064 windowizes and filters the samples from unit 1062 and provides an OFDM waveform. The summer 1 〇7 〇 pairs the CDM waveforms from the CDM processor 1010 and from the OFDM processor The OFDM waveforms of 1050 are summed and provide an output waveform.Figure 11 shows a block diagram of a TX CDM/OFDM processor 920b, which is another design of the TX CDM/OFDM processor 920 of Figure 1. Processor 920b maps the CDM data to subcarriers for CDM and maps the OFDM data to subcarriers for OFDM. Processor 920b then generates an output waveform based on the mapped CDM data and OFDM data. Within processor 920b, TX CDM processor 1110 receives the traffic data, signal transmissions, and pilots to be transmitted using the CDM and provides output chips. Processor 1110 can include units 1012 through 1026 in FIG. The DFT unit m2 performs an L-point 118974.doc • 23 - 1336188 DFT for the output chips in each OFDM symbol period and provides L frequency-domain symbols for the L sub-carriers. L is the number of subcarriers corresponding to an HRPD carrier and may depend on the number of 〇fdm symbols. The encoder/interleaver 1120 and the symbol mapper 1122 process the traffic data to be transmitted using the FDM and provide the data symbols. The symbol-to-subcarrier mapper 1130 maps the frequency domain symbols from the DFT unit 1 Π 2 to the 钊 carrier for cdm and further maps the data symbols from the symbol mapper 丨丨 22 to the subcarriers for OFDM. Zero insertion unit 1132 inserts a zero symbol on subcarriers (e.g., null and guard subcarriers) that are not used for CDM or OFDM. The IDFT unit 1134 performs a K-point 1DFT on the K symbols for each 0Fdm symbol period and provides a useful portion containing K time-domain samples. The loop preamble insertion unit 丨 136 inserts a loop preamble into the useful portion and provides a 〇 FDM symbol containing K + c samples at the sample rate. Windowing/pulse shaping filter 1138 windowizes and filters samples from unit 1136 and provides an output waveform. Filter 1138 can provide steeper spectral attenuation than filter 1 〇 64 in Figure 1 , which allows for better utilization of the spectrum configuration. Figure 12 shows a block diagram of an RX CDM/〇fdm processor 960a, which is designed for one of the rx CDM/OFDM processors 960 of Figure 9. The processor 96A can be used to receive an output waveform generated by the TX CDM/OFDM processor 920a of FIG. To recover the CDM data, the filter 1212 obtains the received samples from the receiver 954 'filtering the received samples to remove spectral components outside the HRPD carrier of interest, performing a self-sample rate to chip rate conversion, and Provide filtered chips. The multiplier 1214 multiplies the filtered chip by the PN sequence 118974.doc • 24· used by the access point and provides 耠 by incrementing μ and inputting the chip. The TDM demultiplexer ι 216 provides an input chip eight main channel estimator 1218 for the pilot segment, and the input chip of the MAC segment is used to ', 5, and consumes the processor, and is provided for carrying the CDM The input sentence of the pg 〇 ° ° ° segment is sent to the Walsh solution cover unit 1222. Juicer 1218 derives a channel estimate based on the received pilot. Unit 122 _ 222 盍 解 or de-channelization (dechanneiiz is used for parent-used CDM, sb νι_ ^ 夭 什 的 的 的 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且 且The received symbol y body demodulator (Demod) 1226 of all Walsh codes performs coherent detection on the received symbols with channel estimates and provides a vertical axis _ from the Bayesian 唬 estimate, the data symbol estimates For the estimation of the data symbols transmitted in CDM, the deinterleaver/decoder 1228 deinterleaves and decodes the data symbol estimates and provides decoded data for (10). The RX (four) processor mo processes the MAC segments. Transmitting the chip and providing the received signal transmission. To recover the OFDM data, the cyclic preamble removal unit 1252 obtains K+c received samples in each OFDM symbol period, removing the cyclic preamble, and Providing K received samples for the useful portion. DFT unit 1254 performs a point DFT on the K received samples and provides one received symbol for κ total subcarriers. Symbol to subcarrier demapping Demappe〇1256 obtained for κ The received symbols of the total subcarriers, the received data symbols for the subcarriers for OFDM are provided to the data demodulator 1258, and the received pilot symbols are provided to the channel estimator 1218. The data demodulator 1258 performs data detection on the received data symbols with channel estimates from channel estimator 1218 (eg, matching filtering, etc.) and provides data symbol estimates, which are estimated by pairs of data symbols. Estimation of data symbols transmitted in OFDM. Deinterleaver/decoder 1260 deinterleaves and decodes the data symbol estimates and provides decoded data for OFDM. Figure 13 shows a block diagram of an RX CDM/OFDM processor 960b, the processor Another design of the RX CDM/OFDM processor 960 of Figure 9. The processor 960b can be used to receive an output waveform generated by the TX CDM/OFDM processor 920b of Figure 11. In the processor 960b, the loop preamble The item removal unit 1312 obtains K+C received samples in each OFDM symbol period, removes the cyclic preamble, and provides K received samples for the useful portion. 0? unit 1314 to 1<; The received samples perform 1 and 0 and provide K received symbols for K total subcarriers. The symbol to subcarrier demapper 13 16 obtains received for K total subcarriers. The symbol, the received symbols for the subcarriers for the CDM are provided to the IDFT unit 1320, and the received symbols for the subcarriers for OFDM are provided to the data demodulator 1330. To recover the CDM data, the IDFT unit 1320 performs L-point IDFT on L received symbols for sub-carriers for CDM in an OFDM symbol period and provides L time-domain samples. RX CDM processor 1322 processes time-domain samples and provides received signal transmission And decoded data for CDM. Processor 13 22 may include units 1214 through 1228 in Figure 12. To recover the OFDM data, the data demodulator 1330 performs a data detection on the received symbols from the demapper 13 16 with a channel estimate and provides a data symbol estimate. Deinterleaver/decoder 1332 deinterleaves and decodes the data symbol estimates. And Decoded Data for OFDM is provided 〇 118974.doc -26 - For the sake of clarity, various aspects of the technology have been specifically described for the transmission of CDM and OFDM into the HRPD system. These techniques can also be used in other combinations of Xigong mechanisms, such as sc_FDM, CDM and TDM, and 〇FDM, TDM, and 〇FDM. These techniques can also be used with other wireless communication systems and for forward and reverse links. In wireless systems, ensuring reliable data packet delivery on each individual transmission can be inefficient. Inefficiency is especially evident in systems where the basic channel conditions are transmitted from one transmission to another. For example, in an OFDM system, there may be a wide variation in the received signal-to-noise ratio (SNR) between frames/packets, making it difficult to guarantee a small frame error rate (FER) for each packet transmission. And inefficient. This difficulty and inefficiency also applies to other communication systems employing orthogonal multiple access techniques including, but not limited to, TDMA, FDMA, and CDM. In such communication systems, a packet retransmission mechanism such as an Automatic Retransmission/Repetition Request (ARQ) procedure can be used to help reduce such inefficiencies. However, ARQ procedures may cause higher packet latency because each packet may take an average of longer to pass β. In general, large packet latency may not be a significant problem for data traffic, but It may be detrimental to voice traffic or other types of applications that require low latency in information transmission. In addition, it is expected that the packet transmission latency will increase as the number of users in the system continues to grow. Therefore, to improve system capacity (e.g., based on system throughput or the number of users using the system at the same time, etc.), the transmission latency should be kept low or small. The ARQ typically includes an acknowledgment/negative acknowledgment (ACK/NACK) signal to indicate whether the terminal has successfully received the 118974.doc -27- 1336188 - packet. As a non-limiting example, the terminal machine checks: the check algorithm (such as the hash function two:: the seal... such a hash function is successfully evaluated by the loop c, and (iv) all the bit systems can issue one If the ACKe indicating that the terminal does not need to retransmit the packet is CRC = evaded, it may not be *+ in the packet; all the bits in the 均 are correct and the terminal sends out a different terminal and needs to retransmit the packet. The NACKe uses the packet transmission on the forward keyway, which knows the full slot to the link towel. The half-slot transmission results in a larger granularity of L and (result) a greater chance of successfully transmitting smaller packets. Although the latency may be the same, the smaller granularity means a smaller data size per sub-paeket and a greater chance of transmitting each sub-packet without any transmission of any given sub-packets. The half slot may transmit a packet or sub-packet (ie, a portion of the 'package) depending on the packet size and the half-slot payload size. As used herein, "package" generally refers to the payload or half-slot of the slot. Payload. - familiar with this The skilled artisan will recognize that a packet defined by a slot such as ifcb may include a subpackage of a data packet or a packet of a conventional data packet. Figure 14A illustrates packet transmission for a conventional full slot packet protocol. Figure i4B illustrates the use of an embodiment in accordance with the present invention. Packet transmission of the half-slot packet protocol. In Figure 14A, each packet (or sub-packet) occupies one slot and the transmission channel is configured with four interlaces to indicate that there may be a specified or different terminal in the interlace The data packet is wrapped in four different streams.
Il8974.doc •28· 1336188 一將封包自存取點傳輸至終端機,終端機便可能要花 費兩個槽來開始以一含有ACK/NACK資訊之ARQ做出回 應。如圖14A中所巾,該ARQ在持續時間上可為一半槽且 在反向鏈路上予以傳回。因此,存取點在其接收到 夺重發封包之最早機會係在發送原始封包之後的四個封 包。結果,四個交錯允許基於ACK/NACK資訊而確定任何 給定資料流是發送新的封包還是重發先前的封包。Il8974.doc •28· 1336188 As soon as the packet is transmitted from the access point to the terminal, the terminal may have to spend two slots to start responding with an ARQ containing ACK/NACK information. As depicted in Figure 14A, the ARQ can be half a slot in duration and passed back on the reverse link. Therefore, the earliest opportunity for an access point to receive a re-sent packet is the four packets after the original packet is sent. As a result, the four interlaces allow for determining whether any given stream is to send a new packet or resend the previous packet based on the ACK/NACK information.
如圖14A中所示,存取點在第一交錯中發送封包丨、封包 2、封包3及封包4。在封包4時間期間,接收且解碼封包^ 之終端機以—用於封包1的&含ACK/NACK資訊之ARQ1做 出回應因此,使用ACK/NACK資訊,存取點可在接收到 ACK時發送出封包i,作為用於第一資料流之新封包,或在 接收到NACX時重發用於第―資料流的先前發送之封包。 同樣地,在封包1,時間期間,發送一用於來自第二資料流As shown in FIG. 14A, the access point transmits a packet 封, a packet 2, a packet 3, and a packet 4 in the first interlace. During the packet 4 time, the terminal that receives and decodes the packet responds with the ARQ1 containing the ACK/NACK information for the packet 1. Therefore, using the ACK/NACK information, the access point can receive the ACK. The packet i is sent out as a new packet for the first data stream, or the previously transmitted packet for the first data stream is retransmitted upon receipt of the NACX. Similarly, during packet 1, during the time, one is sent for the second data stream.
之封包2的ARQ2且存取點可在封包2,時間處以一新封包或 一重發封包做出回應。 圖14B說明根據本發明之實施例的用於使用半槽封包協 定之封包傳輸。在圖14B中,每—封包(或子封包)佔用一 半槽且傳輸通道可(作為一非限制性實例)以八個交錯予以 說明在交錯内可存在指定至相同或不同終:機的 資料封包之人個不同的流。因此,本發明之實施例允許在 ==四槽區塊内交錯更多資料流。另夕卜半槽粒度意 於母—子封包之較Η料大小及將正確地傳輪每一子 封包而無冑再傳輸任何給定封包的較大機會。 H8974.doc •29· 1336188The ARQ2 of the packet 2 and the access point may respond with a new packet or a retransmission packet at the time of the packet 2. Figure 14B illustrates packet transmission for use with a half slot packet protocol in accordance with an embodiment of the present invention. In FIG. 14B, each packet (or sub-packet) occupies half of the slot and the transmission channel can be (as a non-limiting example) illustrated with eight interlaces. There may be data packets assigned to the same or different end in the interlace. People have a different stream. Thus, embodiments of the present invention allow for more data streams to be interleaved within a == four-slot block. In addition, the half-slot granularity means a larger chance of the parent-child packet and the larger chance that the packet will be correctly transmitted without any subsequent transmission of any given packet. H8974.doc •29· 1336188
如圖14B中所示,存取點在第一交錯中發送封包卜8。在 封包7時間(其係與圖14A之習知流相同之潛時)期間,接收 且解碼封包1之終端機以一用於封包!的包含Ack/nack資 訊之ARQ1做出回應。因此,使用ACK/NACK資訊,存取 點可在接收到ACK時發送出封包1,作為用於第—資料流之 新封包,或在接收到NACK時重發用於第一資料流的先前 發送之封包。同樣地,在封包8時間期間,發送一用於來 自第二資料流之封包2的ARQ2,且存取點可在封包2,時間 處以一新封包或一重發封包做出回應。如對於八尺⑴及 ARQ4所說明’類似機制可用於每一半槽封包。As shown in Figure 14B, the access point sends a packet 8 in the first interlace. During the packet 7 time (which is the same latency as the conventional stream of Figure 14A), the terminal that receives and decodes packet 1 is used for packetization! The ARQ1 containing the Ack/nack information responded. Therefore, using ACK/NACK information, the access point can send out packet 1 as a new packet for the first data stream upon receiving the ACK, or resend the previous transmission for the first data stream upon receiving the NACK. The package. Similarly, during packet 8 time, an ARQ2 for packet 2 from the second data stream is sent, and the access point can respond with a new packet or a retransmission packet at time 2, at time. As described for the eight feet (1) and ARQ4, a similar mechanism can be used for each half slot packet.
另外,雖然未展示於單個圖中,但具有全槽之四個交錯 的圖14A之组態可與如14B圖中所示的半槽之八個交錯結 合》作為一非限制性實例,在圖14B中半槽封包3及4可 經結合為單—全槽封包。結果,用於彼全槽封包之ARQ將 出現於ARQ3時間處且將不存在ARQ4。或者,任何給定之 四槽區段可包括全槽之四個交錯或半槽之人個交錯。換言 之’作為-非限制性實例,全槽之四個交錯之後可有半槽 之八個交錯’半槽之八個交錯之後可有全槽之四個交錯。 圖15展示可用於本發明之實施例中的與有效負載大小及 再試之數目有關之各種調變階數。每當存取點須重發一封 包時,存取點可改變調變以具有成功地發送該封包之更佳 機會。另外,終端機可量測前向鏈路通道之品質且將該資 訊傳輸至存取點。存取點使 ^ 取點了使用已接收之通道條件來預測 可接文之傳輸格式、下—封包傳輸之速率。作為一非限制 118974.doc •30· U36188 實例終端機可使用通道品質反饋通道(CQICH)來將最 佳:服扇區之通道品質量測輸送至基地台。可基於已接收 之前向鏈路信號在載波干擾(C/Ι)比方面量測通道品質。可 將C/I值映射至通道品質指示符(CQI)符號上。 另外,終端機可提供資料速率控制(DRC)資訊至存取 資汛可基於(例如)來自先前前向鏈路傳輸之CM量 測。存取點可使用DRC資訊來確定對於在接收到DRC資訊 之後的封包使用何種類型之調變。 藉由調變機制而確定頻譜效率。各種調變機制可用於資 料傳輸。每一調變機制與含有Μ個'信號點之信號分佈 (signal constellati〇n)相關聯,其中购。藉由一複合值界 疋每一信號點且藉由一 B位元二進位值識別每一信號點, 其中^丨謂^對於符號映射,首先將待傳輸之碼位 兀分組為B個碼位元之組β B個碼位元之每一組形成映射 至一特定信號點之B位元二進位值,隨後作為用個碼 位元之彼群的調變符號而傳輸該信號點。每一調變符號因 此載運用於B個碼位元之資訊。可用於本發明之實施例中 的一些非限制性實例調變過程係正交相移鍵控機制 (Qpsk)、8相移鍵控機制(8_PSK),及16正交調幅(i6 qam) 及 64 QAM。 因此,作為一來自圖15之實例,對於第—次發送封包時 4096位元之有效負載大小,可以調變階數6(亦即,料 QAM)發送封包。若須重發封包,則第二次發送封包時可 再次以調變階數6(亦即,64 QAM)發送封包。然而,若需 1I8974.doc 31 第一次重發封包(亦即,第三次 修改為調變階數4(亦即, :輸)’則存取點可將調變 將認識到,對於較小有效負裁幻)° —般熟習此項技術者 且仍在半槽封包大小的範圍内。’可使用較小調變階數 各種資負载A小及再試之數目有關的可達成之 合禋貝枓速率。圖J 6上咨 自截 科速率對應於來自圖15之有效 負載大小、傳輸數目及調變階數。 =17展示-存取點及一終端機之方塊圖。除亦展示了反 向鏈路之傳輸及接收十所使用的操作區塊之外,此方塊圖 方塊圖1此’以上關於圖9所描述的對前向 鏈路之功能描述同樣可適用於圖17。 對於反向鏈路,在終端機中,控制器97()使用來自U CDM/OFDM處理器96()之資料且如較早已解釋般確定是否 已成功地接收到來自半槽之封包。控制器970&τχ資料處 理器980隨後組合ARQ且將其發送至發射器(TMTR)982以 經由天線952傳輸至存取點。在存取點側,接收器 (RCVR)942經由天線924接收反向鍵路資訊。RX資料處理 器940及控制器930解碼ARQ以擷取諸如ACK/NACK資訊之 資訊、諸如CQI之前向鏈路品質資訊,及諸如drc之資料 速率控制資訊。 使用DRC、CQI及ACK/NACK資訊之組合,控制器可決 定是否應以一不同調變機制發送用於彼通道之下一封包。 圖18展示一用於發送且接收半槽封包之過程。左側上之 過程要件(process element)係可藉由存取點執行之存取點 118974.doc -32- 1336188 過程⑽’且右側上之過程要件係可藉由終端機執行之終 端機過程mo。所說明之過程係用於發送且(可能地)重發 一用於-給定資料流之給定封包…般熟f此項技術者將 認識到,》了發送且監控—資料流中之多個封包以及發送 且監控多個資料流,涉及許多其他過程。In addition, although not shown in a single figure, the configuration of Figure 14A with four interlaces of full slots can be combined with eight interleaving of half-slots as shown in Figure 14B as a non-limiting example, in the figure The half-slot packages 3 and 4 in 14B can be combined into a single-to-slot package. As a result, the ARQ for the full slot packet will appear at ARQ3 time and there will be no ARQ4. Alternatively, any given four-slot section may include four staggered or half-sloted interlaces of the full slot. In other words, as a non-limiting example, four of the full slots may have eight staggered half-slots. The eight-interlace of the half-groove may have four interlaces of the full slot. Figure 15 illustrates various modulation orders associated with the payload size and the number of retryes that may be used in embodiments of the present invention. Whenever an access point has to resend a packet, the access point can change the modulation to have a better chance of successfully transmitting the packet. In addition, the terminal can measure the quality of the forward link channel and transmit the information to the access point. The access point causes ^ to use the received channel conditions to predict the transmission format of the cipherable text and the rate at which the packet is transmitted. As an unrestricted 118974.doc •30· U36188 The example terminal can use the Channel Quality Feedback Channel (CQICH) to deliver the best channel quality measurement to the base station. The channel quality can be measured in terms of carrier interference (C/Ι) ratio based on the received forward link signal. The C/I value can be mapped to the Channel Quality Indicator (CQI) symbol. In addition, the terminal can provide data rate control (DRC) information to access resources based on, for example, CM measurements from previous forward link transmissions. The access point can use the DRC information to determine what type of modulation is used for the packet after receiving the DRC information. The spectral efficiency is determined by a modulation mechanism. Various modulation mechanisms are available for data transfer. Each modulation mechanism is associated with a signal distribution (signal constellati) that contains a 'signal point', among which. Each signal point is identified by a composite value boundary for each signal point and by a B-bit binary value, wherein for the symbol mapping, the code bits 待 to be transmitted are first grouped into B code bits. Each group of the group of β B code bits forms a B-bit binary value mapped to a particular signal point, and then transmits the signal point as a modulation symbol of the same group of code bits. Each modulation symbol thus carries information for B code bits. Some non-limiting example modulation processes that can be used in embodiments of the present invention are quadrature phase shift keying mechanism (Qpsk), 8-phase shift keying mechanism (8_PSK), and 16 quadrature amplitude modulation (i6 qam) and 64. QAM. Therefore, as an example from Fig. 15, for the payload size of 4096 bits when the packet is transmitted for the first time, the packet can be modulated by the modulation order 6 (i.e., QAM). If the packet needs to be resent, the packet can be sent again with a modulation order of 6 (i.e., 64 QAM) when the packet is sent for the second time. However, if 1I8974.doc 31 is required to resend the packet for the first time (that is, the third modification is the modulation order 4 (ie, :transmission)' then the access point will be modulated to recognize that Small effective negative cropping) ° is generally familiar to the person skilled in the art and is still within the range of half-slot packet size. 'You can use a smaller modulation order. The achievable combined rate of the various loads A and the number of retests. The protocol rate on Figure J 6 corresponds to the payload size, number of transmissions, and modulation order from Figure 15. =17 shows - the block diagram of the access point and a terminal. In addition to the operation blocks used for the transmission and reception of the reverse link, this block diagram is shown in Figure 1. The functional description of the forward link described above with respect to Figure 9 is equally applicable to the diagram. 17. For the reverse link, in the terminal, the controller 97() uses the data from the U CDM/OFDM processor 96() and determines if the packet from the half slot has been successfully received as explained earlier. The controller 970 & χ data processor 980 then combines the ARQ and sends it to the transmitter (TMTR) 982 for transmission to the access point via antenna 952. On the access point side, the receiver (RCVR) 942 receives the reverse link information via the antenna 924. The RX data processor 940 and controller 930 decode the ARQ to retrieve information such as ACK/NACK information, such as CQI forward link quality information, and data rate control information such as drc. Using a combination of DRC, CQI, and ACK/NACK information, the controller can decide whether a packet for the next channel should be sent with a different modulation mechanism. Figure 18 shows a process for transmitting and receiving a half slot packet. The process element on the left side is the access point 118974.doc -32- 1336188 process (10)' which is executed by the access point and the process element on the right side is the terminal machine process mo which can be executed by the terminal. The illustrated process is for transmitting and (possibly) retransmitting a given packet for a given data stream. As would be appreciated by those skilled in the art, it will be recognized that there are many Packets and the sending and monitoring of multiple streams involve many other processes.
…封包發送過程可在過程1702處以將DRC資訊自終端機發 达至存取點而開始。或者,存取點可開始處理一封包而無 需DRC資訊。對於一資料流中之後續封包而言尤其如此。 自任-開始點,過程1752確定用於該封包之資料速率及調 變機制。此確定可受DRC資訊(若其存在)以及有效負載大 小的影響。隨後,過程1754將半槽中之封包發送至終端 機。當然,其他過程可正發生以填補任何給定槽内之其他 訊務區段或半槽,從而為傳輸作準傷。The packet transmission process can begin at process 1702 by transmitting DRC information from the terminal to the access point. Alternatively, the access point can begin processing a packet without DRC information. This is especially true for subsequent packets in a data stream. From the start-to-start point, process 1752 determines the data rate and modulation mechanism for the packet. This determination can be affected by the DRC information (if it exists) and the payload size. Process 1754 then sends the packet in the half slot to the terminal. Of course, other processes can be occurring to fill other traffic segments or half slots in any given slot to compensate for transmission.
過程1704指示終端機解調變且解碼已•接收之槽,且具體 言之,解調變且解碼用於此封包的所關心之半槽。過程 1706確定封包完整性,其可包含執行CRC以確定是否成功 地接收到資料、分析通道品質以得出CQI,或其組合。決 策區塊1708指示:若接收到位元誤差,則可需要重發。若 需要重發,則過程1710定義應發送NACK。若不需要重 發’則過程1712定義應發送ACKe過程1714指示發送包含 至少ACK/NACK資訊之ARQ。ARQ亦可包含其他資訊,諸 如CQI資訊及DRC資訊。 決策區塊1756指示:存取點確定接收ACK還是 為ARQ之部分》若接收到ACK,則過程存在,因為不需要 118974.doc •33· 1336188 重發當前封包。對於資料流中之後續封包,過程將以進入 存取點過程1750或終端機過程1700之開始過程而重複。 若接收到NACK,則過程循環至1752以確定用於封包之 資料速率。在反向循環上’資料速率確定可受再試之數目 (未展示於圖18中)、有效負載大小、DRC資訊(若其存在) 及CQI資訊(若其存在)之組合的影響。 熟習此項技術者將理解,可使用多種不同的技術 (technologies and techniques)中之任一者來表示資訊及信 號。舉例而言’可藉由電壓、電流、電磁波、磁場或磁粒 子、光場或光粒子或其任何組合來表示貫穿以上描述可提 及之資料、指令、命令、資訊、信號、位元、符號及碼 片。 熟習此項技術者將進一步瞭解,結合本文中之揭示内容 所描述的各種說明性邏輯區塊、模組、電路及演算法步驟 可實施為電子硬體、電腦軟體或兩者之組合。為清楚地說 明硬體與軟體之此互換性,各種說明性組件、區塊、模 组、電路及步驟已在上文中在其功能性方面予以大體描 述。該功能性是實施為硬體還是軟體取決於強加於總系統 之特別應用及設計限制。熟習此項技術者可對於每一特別 應用以變化之方式實施所述功能性,但不應認為該等實施 決策會引起背離本揭示案之範_。 可以通用處理器、數位信號處理器(DSp)、特殊應用積 體電路(ASIC)、場可程式化閘陣列(FpGA)或經設計以執行 本文中所述之功能的其他可程式化邏輯設帛、離散閉或電 118974.doc •34- UJ6188 晶體邏輯、離散硬體組件或其任何組合來實施或執行结合 本文中之揭示内容所描述的各種說明性邏輯區塊、模組及 電路。通用處理H可為微處理^,但㈣代實施例中,處 理器可為任何習知之處理器、控制器、微控制器或狀態 機。處理器亦可實施為計算設備之組合,例如,一Dsp及 -微處理器、複數個微處理器、結合有—Dsp核心之一或 多個微處理器之組合,或任何其他此種組態。 結合本文中之揭示内容所描述的方法或演算法之步驟可 直接體現於硬體中、體現於藉由處理器執行之軟體模組 中,或體現於兩者之組合中。軟體模組可駐留於RAM記憶 體、快閃記憶體、ROM記憶體、epr〇MB憶體、eepr〇m 圯憶體、暫存器、硬碟、可移除磁碟、(:]〇_11〇]^或此項技 術中已知的任何其他形式之儲存媒體中。例示性儲存媒體 耦接至處理器,以致處理器可自儲存媒體讀取資訊且寫入 貝Λ至儲存媒體。在替代實施例中,儲存媒體可整合於處 理益。處理器及儲存媒體可駐留於ASIC中。ASIC可駐留 於使用者終端機中。在替代實施例十,處理器及儲存媒體 可作為離散組件駐留於使用者終端機中。此外,可將軟體 模組傳輸至終端機或存取點用於對其的儲存及執行。 雖然已參看特別實施例描述本發明,但應瞭解,實施例 係說明性的且本發明之範疇並不限於此等實施例。對以上 所述實施例之許多變化、修改、添加及改良係可能的。考 慮此等變化、修改、添加及改良屬於如在以下申請專利範 圍内詳述的本發明之範疇。 118974.doc -35- 1336188 【圖式簡單說明】 、圖1展示一高速率封包資料(HRPD)通信系統。 /圖2展示一支援CDM之單載波槽結構。 圖3A展示一支援OFDM之單載波槽結構。 圖3B展示一支援CDM及OFDM之單載波槽結構。 圖4展示一支援CDM之多載波槽結構。 .圖5展示一支援CDM及OFDM之多載波槽結構。 圖6展示另一支援CDM及OFDM之多載波槽結構。 圖7展示一支援OFDM及CDM之槽結構。 .圖8展示一支援在5 MHz頻譜配置中之OFDM的槽結構。 圖9展示一存取點及一終端機之方塊圖。 圖1 0展示一傳輸(TX)CDM/OFDM處理器之一設計。 v圖11展示一 TX CDM/OFDM處理器之另一設計。 圖12展示一接收(RX)CDM/OFDM處理器之一設計。 圖13展示一 RX CDM/OFDM處理器之另一設計。 •圖14A展示用於習知全槽封包協定之封包傳輸。 圖14B展示根據本發明之實施例的用於使用半槽封包協 定之封包傳輸。 圖1 5展示與有效負載大小及再試數目有關的各種調變階 數。 圖16展示與有效負載大小及再試數目有關的可達成之各 種資料速率。 圖17展示一存取點及一終端機之方塊圖。 ‘圖18展示一用於發送且接收半槽封包之過程。 H8974.doc -36- 1336188 【主要元件符號說明】Process 1704 directs the terminal to demodulate and decode the received slot and, in particular, demodulate and decode the half slot of interest for the packet. Process 1706 determines packet integrity, which may include performing a CRC to determine if the data was successfully received, analyzing channel quality to derive a CQI, or a combination thereof. Decision block 1708 indicates that retransmission may be required if a bit error is received. If retransmission is required, then process 1710 defines that a NACK should be sent. If no retransmission is required, then process 1712 defines that an ACKe procedure 1714 should be sent to indicate the transmission of an ARQ containing at least ACK/NACK information. ARQ can also contain other information such as CQI information and DRC information. Decision block 1756 indicates whether the access point determines whether to receive the ACK or is part of the ARQ. If an ACK is received, the process exists because 118974.doc • 33· 1336188 is not required to resend the current packet. For subsequent packets in the data stream, the process will repeat as it enters the access point process 1750 or the beginning of the terminal process 1700. If a NACK is received, the process loops to 1752 to determine the data rate for the packet. The data rate on the reverse loop determines the effect of the combination of the number of retries (not shown in Figure 18), payload size, DRC information (if it exists), and CQI information (if it exists). Those skilled in the art will appreciate that information and signals can be represented using any of a variety of different techniques and techniques. For example, data, instructions, commands, information, signals, bits, symbols may be referred to by the above description by voltage, current, electromagnetic wave, magnetic field or magnetic particle, light field or light particle or any combination thereof. And chips. It will be further appreciated by those skilled in the art that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as an electronic hardware, a computer software, or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether the functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each particular application, but should not be construed as a departure from the scope of the disclosure. A general purpose processor, digital signal processor (DSp), special application integrated circuit (ASIC), field programmable gate array (FpGA), or other programmable logic set designed to perform the functions described herein. The discrete logic or electrical 118974.doc • 34- UJ6188 crystal logic, discrete hardware components, or any combination thereof, implements or performs various illustrative logic blocks, modules, and circuits described in connection with the disclosure herein. The general purpose processing H can be a micro-processing, but in the fourth embodiment, the processor can be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented as a combination of computing devices, for example, a Dsp and-microprocessor, a plurality of microprocessors, a combination of one or more Dsp cores, or any other such configuration. . The steps of the method or algorithm described in connection with the disclosure herein may be embodied in a hardware, in a software module executed by a processor, or in a combination of the two. The software module can reside in RAM memory, flash memory, ROM memory, epr〇MB memory, eepr〇m memory, scratchpad, hard disk, removable disk, (:]〇_ 11 or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from the storage medium and write to the storage medium. In an alternative embodiment, the storage medium may be integrated into the processing. The processor and the storage medium may reside in the ASIC. The ASIC may reside in the user terminal. In an alternative embodiment 10, the processor and the storage medium may reside as discrete components. In addition, the software module can be transferred to a terminal or access point for storage and execution thereof. While the invention has been described with reference to the specific embodiments, it should be understood that the embodiments are illustrative The scope of the present invention is not limited to the embodiments. Many variations, modifications, additions and improvements to the above-described embodiments are possible. Considering such changes, modifications, additions and improvements are as follows in the following patent application.The scope of the invention as detailed in the following paragraphs 118974.doc -35- 1336188 [Simple description of the diagram], Figure 1 shows a high rate packet data (HRPD) communication system. / Figure 2 shows a single carrier slot structure supporting CDM. Figure 3A shows a single carrier slot structure supporting OFDM. Figure 3B shows a single carrier slot structure supporting CDM and OFDM. Figure 4 shows a multi-carrier slot structure supporting CDM. Figure 5 shows a support for CDM and OFDM. Carrier Slot Structure Figure 6 shows another multi-carrier slot structure supporting CDM and OFDM. Figure 7 shows a slot structure supporting OFDM and CDM. Figure 8 shows a slot structure supporting OFDM in a 5 MHz spectrum configuration. 9 shows a block diagram of an access point and a terminal. Figure 10 shows one design of a transmission (TX) CDM/OFDM processor. Figure 11 shows another design of a TX CDM/OFDM processor. One design of a Receive (RX) CDM/OFDM processor is shown. Figure 13 shows another design of an RX CDM/OFDM processor. Figure 14A shows a packet transmission for a conventional full slot packet protocol. Figure 14B shows a packet transmission according to the present invention. The packet of the embodiment for using the half-slot packet protocol Figure 15 shows the various modulation orders associated with the payload size and the number of retries. Figure 16 shows the various data rates achievable in relation to the payload size and the number of retries. Figure 17 shows an access point and a terminal. Block diagram. 'Figure 18 shows a process for transmitting and receiving half-slot packets. H8974.doc -36- 1336188 [Main component symbol description]
1 a 訊務區段 lb 訊務區段 2a 訊務區段 2b 訊務區段 2c 訊務區段 2d 訊務區段 2e 訊務區段 2f 訊務區段 3 a 訊務區段 3b 訊務區段 4a 訊務區段 4b 訊務區段 4c 訊務區段 100 HRPD通信系統 110 存取點 120 終端機 130 系統控制器 200 單載波槽結構 300 單載波槽結構 302 單載波槽結構 400 多載波槽結構 500 多載波槽結構 600 多載波槽結構 118974.doc -37- 13361881 a Traffic segment lb Traffic segment 2a Traffic segment 2b Traffic segment 2c Traffic segment 2d Traffic segment 2e Traffic segment 2f Traffic segment 3 a Traffic segment 3b Traffic Section 4a Traffic Section 4b Traffic Section 4c Traffic Section 100 HRPD Communication System 110 Access Point 120 Terminal 130 System Controller 200 Single Carrier Slot Structure 300 Single Carrier Slot Structure 302 Single Carrier Slot Structure 400 Multicarrier Slot structure 500 multi-carrier slot structure 600 multi-carrier slot structure 118974.doc -37- 1336188
700 槽結構 800 HRPD槽結構 920 TX CDM/OFDM處理器 920a TX CDM/OFDM處理器 920b TX CDM/OFDM處理器 922 發射器(TMTR) 924 天線 930 控制器 932 記憶體 940 RX資料處理器 942 接收器(RCVR) 952 天線 954 接收器(RCVR) 960 RX CDM/OFDM處理器 960a RX CDM/OFDM處理器 960b RX CDM/OFDM處理器 970 控制器 972 記憶體 980 TX資料處理器 982 發射器(TMTR) 1010 CDM處理器 1012 編碼器/交錯器 1014 符號映射器 1016 解多工器(Demux) 118974.doc -38 - 1336188 1018 沃爾什覆蓋單元 1020 求和器 1022 TX耗用處理器 1024 TDM多工器(Mux) 1026 乘法器 1028 脈衝成形遽波器 1050 OFDM處理器 1052 編碼器/交錯器 1054 符號映射器 1056 符號至副載波映射器 1058 零插入單元 1060 離散傅立葉逆變換(IDFT)單元 1062 循環前置項插入單元 1064 窗口化/脈衝成形濾波器 1070 求和器 1110 TX CDM處理器 1112 DFT單元 1120 編碼器/交錯器 1122 符號映射器 1130 符號至副載波映射器 1132 零插入單元 1134 IDFT單元 1136 循環前置項插入單元 1138 窗口化/脈衝成形濾波器 118974.doc -39- 1336188 1212 濾、波器 1214 乘法器 1216 TDM解多工器 1218 通道估計器 1220 RX耗用處理器 1222 沃爾什解覆蓋單元 1224 多工器 1226 資料解調器(Demod) 1228 解交錯器/解碼器 1252 循環前置項移除單元 1254 . DFT單元 1256 符號至副載波解映射器 1258 資料解調器 1260 解交錯器/解碼器 1312 循環前置項移除單元 1314 DFT單元 1316 符號至副載波解映射器 1320 IDFT單元 1322 RX CDM處理器 1330 資料解調器 1332 解交錯器/解碼器 Chi 邏輯通道 Ch2 邏輯通道 Ch3 邏輯通道 Ch4 邏輯通道 118974.doc -40-700 slot structure 800 HRPD slot structure 920 TX CDM/OFDM processor 920a TX CDM/OFDM processor 920b TX CDM/OFDM processor 922 transmitter (TMTR) 924 antenna 930 controller 932 memory 940 RX data processor 942 receiver (RCVR) 952 Antenna 954 Receiver (RCVR) 960 RX CDM/OFDM Processor 960a RX CDM/OFDM Processor 960b RX CDM/OFDM Processor 970 Controller 972 Memory 980 TX Data Processor 982 Transmitter (TMTR) 1010 CDM processor 1012 encoder/interleaver 1014 symbol mapper 1016 demultiplexer (Demux) 118974.doc -38 - 1336188 1018 Walsh overlay unit 1020 summer 1022 TX processor 1024 TDM multiplexer ( Mux) 1026 Multiplier 1028 Pulse Forming Chopper 1050 OFDM Processor 1052 Encoder/Interleaver 1054 Symbol Mapper 1056 Symbol to Subcarrier Mapper 1058 Zero Insertion Unit 1060 Discrete Fourier Transform (IDFT) Unit 1062 Loop Preamble Insertion unit 1064 windowing/pulse shaping filter 1070 summer 1110 TX CDM processor 1112 DFT unit 1120 encoder/interleaver 1122 No. Mapper 1130 Symbol to Subcarrier Mapper 1132 Zero Insertion Unit 1134 IDFT Unit 1136 Loop Preamble Insertion Unit 1138 Windowing/Pulse Shaping Filter 118974.doc -39- 1336188 1212 Filter, Waver 1214 Multiplier 1216 TDM Solution Multiplexer 1218 Channel Estimator 1220 RX Consumable Processor 1222 Walsh Solution Cover Unit 1224 Multiplexer 1226 Data Demodulator (Demod) 1228 Deinterleaver/Decoder 1252 Cyclic Preamble Removal Unit 1254. DFT Unit 1256 Symbol to Subcarrier Demapper 1258 Data Demodulator 1260 Deinterleaver/Decoder 1312 Cyclic Preamble Removal Unit 1314 DFT Unit 1316 Symbol to Subcarrier Demapper 1320 IDFT Unit 1322 RX CDM Processor 1330 Data Demodulator 1332 Deinterleaver/Decoder Chi Logical Channel Ch2 Logical Channel Ch3 Logical Channel Ch4 Logical Channel 118974.doc -40-
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