TWI335550B - Stream processor with variable single instruction multiple data (simd) factor and common special function - Google Patents

Description

[1335550 * IX, invention description: [Technical field of the invention] The present invention relates to a stream processor's more specifically to a variable single instruction multiple data (SIMD) coefficient A stream processor that can process data in different formats. [Prior Art] Since the beginning of 2000, fixed function image processing units (GPUs) have become more and more programmable to provide users with direct and flexible control of primitives in image wafers. (primitive), vertex, texture, and pixel stream processing. In many modern GPUs, at least one shader (such as primitives, vertices, etc.) has the ability to be programmed, but such a GPU can only handle a small number of data classes (like For 32-bit floating points of vertices and 32-bit integers). These colorizers, which can be programmed in the graphics pipeline, are often arranged in tandem to transfer data to fixed function units or, if necessary, to data converters for data transfer to each other. . Usually parallel multiprocessor architecture principles are also included in the GPU design. The application of the Parallel Architecture principle often uses several Arithmetic Logic Units (ALUs) of the same type to handle different types of data streams in a non-uniform program thread.

Client's Docket No.: S3U04-0012-TW TT, s Docket N〇: 0608-A4]] 10-TW/Final/LukeLee (Li Zongxuan) / 1, Feb, 2007 6 1335550. If the non-uniformity of the midnight brothers is interleaved, the ALU will be required to process different types of information in each clock cycle. Under such a multiprocessor architecture, the implementation of complex mathematical functions (special functions) is one of many important topics. There are usually two ways to do this: execute a special subroutine in the general ALU, or attach a special hardware unit to the general ALU (which will produce results based on the general ALU requirements). The software implementation of the above functions can result in significant performance degradation and may not be acceptable for instant image applications. In the case of multiple ALUs combined with Single Instructi 〇 11 Multiple Data (SIMD) architectures, special hardware units must be attached to each ALU, resulting in significant hardware cost increases. The special functions described above are not commonly used in shader programs. And most of the time these special hardware units combined in each ALU are idle. This condition can be shared by several ALUs with a special function unit (Special

The Function Unit (SFU) solves some of the problems, but in the SIMD architecture, a thread will be stalled until all streams get their results from the shared SFU, and the SFU will process their requests in sequence. Complex math functions in the shader may take several extra cycles to calculate. The SIMD streaming architecture should be specially arranged to reduce the pause waiting period, and to provide smooth stream processing that produces the least extra cycles, if the non-uniform pattern is interlaced. When ALUs are often subjected to high data throughput when used in multiple processing, these ALUs should be able to share the processing of longer formats.

Clients Docket No.: S3U04-0012-TW TT,s Docket N〇:0608-A4 丨110-TW/Final/LukeLee(李宗轩)/1,Feb, 2007 1335550 ^ Same hardware, to handle more short format data Streaming. In general, today's GPU's ALU is only used to handle a floating-point unit format (such as the 32-bit IEEE standard format), and is often inefficient when dealing with low-precision pixel and texture data. In addition, if another data format is supported, these ALUs often work on the same number of streams without considering the data format, and there is no (or only some) flux improvement, and there is no SIMD factor variability. . Furthermore, today's ALUs are usually not free to interleave instruction streams (lack of support for non-uniform programming). In addition, today's dual format multiply Accumulate (MACC) units typically only process integer data. Vector operators with fixed data formats and fixed SIMD coefficients usually have a small amount of hardware burden, and, when the number of elements in a vector stream is less than the width of a vector unit, the vector operator typically processes the stream data relatively Slower. In addition, today's image shader architectures, in the same instructions, generally have limited instruction set capabilities for processing different formats.

Therefore, a demand that has not been proposed so far exists in the industry to solve the above problems and inappropriate Q. [Invention] In the embodiment of the stream processor, it is designed to process data in several different formats. . At least one embodiment of the stream processor includes a first scalar ALU processing short format data (based on a short format control signal in the received command set), and processing long format data (based on a long format control signal in the received command set) . Several embodiments of the streaming processor also include a second ALU for receiving data processed by the first ALU, and according to the instruction set

Client's Docket No.: S3U04-0012-TW TT's Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 8 1335550, Medium: Control Signal 'Processing Input Data and Section-ALU Processing Still other embodiments include an SFU for providing additional computational functions to the first ALU and the second alu. Also included within this specification is an embodiment of a method for processing data in any of a number of different formats. At least one embodiment of the method includes determining whether the received data is short format data and the funds received in response thereto

It is expected to be short-form data, and functionally cuts the -ALU for processing according to an instruction set. Other embodiments of the method include transmitting the processed data to a zero-functionally cut second ALU. Also included in this specification is an embodiment of a modular stream processor for processing data in different formats. An embodiment of at least one modular stream processor includes a first-ALU for receiving first-input data and control data, the control data indicating a format of the received data. The first ALu is used to process short format input data and long format wheel data based on the control data. Some embodiments include a second ALU for receiving control data from the first alu spring, a second ALU for processing the second input data, and a second input data for the first-input material. It is also used to process short format poor materials and long format data, according to the control data. Still other embodiments include a third ALU for receiving control data from the second ALU, a second ALU for receiving the third input data, and a third round entry for the first and second input data. The third ALU is further used to process short format data and long format data according to the control data. Some embodiments include a fourth ALU for receiving control data from the third ALU, a fourth alu for receiving the fourth input data, and a fourth input data for the first, first, and

Client's Docket No,: S3U04-0012-TW TT’s Docket No: 060S-A41110-TW/Final/LukeLee (Li Zongxuan)/! s Feb, 2〇〇7 9 1335550 * The third input is related. The fourth arithmetic logic unit is further used to process the short format data and the long format tribute, and the phase is mediated according to the control. The systems, methods, features, and advantages of the present invention will become apparent from the Detailed Description. All of these additional systems, methods, features, and advantages will be included in the following description without departing from the scope of the disclosure. [Embodiment]

Figure 1A is a flow chart illustrating the streaming data processing steps of a processing unit incorporating an example of a vector ALU and an SFU. More specifically, Figure 1A shows a stream vector processing unit with a conventional architecture 100. As shown, the input stream of the 3-dimensional image data vector is passed to the input buffer conventional memory 102. The input buffer conventional memory 102 passes the vector data to the vector ALU (vector ALU) 104 in this example. As shown in successive instruction cycles, each vector contains four components: X, Y, z, and W. As shown, the vectors are passed from the input buffer conventional memory 102 to the vector ALU 104, which are arranged such that each vector is connected to each other. The vector ALU 104 and SFU 106 can perform the desired operations to produce an output for each element of the existing vector. An SFU is designed to handle many operational types, such as sine functions, cosine functions, square root functions, fractions, indices, and so on. Fig. 1B is a flow chart similar to the step of Fig. 1A, illustrating the execution steps of a scalar processing unit as an example. Figure 1B illustrates a vector data processing using a stream processor with four scalar ALUs 124. More specifically, the 3-dimensional image data vector

Client's Docket No.: S3U04-0012-TW TT's Docket Ν〇:0608-Α41 Π0-TW/Final/LukeLee(李宗轩)/1,Feb,2007 10 1335550 • Stream input to input data buffer 4 groups of orthogonal storage Take memory. Body 122. The memory 122 in this example is used to provide a direct access pattern for data reading and a horizontal access pattern for data writing. This type of memory 'has a special vector element multiplexer and address generator for one or more memory banks, as disclosed and discussed in U.S. Patent Application No. 20040172517, filed on Sep. 19, 2003. 'Think about it as a whole and integrate it here. The input data buffer 4 sets of orthogonal access memory 122 can transmit the reconstructed (vertical) vector data to the scalar ALU (124a-124d). More specifically, the input data buffer 4 sets of orthogonal access memories 122 successively transmit the first vector data elements (W1, Z1, Y1 'XI) to scalar ALU1 124a; successively transmit the second vector data elements (W2) 'Z2, Y2, X2) to scalar ALU2 124b; successively transmit the third vector data element to scalar ALU3 124c; and 'continuely transmit the fourth vector data element to scalar ALU4 124d. The scalar ALUs 124a-124d and SFU 126 can therefore process the vector data and separately transmit the processed data to the buffers SI, S2, S3, and S4. The output buffers S1-S4 then pass the data to the output quadrature converter 130, which converts the received data to a horizontal vector format. Furthermore, output orthogonal converter 130 can be designed to convert processed data from a scalar sequence or vertical representation to a horizontal vector representation. The data can then be output as Xout, Yout, Zout 'Wout ° as shown on the figure. It is worth noting that although the vector processing unit with the conventional architecture 100 processes one vector in the vector data at a time, the use has four scalars. The vector data processing of the ALU stream processor 120 does not have this

Clients Docket No.: S3U04-0012-TW TT’s Docket No: 〇608-A41110-TW/Final/LukeLee/1,Feb, 2007 11 1335550 • Requirements. As shown, the elements of the vector data can be processed in any order and then rearranged for output. Furthermore, although the stream processor 120 having four scalar ALUs and the vector processing unit 100 having the conventional architecture receive the vector data as a data group, this is not a necessary condition. The elements of the vector material can be received in any order of scalar quantity and can be processed in SIMD mode. As mentioned earlier, SIMD stream processors can be designed to perform complex mathematical operations (special functions) such as square root, sine, cosine, and other operations to provide image data processing in contemporary GPUs. The vector ALU may have an additional (or other accessible) SFU. Whenever an appropriate command arrives at the ALU, the SFU begins to work. SFU can be considered as an independent channel of the ALU. Figure 1C shows a stream processing SIMD architecture with software implementation of complex mathematical functions. Under the condition of SIMD scalar ALU, there are some options for the implementation of special functions. Each ALU has a special additional look-up table and a slightly modified data path to perform a special function calculation sequence in a special routine (such as the Newton-Raphson algorithm for calculating the square root). The time delay calculated by the special function in this example * will be equivalent to the number of regular instructions per special function multiplied by the instruction execution cycle of the SIMD scalar ALU. The problem with this implementation is that the delay time is significantly dependent on the number of instructions per ALU. Figure 1D is a stream processing SIMD architecture, with the hardware implementation of complex mathematical functions, each ALU uses a separate SFU. As shown in Figure 1D, each scalar ALU has a separate SFU hardware. The problem with this application is too much hardware, and these too many hardware are rarely used. however,

Client's Docket No.: S3U04-0012-TW TT's DocketN〇:0608-A41110-TW/Final/LukeLee/1,Feb,2007 1335550 The time delay for special function calculations will be minimal and usually equal to the average execution. cycle. · '二才曰 1E is a stream processing s! M D architecture, with the hardware implementation of complex mathematical functions, all ALUs use a common SFU. As shown, it reduces hardware costs by using a common SFU hardware that can handle multiple ALU requests. One problem with this implementation is that when the SFU contiguously processes all of the ^LU requests and calculates the values of all the streams, all alu explicitly pauses the wait time. In general, all ALUs will wait until the last ALU receives a return value from the SFU: stop. The total delay for this operation is equivalent to the processing period of the SFU multiplied by the total number of scalar ALUs connected to. Figure 1F is a -streamed gSIMD architecture with hardware implementation of complex mathematics 'interleaved access-to-sFU'. The time delay of the SFU is reduced by interleaving the SHJ by several ALUs: In particular, the 1F is an embodiment of a stream processing using a common SFU. In this case, 'from different scalars, use special (four) temporary storage H in time, and (4) re-arrange the same SIMD instruction execution in the column. Each string will be equivalent to the delay of each SFU. Compared with the previous architecture, the delay can be compensated by the delay register. Another problem that affects the efficiency of the s_ pure processor when dealing with different input stream patterns is the SIMD coefficient. &" point, triangle' and (4) pixel data, while the two streams may contain the need for a careful accumulation of top-of-the-line remnants that may result in significant delays' will also increase in regional memory

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 060S-A41110-TW/Fmal/LukeLee (Li Zongxuan)/], Feb, 2〇〇7 13 data life span. Figure 1G is a vertice and triangle process for reducing one (four) sub-s of SIMD coefficients under a common shared SIMD architecture. As shown in the figure, the figure illustrates the vertices and triangle stream processing of the same SIMD architecture with 4 coefficients when the four ALUs process the stream data and the SIMD coefficient is 4. The vertex packet to be processed contains data for four vertices. The triangle # packet to be processed contains 12 vertices, and may cause significant delays when the triangle vertices begin processing because of the pre-time to accumulate the complete packet. This is why when the triangle is processed in the same architecture with four ALUs, the reduction of the coefficients from 4, 2 to 1 becomes an important issue for today's image processing units. Figure 2A is a flow chart illustrating a scalar processing unit similar to the first

The flowchart of Figure 1 is accompanied by a SIMD coefficient of four. As shown in the figure, the flute 0 A map processes the vector stream data with a scalar ALU with a SIMD coefficient of 4 and = a long format. Similar to the data stream of Figure 1B, vector data is not a clever way to flow through a set of data streams. When each data element arrives at each ALU (ALUO 204a, ALU1 204b, ALU2 204c, and ALU3 204d), the ALU can process the data according to the ALU instruction that is synchronously communicated with the delay of the data transfer. In addition, as shown, the ALUO 204a receives data earlier than the ALU1 204b. Similarly, ALU2 204c is delayed compared to ALU1 204b. ALU3 204d is delayed compared to ALU2 204c. When the data has been processed, the processed data is transferred to buffers SI, S2, S3, and S4 with respective synchronization delays. It is worth noting that the SIMD coefficient of Figure 2A is 4 because of four

Client's Docket No.: S3U04-0012-TW TT's Docket N〇: 0608-A41110-TW/Final/LukeLee (Fe Zongxuan X), Feb, 2007 1335550 ALU Mussel performs the same operation. In addition, as shown in Figure 2a Each is used to process 3 6-bit long format data. · Figure 2B is a flow chart 'illustrating a scalar processing unit, similar to the \'s ", L private graph' with the SIMD coefficient is 1, and the result of the four ALUs is combined with the result of ALU3. As shown in the figure, Figure 2B illustrates several pure ALU processing vector stream data, and the SIMD coefficient is 1 and the data is long. When the structure of Figure 2A shows that vector data is sent to these ALUs in a different way than the inbound element data set, the structure in Figure 2B shows that vector data is transmitted to these ALUs as vector data sets. In particular, the data XI of Figure 2B is sent to ALU0. ALU0 can process the data and transmit at least part of the processing result to ALU1, and ALU0 also outputs the data to the element reorganizer ((;〇111?〇1^1^5} 111 volumes 226. People] 11; 1 delayed to pick up the output data from ALU0 and the data γι ALU1 transmits the output data to element reorganizer 226 and ALU 2. ALU 2 receives data zi and data from ALTJ 1. ALU 2 transmits the output data to element reorganization 226 and ALU 3. ALU 3 receives data W1 and data from ALU 2. ALU 3 transmits output data to element Reorganizer 226. Element shuffler 226 can transmit data to one or more of the following outputs: Xout, Yout,

Zout, and Wout. In this example, if it is a vector inner product operation, this mode is better able to process a small number of streams, such as triangles and vertex packets, in fewer clock cycles. It is worth noting that the SIMD coefficient of Figure 2B is 1, because each ALU executes the same instruction but a different number of operands. More specifically, because each ALU receives data from the previous ALU, these ALUs are based on their location.

Client’s Docket No.: S3U04-0012-TW XT’s Docket No: 0608-A41110-TW/Final/LukeLee/1, Feb, 2007 1335550 Perform different operations. As described above, the embodiment in which the inner product instruction is implemented by the ALU has the following functions: ' ALUO : D0=A0*B0+0, realizes X1*X2 ALU1 : D1=A1*B1+D0, realizes Y1*Y2+X1 *X2 ALU2 : D2=A2*B2+D Bu implementation Ζ1*Ζ2+Υ1*Υ2+Χ1*Χ2 ALU3 : D3=A3*B3+D2, realize W1*W2+Z1*Z2+ Υ1*Υ2 +Χ1*Χ2 Actual The result may be in the output of ALU3 and can be moved to any vector location for later use. In addition, as shown in Figure 2, in each ALU, Figure 2B processes 36-bit long format data. Figure 2C is a flow diagram illustrating a scalar processing unit similar to the flow chart of Figure 2A with a SIMD coefficient of 8 and data in a short format. This scalar processing unit contains the same number of ALUs as in Figure 2A. However, in Figure 2C each ALU separately processes two short format data streams (e.g., 18-bit elements, not 36-bit elements). ). As shown, the 2C graph contains vector stream data processing, with several scalar ALUs with short format data and a SIMD coefficient of 8. This means that each ALU can process eight sets of input data and produce eight results based on the same instruction for different delay times. More specifically, the vector data can be 18 bits (short format), unlike the aforementioned 3 6 bits (long format). More specifically, the vector element W1 in the previous example is now divided into two short format elements W1.0 and W1.1. Similarly, X, Y, and Z, as well as other data sets 2, 3, and 4, are also represented in short format data. In addition, Figure 2B also shows that the data entered into these ALUs is not necessarily related to a vector element data set. More specifically,

Client's Docket No.: S3U04-0012-TW TT's Docket N〇: 0608-A41110-TW/Final/LukeLee/1, Feb, 2007 16 1335550 • As with the input of each ALU, the data is not necessarily related to each other. The ALU is also not limited to the processing vector data set. This embodiment also includes several separate or divergent ALUs to process short-form data more efficiently. More specifically, the data XI.〇 is input to the left half of ALU0 (ALU0.0), while the right half of ALUO (ALU0.1) receives data X1.1. The data entered into ALU0.0 and ALU0.1 are processed and sent to output buffers S1.0 and S1.1, respectively. Similarly, data X2.0 and X2.1 are sent to the left half (ALU1.0) and the right half of ALU1 (ALU1.1). As shown, ALU 1.0 and ALU 1.1 processed data later than when processing data with ALU 0.0 and ALU 0.1. When the data is processed, ALU1.0 and ALU1.1 send the output data to output buffers 52.0 and S2.1, respectively. In the same way, ALU 2.0 and ALU 2.1 receive data X3.0 and X3.1, respectively. After processing the received data, ALU 2.0 and ALU 2.1 respectively transmit the output data to output buffers S3.0 and S3.1. In addition, the data processing of ALU2.0 and ALU2.1 is later than the data processing of the previous ALU. * As with previous operations, ALU 3.0 and ALU 3.1 receive data X4.0 and X4.1, respectively. After processing the received data (from ALU 2.0 and ALU 2.1), ALU 3.0 and ALU 3.1 respectively transmit the output data to output buffers 54.0 and S4.1. Since all eight ALUs (physically visible as four dual-channel ALUs, each logically split into two halves) execute the same instruction, the SIMD coefficient of Figure 2C is 8. In addition, the ALU in Figure 2C can be used to receive and process 18-bit (short-format) data, and 3 6-bit (long format)

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 1335550 Information. Fig. 2D is a flow chart illustrating a scalar unit, similar to the flowchart of Fig. 2A, with a SIMD coefficient of 4 and data in a long format. Figure 2D contains vector stream data processing for short format scalar ALUs. As shown, the data entered into the ALU is similar to the 2C diagram and can be a data frame architecture or an architecture that is not a data set. In addition, as in the previous example, the data X1.0 and X1.1 are input to ALU0.0 and ALUO". However, in this example, ALU0.1 is slightly delayed compared to ALU0.0 and uses the result of ALU0.0. In addition, ALU0.1 not only receives input data from XI.1, but also receives data from the output of ALU0.0. Similarly, ALU 1.0 receives the data X2.0, processes the received data, and outputs the processed data to ALU 1.1. ALU1.1 receives the output data from ALU 1.0 and data X2.1. After processing the received data, ALU 1.1 outputs the processed data to the output buffer 52.1. ALU2.0 receives the data X3.0, processes the received data, and outputs the result to ALU2.1. ALU2.1 receives the output data of ALU2.0 and also receives data X3.1. ALU 2.1 processes the received data and outputs the result to output buffer 53.1. ALU3.0 receives input data X4.0. ALU 3.0 processes the received data and outputs the processed data to ALU 3.1. ALU 3.1 receives the output data from ALU 3.0 and also receives data X4.1. ALU 3.1 processes the received data and transmits the processed data to output buffer S4.1. Thus an embodiment of the ALU can be used to implement the following functions: ALU0.0: d0.0=a0.0*b0.0+0 ALU0.1: d0.1=a0.1*b0.1+d0.0 ALU1.0 : dl.0=al.0*bl.0+0

Client's Docket No.: S3U04-0012-TW TT’s Docket No:0608-A41110-TW/Final/LukeLee/1, Feb,2007 18 1335550

- ALUl.l : dl.l=al.l*bl.l+dl.O ALU2.0 : d2.0=a2.0*b2.0+0 ALU2.1 : d2.1=a2.1*b2 .1+d2.0 ALU3.0 : d3.0=a3.0*b3.0+0 ALU3.1 : d3.1=a3.1*b3.1+d3.0 As if there are eight ALU processing materials but Only four outputs are the result of the operation, and the SIMD coefficient of the logic circuit of the 2D diagram is 4. In addition, when ALU0.0 transmits data to ALU0.1, ALU0.1 has a slight delay compared to ALU0.0. ALU0.1 can wait for ALU0.0 to process data X1.0 before receiving and processing the output data and data X1.1 of ALU0.0. Similar delays and processing are also performed on the remaining ALUs. Figure 3 is a logical architecture of an even-pair scalar ALU that can handle dual formats, illustrating the processing characteristics of Figures 1 and 2A-2D. More particularly, Figure 3 includes several embodiments of a stream data processor that can be configured to process data in any of several formats. At least one embodiment includes processing a plurality of first * sets of short format floating point data in response to receiving a short format control signal of the instruction set. The first scalar ALU, in response to receiving a long format control signal in the command set, is also used to process the first set of long format floating point data. In addition, some embodiments include a second ALU for processing a plurality of second sets of short format floating point data in response to receiving one of the short format control signals of the instruction set; and processing the signal according to one of the long format control signals of the received instruction set a second set of long format floating point data; receiving processed data from the first ALU; and controlling the input data and processing the processed data from the first ALU according to one of the instruction sets. Some embodiments include an SFU for the amount of

Client's Docket No.: S3U04-0012-TW TT’s Docket No: 0608-A41110-TW/Final/LukeLee/1, Feb, 2007 19 External calculation function to the first ALU and the second ALU. Furthermore, this embodiment is designed to allow the stream processor design to functionally separate at least one pair of ALUs in response to receiving short format data for the benefit of short format and long format dual format processing, ie The SIMD coefficient is variable. - The instruction set for this embodiment includes at least one instruction to process at least one of the following modes: short format operand mode, long format operand mode, and coherent format late mode. The instruction set of some embodiments is designed to control a variable SIMD overlay mode for processing when the output data of the first ALU is transferred to the second ALU in the extended format mode, and when the output data of the first ALU When the operands in the short format mode are transferred to the -ALU, there are two different cases. More specifically, the two ALUs 310 and ALU 32 of the Fig. 3 map the long data format and the short data format with the SIMD coefficients of 2 and 4, respectively. The described architecture displays a data path that includes a region multiplier 'and adder' combined with a region multiply accumulate (MACC) that can handle short format and long format data. In this example, data from the SFU is received at the accumulator registor 370 of the ALUO and ALU1. Coupled to the accumulator is a cache memory input data module 372 and an ALU input port (port) p〇 376. The ALU input 淳P0376 can process 72 bits into four segments. Lightly connected to the cache input data 372 is the ALU input 埠 P1 378. Similar to the ALU input 埠P0 376, the ALU input 埠P1 378 can also process 72-bit data into four segments of 18 bits. Coupled to the ALU input 埠p 1 378 is the ALU input 埠P2 380, which can be used to process 72-bit data into four segments

Client's Docket No.: S3U04-0012-TW TT’s Docket No: 0608-A41110-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 20 1335550 18-bit. ^ Combined to ALU input 淳p〇 376, AUJ round 淳 ρ 378, and and output ^ person 埠 P2 38Q is ALUG 310, which includes the input multiplexer 382a Ershigong 384a. The input multiplexer 382a includes an output 埠ch,

The A0L 7, the machine's and the muscle input multiplexer 384a contain outputs 埠H, A〇L, B1H, and CL. The output 珲CH ί is merged into the addition, and the & outputs 埠Α1Η and B0L are coupled to the multiplier 386a. Multiplier = also turns to adder 396a. The outputs 埠A1L and B1L are combined to the method. 〇 388a, multiplier 388a is coupled to 13-bit shifter 371a, which is coupled to adder 396a. The port is input to the 394a, and the outputs 埠a〇H and Β0Η ♦ Mahe to the multiply buckle 392a. Multiplier 392a is also coupled to adder 399a. The outputs 埠A〇L and B1H are coupled to a multiplier 39〇a, the multiplier 39〇& is coupled to an i3 bit shifter 373a, and the 13-bit shifter 373a is coupled to an adder 39%. The output 埠CL is coupled to an adder 399a. Adders 396a and 399a are coupled together via a 13-bit shifting and enabling device 398a. Multiply Accumulate Units (MACC) 394a and 397a are coupled to adders 396a and 399a, respectively. The outputs of Additions 396a and 399a are coupled to a low output 埠 dl and a high output 埠 DH, respectively. Inputs 埠 ALU port P0 376, ALU port P1 378, and ALU port P2 380 are also coupled to ALU1 320 via delay register 383. delay

The register 383 is coupled to the input multiplexers 382b and 384b. The output 埠CH of input multiplexer 382b is coupled to adder 396b. Outputs A1H and B0L are coupled to multiplier 386b, which is coupled to adder 396b. Output 埠A1L

Client's Docket No.: S3U04-0012-TW TT's Docket No: 0608-A4 II 10-TW/Final/LukeLee (Li Zongxuan) /], Feb, 2007 1335550 and B1L lightly coupled to the multiplier 3 8 gb, which passes 13 bits A meta-shifter 3 71 b, and a bit shifter 371b is coupled to adder 396b. The output of input multiplexer 384b contains A 〇 H and B 〇 H, which are coupled to multiplier 392b. Multiplier 392b is coupled to adder 399b. Outputs A0L and B1H are coupled to multiplier 390b, which is coupled to adder 399b via a 13-bit shifter 373b, 13-bit shifter 373b. Output 埠CL is coupled to adder 399b. Adders 396b and 399b are coupled together via a 13-bit shifter and enabling device 398b. Multiply Accumulate Singles (MACC) 394b and 397b are coupled to adders 396b and 399b, respectively. Adder 396b is coupled to low output 珲 DL, and adder 39 耦合 is coupled to high output 埠 hl. In this example there is a bypass element 395 and an output CL data element 393 coupled between the ALU 310 and the ALU 320 for a clock cycle delay of operation of the ALU1 320. The point to note is that the components depicted in Figure 3 illustrate the logical architecture of the operation. More specifically, the architecture depicted in Figure 3 illustrates the design principles of ALUs with separate resource paths and variable SIMD coefficients. Figure 4 illustrates a stream processing unit with a dual scalar ALU, similar to the architecture of Figure 3. As shown, the data is input to the cache memory unit, which includes LQ, L1, SO, SI, S2, S3, and so on. The cache memory unit 472 transfers the stored data to the memory output multiplexer 474, which is coupled to the inputs port P0 476, port P1 478, and port P2 48〇. pcJ p〇 476, port PI 478, and P〇rt P2 480 are also coupled to input multiplexer 482a, which is lightly coupled to ALUO. ALU0 calculates a〇*b〇+c〇 equal to DO in this example, and the result is output to d〇L.

Client's Docket No·: S3U04-0012-TW TT's Docket N〇:0608-A4111 〇-TW/Final/LukeLee//, i, Feb, 2007 22 1335550 port P0 476, port PI 478, and port P2 4 To the delay register 483, the delay register 483 is coupled to the input multiplexer 482b, and then to the ALU1°ALU1. In this example, A1*B1+C1+D0 is calculated to be equal to D1, and the result is output to D1L. The output 埠D0L of ALU0 is also coupled to ALU1. Those skilled in the art will appreciate that this particular example calculates the output value of ALU0 in ALm. More specifically, ALU0 calculates the value of D0, which is passed to delay register 386. D0 is transferred from delay register 386 to ALU1 to calculate D1. Coupled to the outputs of ALU0 and ALU1 is a multiplexer 484 that is coupled to the SFU 470 common to ALU0 and ALU1. SFU 470 also switches to the input of ALU0 and (via delay register 483) the input of ALU1. The outputs of ALU() and ALU1 are also coupled to cache memory unit 472 and other units. Figure 4 also includes a SIMD microcode controller 488 for determining and transmitting the desired operational control signals to ALU0 and ALU1. Lightly coupled to the SIMD microcode controller 488 is the ALU control and addressing component 490. Delay register 483 is coupled between ALU control and positioning component 490 and ALU1. It is to be noted that Fig. 3 is an embodiment for short format data processing and Fig. 4 is an embodiment for long format data processing. More particularly, although the disclosed embodiments of the present invention include the ability to handle short formats, long formats, and mixed formats, 荨, etc., many of these examples may also include processing of rearrangement. Figure 5A is a diagram illustrating the arithmetic functions of the even-pair ALU. Such an ALU has been described in Figures 3 and 4. This table shows all possible operations for ALU0 and ALU1. These operations can be as short as 18 bits and as long as 36 bits.

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan) / 1, Feb, 2007 23 1335550 ' and mixed 18-36 bit floating point data. All operations are individually pong group: regular, mixed, and crossover operations. Each group has four times/twice the type operation of normal operation and 18/36 bit data. The quadruple/double pattern uses data that is passed between blocks of the same ALU or between ALU0 and ALU1. At the top of the chart, there are several lines with the same name as the inputs of ALU0 and ALU1 in Figure 3, and the same data path control signals as shown. Each operation is described by two columns: the first column represents the input data from ALU珲Ρ0, Ρ卜, and P2 (special elements such as Ρ0·0, Ρ0·1, etc.), • and the status of some data path control signals. The second column describes the formula, and the result of the formula is passed to the outputs 埠dl and dh. The last line contains information about the SIMD coefficients of the even pair of ALUs under special operation. Such even ALUs can be replicated several times to increase the overall SIMD coefficient. The right side of the table contains the abbreviation notes for the operation. The ALU hardware's arithmetic function uses the multiplication symbol "S" and the addition symbol "s", as well as the multiply-accumulator register (MAC) for special operations. The following detailed instruction set description illustrates the overall functionality of the stream processor. ® Figure 5B contains a GPU with one of the SIMD stream processors as the computing core. This example contains four stream processors and each processor contains four pairs of ALUs and two SFUs. Embodiments of the stream processor are used to process different types of data (geometry and pixels/texels); by using different instructions in the instruction set, variable SIMD coefficients can be provided for the different types of data used. Streaming processor instructions may have a length of 3 to 9 bytes, depending on the instruction type and address mode. The instruction consists of the following parts: (1) the subject (a

Client's Docket No.: S3U04-0012-TW TT's Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 24 1335550 General Command and Flow Control Instructions); (2) Command Preposition. The result of the general instruction can be passed to the SFU, or the execution of the general instruction can be repeated; and (3) the instruction word can be modified, the operand size can be changed, the flag is set, and the control result is written back. The principle of instruction coding is listed as follows: The sample of the order of the food group 4:: 2nd bit of the instruction paper:::: The 3^ byte of the instruction bit address group general instruction format operation code operation; Sister operation; ^ sister instruction preposition (special function unit) pre-operation code no or no instruction preposition (repeated instruction control) repeated operation code present value no no instruction modification preposition side operation code operation element modification word no data length Preposition data length operation code 1 data length operation code 2 no control flow instruction control flow operation code 1 control flow operation code 2 replacement word 1 replacement word 2

Table 1 Based on this format, the stream processor has the following instruction sets that are functionally categorized. An example of the stream processor instruction set is as follows: Function format value instruction general instruction Is1 byte 2nd byte 3"*byte 4th-9th byte MAC multiplication accumulation 0000 OOsD short address A short address B/High Part AB and D Address 1 MUL Multiply 0000 010D Short Address A Short Address B/High Part AB and D Address 1 ADD Force α 0000 100D Short Address A Short Address C/High Part AC and D Address 1 SUB minus 0000 101D Short Address A Short Address C/High Part AC and D Address 1 MAD Multiply Plus (No MACC) 0000 11sD Short Address A Short Address B/High B, C and D Addresses 1

Clients Docket No.: S3U04-0012-TW TT's DocketN〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb, 2007 25 1335550 MAC Multiply Accumulate Long Format MAC Multiply Accumulate Short B Address MAC Multiply Accumulate Length B address ADD addition long format SUB subtraction long format MOV move

ADAACC addition long format SBAACC subtraction short format MAAACC multiplication accumulation MUAACC multiplication MPAACC multiplication plus ACC MMAACC multiplication minus ACC

Part A 01BB CCsD D High Part A7 Short Address A 0100 OCsD D High Part A7 Short Address A 0101 OCsD D High Part A7 Short Address A 0110 0C0D D High Part A7 Short Address A 0110 0C1D D Two Parts A7 Short Address A 0110 lOxD D High Part A7 Short Address A 0110 110D D High Part A7 Short Address A 0110 HID D High Part A7 Short Address A 0111 OCsD D High Part A7 Short Address A 0111 lOsD D High Part A7 Short Address A 0111 110D D High Part A7 Short Address A 0111 111D D High Part A7 Short Address AB, C and D Address B, C and D Address 1 B, C and D Address 1 B, C and D Bits Address 1 B, C and D Address 1 B, C and D Address 1 B, C and D Address 1 B, C and D Address 1 B, C and D Address 1 B, C and D Address 1 B, C and D address 1 B, C and D address 1

Outer product XRS outer product mixing BLN mixing DP2 inner product 2 BLF superimposed hybrid DPF superimposed inner product BL8 short mixed SMD 8 DPM inner product mixed data inner product 4

0001 OSsD Short Address A

Short address B/high Part A B, C and D addresses

0010 OSsD Short Address A Short Address B/High Part A 0010 ISsD Short Address A Short Address B/High Part A 0011 OSsD Short Address A Short Address B/High Part A 0011 ISsD Short Address A Short Address B/High Part A 1101 OSsD Short Address A Short Address B/High Part A 1101 ISsD Short Address A Short Address B/High Part AB, C and D Address 1 B and D Address 1 B, C And D address 1 B and D address 1 B, C and D address 1 B and D address 1

Client's Docket No.: S3U04-0012-TW TT's Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb, 2007 26 1335550 DP4 inner product 4 1100 OSsD short address A short address B/high Part A DPI inner product 4 with IDCT recombination 1100 ISsD short address A short address B/high part A instruction preposition Γ byte 2"1 byte 3rt byte SFU pass preposition REC passed to 1/X 0001 1001 SQR Pass to SQRT 0001 1011 RSQ pass to 1/SQRT 0001 1011 LOG pass to LOG 0001 1101 EXP pass to EXP 0001 1110 SIN pass to SIN 0001 1111 B, C and D address 1 B, C and D address 1 4th - 9th Bit

Note to Table 2: Depending on the current operation element B, C, and the operand length of the destination 2 - If the instruction format is short format, the "S" block only affects the data exchange (swap) without affecting the write mask. (write masking) 3 - If the instruction format is short format or mixed format 'S' rotten bit only affects data exchange without affecting write mask 4- if inner product and outer product instruction symbol are used for second derivative 5 - if inner product 4 The instruction symbol is used for the second derivative and the fourth differentiation; the default value of the address of the operation element C is the address of the operation element A plus 1 the function format repeats the preposition Ist byte 2nd byte 3rd byte 4th- 9th byte REP repeated instruction short no MACC ΠΙΟΟπτ REP repeated instruction short no MACC lllOlrrr

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 1335550

REP repeated instruction without MACC lOOOrrrr repeat imm8 REP without repeated MACC 1001 rrrr repeat one imm8 REP repeated instruction on lOlOnrr MACC repeat_imm8 REP repeated instruction 1011 rrrr MACC repeat_imm8 instruction modifier command preposition Γ byte 2nd bit Tuple 3rd byte SCS setting size 1111 1100 set_scale_i mm8 SCT switching size 1111 1101 set_scale_i mm8 0PS setting operand field mi mo set_ops_imm 8 OPT switching operand field 1111 1111 set-ops-imm 8 CFS condition flag setting 1111 Offf set_cf_imm8 WBS conditional writeback setting 0000 0111 0010 set_wb_imm4 WBT conditional writeback switching 0000 0111 0011 set_wb_imm4 data length preposition DLS data length setting 0000 0111 0100 11 LL DLT data length switching 0000 0111 0101 11 LL flow control branch With the call 1st byte 2nd byte 3rt byte IF condition with release label trigger 0000 0111 0001 00 WW disp8 IF condition with absolute label trigger 0000 0111 0001 01 W displ6_low JC relative condition jump 0000 0111 0001 10 WW disp8 4th- 9th bit 4th - 9th byte displ6_high Client's Docket No.: S3U04-0012-TW TT’s Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/l,Feb,2007 28 1335550

JC absolute condition 0000 0111 0001 11 WW displ6_low JMP unconditional relative jump 0000 0111 0000 10 00 disp8 JMP unconditional absolute s 0000 0111 0000 11 00 displ6_low CALL unconditional relative call 0000 0111 0000 10 01 disp8 CALL unconditional absolute call 0000 0111 0000 11 01 displ6_low RET unconditional return 0000 0111 0000 10 10 ENDIF relative unconditional jump setting condition off 0000 0111 0000 10 11 disp8 ENDIF absolute unconditional jump setting condition off 0000 0111 0000 11 11 displ6_low loop control Ist byte 2nd byte 3rt byte FOR Set loop index counter 0000 0110 set_cnt_imm 8 LOOP relatively short loop 0000 0111 0000 00 II disp8 LOOP relatively long loop 0000 0111 0000 01 II displ6—low Lookup table LKP constant page lookup table 0000 0111 0000 11 10 short address A

Displ6_high displ6_hi^i displ6_high displ6_high 4th - 9th byte

Displ6—hi by hign part A Note to Table 3: L depends on the length of the operands of the existing operands B, C, and destination • 2- If the instruction format is short format, the “S” field only affects data exchange (swap Does not affect the write masking (write masking) MAC there is MACC, repeated from the operation unit C initialization, when not repeated (the operation element C is ignored) is not initialized 2 - no MACC, if the bit "C" is set Address of operand C = address of operand B + "cc" +1 3- MACC and initialized with "0" when repeated, "cc" column

Clients Docket No.: S3U04-0012-TW TT,s Docket N〇:0608-A41110-TW/Fina!/LukeLee(李宗轩)/1,Feb, 2007 1335550 Bits always select the address of the operand c. - in the order of {operating element A, connecting element B, operand C, destination}, depending on the existing operand and length. Block description symbol difficult to describe A operand AB operand BC operand CD destination d destination to ACC write enable S exchange overlap part S mixed symbol, DP4 and outer product rrr(r) repeat indicator ww conditional branch Write back control Π conditional loop control (same branch and writeback conditions)

Table 4

D Destination to ACC 0 Start write to ACC 1 Close write to ACC

Table 5 S Exchange stacking points 0 No swapping 1 Exchange stacking part Table 6 WW Condition Write back control 00 Always write 01 Write ^ If only zero label setting (=0) 10 Write ^ If only symbol standard Setting (<0) 1 1 Writing ^ If only zero or symbol label setting (5)) Table 7

Client's Docket No.: S3U04-0012-TW TT,s Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb, 2007 1335550

Rrr Repeat count 000 Repeat times See set value 001 Repeat to 2 010 Repeat to 3 Oil Repeat to 4 100 Repeat to loop or divergence indicator 101 Repeat to 6 110 Repeat to 7 111 Repeat to 8 WW orH ~~~~--- One and loop control ----- 00 01 If there is only zero label setting (= -〇) 10 If only the symbol label setting ( <0) 11 is executed, if there is only zero or Symbol mark ^ (cut) ° Table 9 f 8 ^ x〇I xl I x2 I x3

Ox lx 2x 3x

MAC

BLN

BLF x4 x5

X7 I x8 ADD m / ·-

R E C xA xB xC xD SUB MAD SQ R RS Q ;rsr, η,; vd L 〇 G ® Si ^ N DP2

DPF

4x 5x MAC short B address MAC long B address ADD SUB ADD SUB ADD SUB ADD 6x long long long long long long form form form form form form 7x 8x MAC ACC multiply-accumulate REP long format counting up no MACC 9x

REP long format counting down with MACC

Ax

REP long format counting up no MACC

Bx

REP long format counting down with MACC

Cx DP4

DPI

Dx BL8

DPM

Ex

REP short format without MACC

REP short format with MACC

Fx

CFS

;··· sc sc 6η s T Table 10: Instruction Encoding Master Matrix (instruction first byte)

07 x0 xl x2 x3 x8 x5 x6 x7 x8 x9 xA xB xC xD 5 NV Net: J C R E J C L Οχ LOOPrel LOOP abs M ET N M A 〇: 0 A K

Client’s Docket No·: S3U04-0012-TW TT’s Docket Ν〇:0608-Α4 Π 10-TW/Final/LukeLee(李宗轩)/!,Feb,2007 3l 1335550

Table 11: Instruction Encoding Master Matrix (Instruction Second Byte) Figure 6 is similar to the ALU of Figures 3 and 4, illustrating the logical architecture and flow diagram of a stream processor with four pure ALUs. As shown in the figure, the input data is sent to four ALUs, which are labeled as ALUO, ALU, and ALU2.

And ALU3. More specifically, the input data 6〇2a is transmitted to the input port of the ALU〇. In addition, the control and address signals from the command decoder 6〇2e are input to ALU0' and the common data 6〇2f is also input to alu〇. Information from SFU 670 is also entered into ALU〇. After the instruction execution cycle, the data is processed in ALU0. During execution cycle 1, input data 602b is stored in delay register 683a and then transferred to the input port of ALU1. The control and address signals from the instruction decoder 6〇2e are stored in the delay register 683d and then transferred to the input port of the ALU1. Similarly, the common data 602f is stored in the delay register 683e and then input to the ALU1. Information from SFU670 is transmitted without delay to

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan) / 1 Feb 2007 , 32 1335550 ALU1. At the time of the deduction execution period 2, ALU1 processes the incoming data. At the time of the binding cycle 1, the input data 602c is stored in the delay register 683b. During the execution cycle 2, the data is stored in the delay register. The input data 602c is then transferred to ALU2. ALU2 also receives control and address signals via the delay register and the 683g 攸 and decoder decoders 〇2e. Similarly, the common data is transmitted to the ALU2〇ALU3 via the delay registers 683e and 683h, and the input data 6〇2d is received. The instruction execution cycle 1 is via the delay register 683c, and the instruction execution cycle 2 is delayed by the temporary storage. 683q, in the instruction execution cycle 3, via the delay register 683f. Similarly, the control decoder and the address signal 6〇2e' received by the ALU3 are in the instruction execution cycle 1 via the delay register 683d. Execution cycle 2 will pass through delay register 683g, and will pass through the delay register during instruction execution cycle 3. The common data received by ALU3 will be buffered to 683e' via the delay during the instruction execution cycle, via delay register 683h during instruction execution cycle 2, and via delay register 683j. during instruction execution cycle 3. The output of ALU3 is passed to a four-slot output buffer 604 having a width 和 and a multiplexer 672 that is coupled to an input port of the SFU 670. The output from ALU0, ALU 1, and ALU2 is transmitted to multiplexer 672. The output of ALU2 is passed to output buffer 4 604 via delay register 683 。. The output of ALU1 is passed to output buffer 4 604 via delay registers 6831 and 683ri. The output of ALU0 is transferred to output buffer 4 604 via delay registers 683r, 683k, and 683m. It is worth noting that in at least one embodiment, Figure 6 can be designed with logic to remove at least one delay from the data path. Figure 7 is a flow chart illustrating the normalization direction in the vector ALU

Client^ Docket No.: S3U04-0012-TW TT’s DocketN〇: 0608-A4111〇-TW/Final/LukeLee (Li Zongxuan)/1, Febs 2007 1335550 Differential processing. More specifically, the normalized vector difference can be considered as an embodiment when it is implemented in the traditional vector ALU and the streamed SIMD scalar ALU. Figure 7A shows the data flow of the normalized vector difference calculation. For example, the vector architecture calculated by the difference between vector normalization (vector VI and V2) is implemented as follows: //Data configuration: Vl->r0.xyzw V2->rl.xyzw (x,y,z,w is a graphic The element of the data vector) // The program of the vector ALU SUB r2, r〇, rl // The subtraction of all elements DP3 r3.x, r2, r2 // The inner product of the three elements produces the X element RSQ r3.x, r3.x // Generate the reciprocal square root of the X element MULr2, r2, r3.x// Use the result of RSQ to adjust the value of all elements to process 4 sets of data. This process can be repeated 4 times and takes 16 instruction cycles. Using the scalar ALU of Figure 7B-C, the same task can be achieved in the SIMD stream processor: Example: Differences in vector normalization (vectors V1 and V2) Comparison of traditional practices with SIMD streaming scalar ALU architecture. SIMD application for scalar ALU: Vl->r0.xyzw=r0[0], r0[l], r0[2],r0[3] V2->rl.xyZW=ri[〇],ri[i ], ri[2], rl[3]. (x, y, z, and w are elements of the image data vector, r[0-3] represents separate scalar quantities) Vector ALU Streaming SIMD scalar ALU Annotation SUBr2, rf), rl Repl(j<3) SUB r2[j], lOULrlU] Subtraction of all elements DP3 γ3.χ5τ2, r2 Repl(j<3) MAC Null, r2 [j],r2[j] The inner product of all elements is generated to the χ element, which is multiplied and accumulated

Clienfs Docket No.: S3U04-0012-TW TT’s Docket 1^〇: 0608-八4"10-TW/Fina!/LukeLee(李宗轩)/1,Feb,2007

Figure 8 of the example of the work ^ is the -ALU module, which implements the ALU of Figure 6. More specifically, 'Fig. 8 can be regarded as the sixth figure: ::::": The example consists of four parts: a data path with double 874. - red early and necessary input and output multiplexer, Temporarily stored as a library, including a delay register 883a, writing back to the memory crying and a number of accumulators 878 for each thread; - 轫 ^ having a regional ALU staging table 880; and a regional control unit, presenting State machine and address generator 882. Eight', as shown, the input (four) bile is transmitted to the multiplexer 870 in the partial data path of the ALU. The input data lm, IN2, and m3 are respectively transmitted to

Client's Docket No.: S3U04-0012-TW TT s Docket N〇:0608-A41110-TW/Final/Luk:eLee(李宗轩)/1,Feb, 2〇07 35 (1) 5550 Delayed Register 8S3c, Delayed Staging 88μ' and temporary storage = output. The control and address signals (3) are transmitted to the delay temporary: two: , , and after the output, also transmitted to the area control part of A L U (four) = address generation please 2. The common data wheel (10) is transmitted to the delay temporary = b攸 delay register 883b, and the common data is transmitted to the round trip, and is also input to the multiplexer 870.

The multiplexer 87 receives the data from the SRAM temporary storage table 88, the data written back to the temporary register 876, and the data of the thread accumulation 8. In the figure, the multiplexer 87Q has three output ports, each of which transmits the data of the Μ bit. The wheel 埠 of the multiplexer (10) is lightly coupled to a multiply-accumulate unit (MACC) 872, which is detailed below. The output of the dual format p2 is summed to the second input bee of the multiplexer m: to the input of the temporary storage H 876. As previously described, the wheel 埠 of the memory 876 is coupled to the wheel 埠 of the multiplexer 87 埠, and the input 埠 WDATA of the SRAM temporary table 880 is rotated to D: 阜FW. The output of the multiplexer 874 is lightly coupled to the ECU load = 8' Thread Accumulator Register, 878 and then multiplexed to the multiplexer _. As described above, the control and address signal CAI is coupled to the control state machine and address generator 882 via delay staging, =in. The control state machine ^ generator 882 outputs the data to the rotation of the SRAM temporary table 88, RA, WA, and WE. lRA0, Fig. 9 is similar to the AUJ' of Figs. 3 and 4, which shows that there are four stream processor modules, and the scalar processor ALU described in Fig. 8 stands. This architecture shows the use of the same scalar processing as $8 Figure 4 to build the module.

Client's Docket No.: S3U04-0012-TW TT>s Docket No:0608-A41110-TW/Fmal/LukeLee(# Feb, 2007 1335550 SIMD Streaming Multiprocessor. This way simplifies the design and verification work, it can be applied To build a machine module of a SIMD stream processor that can be large or small. Similarly, similar to Figure 8, the control and address signals (CAI of Figure 8) are input to the CAI of ALU0. Common data (8th The CDI of the figure is input to the CDI of ALU0. As shown in Figure 9, ALUO receives the data input from input buffer 4χΜ directly to ΙΝ0. ALU0 then processes the received data, but the processed data is then input to the three delay registers. (Like the delay registers 683r, 683k, and 683m in Fig. 6.) In Fig. 9, these delays can be realized by connecting the output of ALU0 to the input port. Further, the data received from ΙΝ0 is processed. After the output is coupled to 00.00 to IN3, IN3 delays the data (first delay) and then outputs to 03. 03 is coupled to IN2, IN2 delays the data (second delay) and then outputs to 02. 02 coupled to INI, IN1 delays the data (third delay) and then outputs it to 〇1. The output of 01 is coupled to the output buffer 4. For ALU1, the control and address signals and the common data signal are received at the CAI and CDI of ALU1, respectively. As shown in Figures 6 and 8, these signals are subject to a delay before ALU1 is received. This delay is represented by the ACI0 output to CA0 and CD0, and then to the CAI and CDI of ALU1. The input data from the input buffer 4χΜ is received at ΙΝ1 of ALU1. As shown in Figure 6, the input data is processed in ALU1. It is subjected to a delay (such as delay register 683a in Fig. 6). This delay is achieved by coupling outputs 埠01 to IN0 in Fig. 9. The data is processed and output to 00. Output 埠00 is coupled to IN3 to create an output. Delay, as shown in Figure 6. Two output delays are delayed by IN3 to 03 (delay register 6831)

Client's Docket No.: S3U04-0012-TW TT,s Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1, Feb, 2007 133555〇%, and leg to 02 delay (delay register 683n) created. After these delays, the output data can be transferred to the output buffer 4χΜ. 2k As for ALU2, control and address signals and common data ALU2 receives two delays before receiving, and then receives them in CDI of ALU2 respectively. Input data from the input buffer 4A is received at the ALU2. As shown in Fig. 6, in order to achieve the input data, two delays are received in the ALU2 processing 2, and the received signal processing (in the delay buffer of Fig. 6 = 683b) is output to 〇2. This signal is received at ΙΝ1, processed (delayed by 683p) and output to 01. This signal is received at IN〇, processed (=, sub-register 683p) and output to 〇〇. To achieve the output delay, the poll is transferred to the IN3' processing (delay register 683〇) and then to the input buffer 4χΜ. & As for ALU3, control and address signals and common data signals are received at ALU3 and CDI after three delays (ALU0, ALm, and ALU2). The input data is transferred to IN3 and is subject to three input delays. The first input delay is delayed by the delay between IN3 and 03 of ALU3 (delay register 683c). The input data is transferred from 〇3 to IN2 and then subjected to a second delay (delay register 683q) at ALlJS3. This input data is transferred from 〇2 to IN1. After the input data is delayed (delay register 683f), it is output to 〇 1. The input data is transferred to IN0' for processing and output to 〇〇, and then to the output buffer 4xM. Further, as shown in Fig. 8, the output data is coupled to the output 埠fW for transmission to the SFU 980. The rounded data can be transferred to the multiplexer 970. The multiplexer 970 is consuming to the SFU 980' which can further process the output data for input to

Client's Docket No.: S3U04-0012-TW TT's Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan yi, Feb, 2007 38 1335550 *- Input of each ALU 珲 SF. The streaming ALU module Part of is a multiply-accumulate unit that can be used to support variable SIMD coefficient processing, which can compute dual floating point data formats and the ability to stack (reduce) SIMD coefficients and process data in parallel. It is worth noting in this disclosure that the abbreviations are "MAC" refers to the multiply-accumulate register, and "MACC" and "Multiply Accumulate Unit" refer to a dual format multiply-accumulate unit, such as element 872 of Figure 8. In addition, as shown in Figure 9, ALU0, ALIH, Embodiments of ALU2, and ALU3 can receive operational data from the SFU, and the operational data is used to indicate the operations performed on the received data. Similarly, in some embodiments, ALU0 can transmit common data to ALU1, ALU1 can transmit common data. The ALU2 and ALU2 can transmit the common data to the ALU 3. The 10A-C diagram illustrates the data flow and format of the MACC unit MACC as shown in Fig. 8. More specifically, please refer to Fig. 8, the MACC unit 872 can be used everywhere. Long format data (floating point, integer, etc.), short format data (floating point, integer, etc.), and mixed format data (floating point, integer number, etc.), and its performance will increase when processing short format data Figure 10A illustrates the data flow logic architecture of the MACC unit and the ability to interpret two different data formats (ie, long floating point and short floating point formats). The following steps can be used to handle floating point arithmetic based on floating point arithmetic algorithms. Data: 1) Short and/or long exponent processing, when the exponents of the multiplicands are added and the exponents of the addition elements are subtracted. 2) The short and/or long operands are multiplied by the mantissas of the region multiplier.

Client's Docket No.: S3U04-0012-TW TT's Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb, 2007 1335550 3) ίΓί Long-numbered complement operations, based on operators and definitions Addition or subtraction operator modifier -modifier). 4) New and/or long base calibrations that are prior to addition/subtraction. 5) (ahgn job t) ’ It shifts according to the index. For multiple addition operations 减 subtraction. Addition of short and/or long bases / 6) 7) Addition/subtraction of short and/or long bases with pre-aligned MACC temporary crying content. The normalization of ^ may require a base shift of the associated index update before being passed to the output register. As shown in the second figure of the bit t, the long floating point data can be 36 bits, and the (10)th bit is the still index bit. An 18-bit table is not low-bit-bit 12-bit where the index value is expressed... The 16.13-bit represents the low-index Γ〇0-bit 12-bit represents the base symbol %, which is the high-base-part, the u_u-bit M24-m, 3 is also. , 1GC chart shows short floating point data, for the channel! Short floating point data. The two short-form data can be placed in the position of the first-generation data. More specifically, I ’ 0 bits are exponent bits e4. The 34th 31st bit is the high index bit (4). The base symbol (3) is the third unit, the 29th-18th is the high base = the elevation is the tree artifact (four) (four), the 17th surplus bit... The bit το is the low number e3_e〇. The base symbol % is the 12th bit, and the ll-o bit is the low base bit. Figure 11 is similar to the MACC unit of Figure 8 and implements the 10A diagram of the Client's Docket No.: S3U04-0012 She _ side deputy clear W / F shout ukeue (Li Zongxuan franchise, hire 1335550 material flow, detailing the internal logic architecture of the floating point data path of the MACC unit. More specifically, 'MACC unit 872, as shown in Figure 8, Simultaneous processing of short and long floating point data. The floating point data path of Figure 11 contains the following main parts '' and these main parts can be used to process a set of long operands (ABC) or two sets of short operands (2xabc). The index processing part processes the long index and the short index in the appropriate channel; 2) the base processing part, which processes the long index and the short base. The floating point data path of Figure 11 is implemented based on a floating point multiply and add algorithm with additional accumulated elements. The MACC unit 872 can be directed to a Short Expoent Calculation and Scale unit for chennale 0 (SECSO) 1120. SECSO 1120 receives five high-index bits of operand A (hereafter referred to as "al") from channel 1. In addition, SECSO 1120 receives five low-index bits of operand B (hereinafter referred to as "b0"), five bottom-index bits of operand al, five bottom-index bits of operand bl, and The fifth operand of the third operand cl (cl denoted as the operand of ab+c). • SECSO 1120 also receives the scale factors scal_c, scal_h, and scal_l of operands C, B, and A. The output of the SECSO 1120 contains a short exponent of 6 bits, which is passed to the Complement and Alignment Shifter Unit (CASU) 1139, which aligns the base before the addition. The SECSO 1120 also outputs a 6-bit short index to the final adder (CPA or CLA) and normalization unit 1147 to output the final value of the index and provide the final output from the floating point data path. Long Exponent Calculation and Resizing Unit (Long Exponent Calculation

Client's Docket No.: S3U04-0012-TW TT's Docket N〇:0608-A41110_TW/Final/LukeLee(李宗轩)/1,Feb,2007 41 l33555〇andScaleunit'LECs) mo receives the (7) bit of the combined operand and u The index data, the 1G bit index data in combination with the operands bG and bl, and the 1 bit in combination with the operands ch and d. Also received are the operand size coefficients scal_c and scaUl. The output of LECS 1〇4〇 consists of three: the 11-bit output of casu 1139, and the output of the final adder and the normalized unit 丨ι47. The Mixed Index and Short Exponent Calculation and Scale Unit Channel (MESEC1) 1130 receives the five low-index bits of the operand a0. In addition, MESEC1 1130 also receives the high-index five bits of the operand bl, the high index of the operand, the high index of the operand b0, the operand ch-e, the low index of the operand b〇, and the operand bl The low-index five-bit, and the high-index ten-bits of 汕 and 、, and cat(ch-e, d-e) eMESEC1 113〇 also receive seal-c, scal_h, and scal-1. MESEC1 113〇 outputs three sets of data (6 or 11 bits, depending on the special operand) to CASU ιΐ39, and Lu also outputs a 6-bit short index to the final adder and normalization unit 1147. As for the base portion of the channel ,, the multiplier 1131 receives the low base (13 bits) of the operand and the b 1 咼 base (13 bits). The multiplier 113 3 receives the operand al high base (13 bits) and the operand b low base (13 bits). Both multipliers 1131 and 1133 output 26 bits to the CASU 1139. In addition, the cl_m (13-bit) of channel 0 is received at CASU 1139, and the sign bits 兀sign_h, signj, and Sing_c are also. Similarly, the channel multiplier 1135 receives the high base (13 bits) of the operand a0 and the operand and the base (13 bits το). The multiplier 1137 receives the operand a 〇 low base

Client's Docket No.: S3U04-0012-TW TT's Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan yi, secret, 2〇〇7 1335550 negative β-position 兀) and operand bl high base (13 digits) yuan). The symbol bits signj^signj, and sing-c (long format), the operand modifiers abs_c and neg-c are all received in channel 1 by CASTJ1139. For short format operands, CASU 1139 outputs six 26-bit to multiple input adders (MAD CSA units) U41, which implement the Multiply-Add (MAD) step. The MAD CSA unit 1141 can be implemented with several carry storage adders (Carry_Save Adder, CSA) with four 37-bit signal (long format operand) inputs and two 39-bit signal inputs. The MAD CSA unit 1141 outputs two 2+26 bit outputs or a 2+40 bit (long format) output to a multiply accumulate carry store adder (maC CSA) unit 1145. The MAC CSA unit 1145 can be used to output two 5+26 bit short format outputs and one 5+40 bit long format output to the final adder and normalization unit 1147. The MAC CSA unit 1145 also outputs 5+40 bits (long format) and two sets of 5+26 bits (short format) to the multiply-accumulate register 1143, which is coupled to the complement and alignment shifter CASU (complement and alignment) Shifter) 1144 〇 CASU 1144 outputs two 5+26 bit signals and a 5+40 hop bit long format signal back to the MAC CSA unit 1145. The final adder and normalize early 1147 output two short format results 'each containing one sign bit, five exponential bits, and thirteen base bits (S5el3m). Furthermore, in at least one embodiment, the final adder and normalization unit 1M7 can output a long format operand in the form of sl〇e26m. The following two possible implementations of the dual format multiply-accumulate operation in Figure 11 are described: one is to separate short format data and long when we use separate circuits to process different data formats and share a unique output data/result buffer. format

Client's Docket No.: S3U04-0012-TW TT's Docket No: 0608-A41110-TW/Final/LukeLee (Li Zongxuan) / 1, Feb, 2007 1335550 Data path of the data; the other is, when we use the same circuit with additional words When the circuit interleaves short and long format data, it combines the data path of the short format data with the long format data. ';: Figure 12 is similar to the short exponential calculation channel of the 11th figure, indicating the exponential calculation of the separation. The short exponential channel receives the index of the exponents of the three short operands to calculate the exponential portion of the result, and the number of truncated bits needed to align the operand base. The short channel consists of four levels of exponential adders: multiplication ^ ^ knife-edge actuators 1212 and 1214, addition adders 12〇4, 12〇6, and 12〇8 °.匕> Claw/ί: The twisted states 1216, 1218, 1222, and 1224' of the load port and the adders 1241, 1244, and 1246 (2χ, 4χ, etc.) that adjust the operands. The short channel also contains multiplexes 1210, 1226, 1232, 1234, and 1236 to help the upper input and the yiAC index register 112 8 select the correct input. In addition, the winged, first includes a priority encoder 1220 that generates a control signal to a plurality of multiplexers based on whether the output of the selected force processor is positive or negative. , 咕 ° ° The result of the calculation of the base channel produces some signals for use in the short base channel. The operation, the gentleman's watch, the 'short-bottom channel produces a small amount of signal to the short-bottom channel. These signals are described below: the exponential portion of channel 0, and a group of offset signals for the base. The bit signal contains the displacement of the short operand c, the displacement of the short operands a and b, and the displacement of the C and MACC register values. Table 13 describes the carry-transfer adder r r , larry

Propagate Adder ' CPA) The output control function of the 1208 symbol output, which defines the route of each output signal (see the 12-character code table xl x2 & + rounds): Condition 0 Xl CPA 1208A Condition 1 x2 CPA 1208B Condition 2 x3 CPA 1208C code N0T(cl> alh *b〇l) NOT(all*blh>alh*b01) alh*b01>all*blh N0T(cl> alh *b01) all*blh>alh*b01 NOT( Alh*b01>all*blh)

Client's Docket No.: S3U04-0012-TW TT's Docket No:0608-A41110-TW/Final/LukeLee(李宗轩)/ι,Feb,2007 44 1335550 NOT(cl> alh*b01) all*blh>alh*b01 alh *b0 卜all*blh 0 · · -. '.V "--r V π \ ----.3⁄4.·- — .*>«»-*s..- v—*·-· Λ-»'·' ····..,. ---_V · ---"i,ii · :: i*. '·' cl > alh * b01 NOT(all*blh>alh *b01) alh*b01>all*blh 1 cl> alh*b01 all*blh>alh*b01) NOT(alh*b01>all*blh) 1 cl> alh*b01 all*blh>alh*b01 alh*b01&gt ;all*blh 1 --^ .^ · -' · ·'-··· -i·':.- , -·.... ..·.. - •/«i. - ·· , - . -V···· .- -- ·'·. ' /' ..,..- - - . - ...: > -.-, NOT(cl> alh*b01) NOT(all* Blh>alh*b01) NOT(alh*b01>all*blh) 2 cl> alh * bOl NOT(all*blh>alh*b01) NOT(alh*b01>all*blh) 2 Only MAC磐 only MAC body only MAC Crane 3 Table 13

More specifically, as described above, SECS0 1120 receives the operation element Cl_e, the operation element bl_e high index portion (5 bits), the operation element aal1 low index portion (5 bits), and the operation element b0_e low index portion (5 bits) ), and the high-index part (5 bits) of the operation unit al_e. These input faces are combined to a zero exponent detector 1202. If the index portion is zero, the zero value index detector 1202 can be used to output a signal. In addition, the zero value index detector 1202 outputs 5 bits in cl_e to CPA (carry propagate adder) 1204, which is a partial CPA addition, and is also output to the input multiplexer 1210 with an input 埠 "1". The two sets of 5 bits are also transferred to another CPA 1212' and the other two sets of 5 bits are transmitted from the zero value index detector 1202 to the CPA 1214. The CPA 1212 transmits data (6 bits) to the adder (CP A for addition) 1204, the multiply accumulate adder (CPA for MAC) 1218, and the input of the multiplexer 1210 "埠". A multiplier adder (CPA for multiplication) 1214 transmits an output to the adder (CPA for addition) 1206, 1208, a multiply accumulate adder (CPA for MAC) 1222, and an input multiplexer 1210 of the multiplexer 1210. Addition Adder (CPA for addition) 1204 transmits 6-bit data. Input "0" of the multi-mode 1232 and inverter 1250, inverter 1250

Client's Docket No.: S3U04-0012-TW TT's Docket No: 〇608-A41110-TW/Final/LukeLee/1,Feb,2007 1335550 Inverting the signal and transmitting the inverted signal to the input of the multiplexer 1234埠 "1". The CPA f0r addition 1204 also generates a negative signal (<〇) to the encoder 1220, and the encoder 1220 controls the multiplexers 1232, 1234, and 1236 ° CPA for addition 1206 to transfer the input of the 6-bit to the multiplexer 1232. 2" and inverter 1254, the inverter 1254 inverts the signal and transmits the inverted signal to the input 埠 "1" of the multiplexer 1236. The CPA for addition 1206 also generates a negative signal (<〇) to the encoder 1220. The CP A for addition 1208 generates a negative signal (<〇) to the encoder 1220, and the 6-bit signal to the multiplexer 1234. The input "2"' and the input via the inverter 1252 to the multiplexer 1236 are "〇". The multiplexer control input 1210 is coupled to the OR circuit 1230 and the encoder 1220. In addition, the multiplexer 1210 outputs a 6-bit to the AND circuit 1240 and channel 1. CPA for MAC 1216 transfers the 6-bit data to the input of multiplexer 1232 埠 "3". The input of the CPA for MAO 1218 to the multiplexer 1234 is "3". CPA for MAC 1222 transmits the input tan "3" from 6-bit to multiplexer 1236. The CPA for MAC 1224 transmits a 6-bit to the AND circuit 124〇. The multiplexer m6 receives 6 bits from the multiplexer 1210 to input 埠 "1", and receives 6 bits from the MAC index register 1228 to input 埠 "〇". The output of multiplexer 1226 is passed to the input of MAC index register 1228, as well as the output of channel 〇.

The multi-mode 1232 outputs 6 bits to the adder (调整ρA for operand scale) 1242, the CPA for operand scale 1242 also receives the scale_c ' and the scale_c represents the size operands 2x, 4x, and the scale_l represents the c 1

The multiplication result before addition is 2x, 4x, and so on. CPAf〇r^erandscale 1242 outputs the base shift-cl data, which can be used on the alignment shifter. cpA

Client's Docket No.: S3U04-0012-TW TT sDocketNo: 0608-A41110-TW/Final/LukeLee (Li Zongxuan) / 1, Feb, 2007 46 1335550 for operand scale 1244 Receive scaleJ (size of multiplier XJ result) and more The output of the tool 1234, and output 6-bit to base CPA for operand scale 1246 to receive scale_h (size of the multiplier result) and the multiplexer 1236, and output 6-bit to the base shift-hO, It can be used on the base alignment shifter. The "and" gate 124 is received from the cpA f〇rMAC 1224 and the multiplexer 12 to receive the 6-bit output. The "and" gate i24〇 outputs 6 bits to the base shift-maccO output, which can be used for the MAC alignment shifter. Figure 13 is similar to the short index calculation in Figure 11, which illustrates the short index calculation. The short exponential channel 1 is almost symmetrical to the exponential channel 第 of Fig. 12 and has similar power, except for the possibility of increasing the short index value of channel 0 to the final output index. This feature supports variable SIMD coefficients in short operand processing mode. More specifically, as shown in the figure, the input value includes the operation element a〇 high index (5 bits), the different 7G b0 high index (5 bits), the operation element a0 low index (5 bits), and the operation element. The bl high index (5 bits) and the short operand index ch-e. Although the circuit of the short index difference channel 0 (Fig. 12) and the short index calculation channel 1 of the Fig. 13 (in combination with the mixed index channel) are similar, one significant difference is that the multiplexer 1355 appears in the Fig. 3 figure. The multiplexer 1355 receives the index 'from channel 0 (the output of Fig. 12) and is also received from the output of the MAC register 1328. The multiplexer 1355 outputs data to a number of CP A for MACs in Fig. 12. The input data can be processed to provide the index value of channel 1 and the base shift Mantissa shift_macl,

Signals from Mantissa shift-hi, Mantissa shiftjl, and Mantissa shift_ch. Figure 14 shows a short base path providing multiple channels, detailing

Client's Docket No.: S3U04-0012-TW TT S Docket No: 0608-M 1110-TW/Final/LukeLee (Li Zongxuan) / 1, Feb, 2007 1335550 The bottom path of Figure 11. The purpose of this architecture is to provide the base operations of short floating point operators. This architecture can be used to implement the same operation of d=a*b+c+MAC and contains the necessary hardware blocks. The short base data path contains two nearly symmetrical parts: a short base channel 0 and a channel 1 (the left and right halves of Figure 14 respectively). They contain region multipliers 1431, 1433, 1435, 1437, and their outputs are passed to the complement and alignment shifter units (denoted as +/-/>>) CASU 1439a, b, c, d, e, f, g, and h, which are used to align the operand bases according to the selected index value. These units also complement or negatively enter the base value based on the arithmetic symbol (addition or subtraction). These units are combined with an adder 1441a, 1441b, 1445a, 1445b' which implements a carry-save adder tree which adds up the result of the multiplication and the operands c_l〇w and c_high, and adds maccjow and maccjiigh. The MAC short base registers 1430a and 1430b contain accumulated short bottom values. The full adder and the normalizers 1447a, 1447b produce a two-channel short base and short index final value. More specifically, as described above, the multiplier X0L 1431 receives the 13-bit nose number b 1 low base number and the 13-bit nose nose a 1 low base number. The multiplier Χ0Η 1433 receives the 13-bit operand b0 low base and 13-bit operand al algebra. The CASU 1439a receives a 6-bit shift cl ' 13-bit operand al algebra, and a 1-bit sign_c. The CASU 1439b receives the 26-bit output from the multiplier 1431, the 6-bit pre-aligned shift control signal shift 10 (which is the output of the short exponential channel of Fig. 12), and the symbol value Signj. CASU 1439c receives the 26-bit base product from multiplier ΧΟΗ 1433, the 6-bit pre-aligned shift control signal shift h0 from the short exponent channel, and the symbol value sign_h.

Client's Docket No.: S3U04-0012-TW TT's Docket N〇:0608-A41110-TW/Final/LukeLee/1,Feb,2007 48 1335550 The output of CASIJ 1439a, 1439b, 1439c is input to the MAD CSA tree 1441a ( There are related tables showing the CSA hierarchy and extra bits p MAD CSA tree 1441a output 2+26 bit data to MAC CSA tree M45a and multi-work fast 1432. Extra bits are used to avoid the base before alignment and normalization The overflow of the mac loop. The full adder and normalization unit 1447a receives the 5+26 bit base data from the MAC CSA tree 1445a and the index data from the short exponent channel. An additional 5 bits are added to avoid possible The base overflow in the MAC loop. The full adder and normalization unit 1447a converts the base from the CSA format to the general bit encoding format, normalizes the result, and outputs the result. The result contains a 1-bit symbol '5 bits The meta-index, and the 13-bit base (S5el3m), and the result is passed to the output dl. As described above, the multiplier X1H 1435 receives the operand a〇 high base and the operand b0 high base. The multiplier xil 1437 receives the operand A〇 low base and operand The bl high base. The CASU 1439d receives the output from the multiplier χΐΗ 1435 (the 26-bit base product) and the 6-bit shift 11 (the output of the exponential channel) used for the base alignment operation and the 1-bit symbol value signj!. CASU 1439e receives a 26-bit, 6-bit shift hi from multiplier 1437, and a 1-bit sign-hCASU 1439f receives a 13-bit ch_m, a 6-bit shift ch, and a 1-bit sign_c. MAD CSA Tree 1441b is used to receive a pre-aligned 26-bit base from CASU 1439d, a 26-bit base from CASU 1439e, and a 26-bit base of CASU 1439f.

In addition, MAC_h register 1430b receives 5+26 bits of material from MAC CSA tree 1145b. The multiplexer 1432 receives 5+26 bit data from the MAC_h 1430b and receives data from the MAD CSA tree 1441a of channel 0. CASU

Client's Docket No.: S3U04-0012-TW TT's Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 49 1335550 .1439h receives 5+26 bits from multiplexer 1432, and The base shift signal matissa shift__maccl signal is received from the exponential channel. The MAC CSA tree 1445b receives 5+26 bit data from the CASH 1439h and also receives 2+26 bit data from the MAD CSA tree 1441b. The full adder and the regularizer 1447b receive the index data from the exponent channel 1 and also receive the 5+26 bit data from the MAC CSA tree 1445b. The full adder and the normalizer 1447b transmit the result data of s5el3m to the output fairy. Figure 15 illustrates the long index calculation ALU0, similar to the index variation in Figure u. The example of Figure 15 contains four adder levels with appropriate multiplexers, similar to the short exponential channels of Figures 11 and 12. The difference point is to process a set of 10-bit length indices in this channel, while Figures 11 and 12 process a set of 5-bit short indices. The long index processing channel is used to generate all operand shift signals for alignment with the base of the base processing channel and to produce further normalized index results. The 14th indicates the path arrangement function condition of the long exponential channel. 0 CPA 1503 Symbol output condition 1 CPA 1509 symbol output For the C shift amount and the A*B shift amount, the control signal of the output multiplexer N〇T (C>A* B) NOT((A*BorC)>MAC) 0 NOT(C>A*B) (A*BorC)>MAC 1 C>A*B NOT((A*BorC)>MAC) 2 C> A*B (A*BorC)>MAC 3 Adder of the 14th table multiplication (CPA for MUL) 1505 Receive 1 bit. The multiplicands A and B are treated as operands a0 high index and operand a 1 high index The combination of the high index of the operand b0 and the high index of the operand b1. The multiply-addition p (CPA for MAD) 1503 receives the 10-bit exponent of the operand C as a combination of ch e and cl_e, and an exponent result of the 11-bit CPA for MUL 1505. The multiplexer 1511 receives data from the CPA for MUL 1505 and also receives the operand c

Client's Docket No.: S3U04-0012-TW TT'sDocketN〇:0608-A41110-TW/Fina!/LukeLee(李宗轩)/],Feb,2007 50 (〇>af〇rMAC) 1501 combination of heart and cI_e The index of the operand c is received, and the output of the MAC index register (5) 5 is also received. (D) Ruo 1507 from the MAC index register! 5! 5 Receive data also receives data from cpa plus leg 1505. The multiplexer 1513 receives from the register i5i5 and the multi uu. data. The data of the multiplexer 1511 is also transmitted to the output index to ALm.

The output of the processor 1513 is transferred to the temporary storage $1515 and the index output 埠. Cat single 70 1517 transfer data to CPA f0r MAD 15〇3, multiplexer, multi x# 1513>CPAf〇rMACl509^^a 1523

The clock is lost. The CAT unit 1517 combines the two elements into one (h and 】 knot synthesis - one double width block, this example from the negative result flag of the adder (10) and the same flag from the adder 1503). The multiplexer 523 receives the input bee "〇". Fl number 0"' receives the inverted shift amount from CPA f sinking D 15〇3 at input ! "!", and receives the output of cpA f〇rMAc 1507 at input 埠 "2" and "3". The adder for adjusting the operation (cpAfGrseaie) i527 receives the tensor output from the multiplexer 1523, and also receives the system #Jtscale_h, and then outputs the resulting shift amount of A*B. The multiplexer 1521 receives the CPAforMAC1501 output from the inputs 埠 "3" and "2", receives the signal "〇" from the input 埠 "], and receives the output of the CPA for MAD 1503 at the input "0". The multiplexer 1521 outputs 11 bits to the CPA for scale 1529, which also receives c. CpA f〇r scale 1529 outputs the operand C shift amount. Figure 16 illustrates the long index calculation ALU1, similar to the long index juice of Figure u. Although the ALU0 long index calculation in Fig. 15 is similar to the long and private number of ALU1 in Fig. 6, it is worth noting that the multiplexer in Fig. 16 is 16〇2.

Client's Docket No.: S3U04-0012-TW TT'S Docket N0:〇6〇8-A4111〇-TW/Final/LUkeLee(李宗轩)71,Feb,2〇〇7 !335550 " Receive ALU0 index input, accompanying round Into the combination of ch_e* cl_e. In addition, the long index calculation of ALU1 produces an output of an index, a Mac shift amount, an A*B shift amount, and a c shift amount. It is worth noting that the function table of Fig. 16 is identical to the function table of Fig. 15. Figure 17 illustrates the long base data path ALU〇, detailing the data path of Figure u. The purpose of this architecture is to provide the base operations of long floating point operators. This architecture can be used to implement D=A*B+C+MAC bottom-value operations and to include the necessary hard φ body blocks. The long base data path has two nearly symmetrical architectures: the ALUO long base data path in Figure 17 and the alui long bottom data path in Figure 18. The long base data path of ALUO includes four regional multipliers 1731, 1733, 1735, 1737 with pre-shifters pa, 1753; complement and alignment shifters CASU 1739a, b, c, d, e, f, g, denoted by (+/_/〉>), which aligns the operand base according to the selected index value. These units also complement or negatively enter the base value based on the operand (addition or subtraction). These units combine the added states 1741a, 1741b, and 1745 to implement CSA (carry_save adder), which adds the multiplication result to the operand c and adds it to the MAC register. The MAC base register i759 contains the accumuiated long-bottom binary full-charger and the normalizer to produce the shortest base and short-index two channels. More specifically, similar to the above, the multiplier 1731 receives the _ high base and the operand b 〇 low base. The multiplier 1733 receives the operation_equivalent al number and the operand bl low base. The multiplier 1735 receives the operand two low bottom operand aO low base. The multiplier 1739 receives the operand b 〇 ancient base and the element aO high base.冋 Base and operation Multiplier 1731 transmits 26 bits of data to CASH 17

39a ’ CASH

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb,2007 52 1335550

1739a also receives ygn-h and base Shift_h. The CASU 1739b receives the 39-bit data from the multiplier 1735 via the π-bit shifter 1743. CASu n39c receives the 39-bit input data cl_m via the 13-bit shifter 1749. The feature of this architecture is that it consists of a two-stage MAD adder with two parts: a 1/2 MAD adder and a MAD adder. This feature comes from using a region multiplier to process long bases. The 1/2MAD CSA tree 1741a receives data from CASU 1739a, 1739b, and 1739c. The MAD CSA tree 1741b receives 1+4 bits from the 1/2 MAD CSA tree 1741a via the 13-bit shifter 1769, 37-bit data from the CASU 1739d, and 13-bit via the regional multiplier 1735. 39-bit data of the meta-shifter 1753. In addition, the MAD CSA tree 1741b receives 37-bit data from the multiplier 1737 from the CASU 1739f. The MADCSA tree 1741b transmits the ALU0 base data to the ALU1 base output and to the MAC CSA tree 1745. The MCA CSA tree 1745 receives the base shift signal mantissa shift_macc data via the CASU 1739g. The MAC CSA tree 45 transmits 5+40 bits of data to the full adder and the regularizer 1747, which can also calculate the exponent portion for further adjustments during normalization. An extra 1 bit of the base can be used to avoid the base overflow in the MAC loop. The full adder and the normalizer 1747 pass the long format operand data of sl0e26m to the output 埠cat (dh, dl), which combines the two halves of dh and dl to D. Figure 18 illustrates the long base data path, similar to the data path in Figure 17. More specifically, except for a few exceptions, the long base data path of ALU 1 is symmetrical to the long base data path of ALU0. It is worth noting that the multiplexer 1805 receives the base from the ALU0 channel. In addition, the multiplexer 1705 receives Ch m,

Client's Docket No.: S3U04-0012-TW TT’s DocketNo: 〇608-A41110-TW/Final/LukeLee (Li Zongxuan)/], Feb, 2007 1335550 This is the part of the base of the ALU1 operand c.

The number considerations will use two different operands in the presence of the instruction. Two = one of the multiplicands may be in short format and all in long format (see Table 5). This architecture is very similar to the short format 曰m’ except that it can also handle long format indices. Implementation of this architecture has four equal-level exponential adders/subtractors for several appropriate multiplexers controlled by an encoder. The size of the MAC index register is also the long index of the i i bit. More specifically, 'CPA 19〇3 receives data that combines the operating element b's bottom exponent and the extraordinary bl high index. CPA 19〇3 also receives the operand aQ low index. CI>A 19G5 receives the data of the combined operation element bQ high index #σΜ high index, and the a0 high index of the short format. The CPA 1907 receives information combining ch-e and cl-e, and the output of the CPA 1903. CPA }9〇9 receives the output lean from CPA 19〇5 and the input data ch-6 and cl-e. cpA ΐ9 ι receives the output data from CPA 1903' and the output data from CPA 19〇5. The encoder 1920 provides clock signals to cpA 19〇7, 19〇9, and 1911, and k for controlling the number to the multiplexer 1913, and via the OR circuit 1925 to the multi-states 1923, 1935, 1937, and 1939. . The multiplexer 1913 receives data from the CPA 1903 to input "埠", receives ch_e* cl_e to input 」", and receives data from cpA 19〇5 to input 埠2". The CPA 1915 receives the input data ch_e and cl_e and receives the data from the register 1943. The cpa 1917 receives data from the CPA 1913 and the scratchpad 1943. The CPA 1919 receives data from the scratchpad 1943 and the CPA 1905. The CPA 1921 receives data from the scratchpad 1943 and the multiplexer 1913. Multiplexer 1923

Client's Docket No.: S3U04-0012-TW TT's Docket N〇: 0608-A41110- D/W/Final/LukeLee/1, Feb, 2007 54 1335550 Receive data from multiplexer 1913 and scratchpad 1943, and Output result index. The MAC index register 1943 receives data from the multiplexer 1923. The multiplexer 935 receives data from the CPA 1915 to input "3", receive from cPA 19〇9 to input 埠2", receive signal "〇" to input 埠"丨", and receive input from cpA19〇7 to input 埠"0". Similarly, the multiplexer 1937 receives the signal "〇" to the input 埠 "〇", receives the CPA 1907 output to the input 埠h via the inverter 1929, receives the input 埠 "2" from the CPA 1911, and receives the input from the CPA 1917. Enter 埠 "3". The multiplexer 1939 receives the round-out of the cpA 1911 to the input 埠 "〇" via the inverter 1931, the cpA 19 接收 output to the input factory 1" via the inverter 1933, and the reception signal "〇" to the input 埠 "2". Receive CPA 1919 output to the wheel 埠 "3" cCpA 1949 Receive data from the multiplexer 1935, also receive the coefficient scale_c, and then output to the operation element base shift signal claw capture s · C. The CPA 1947 receives the data from the multiplexer 1937 and also receives the coefficient scale-1, and then outputs the half-product matrix shift signal to the edge of the signal. cpA 1945 receives data from multiplexer 丨939 and also receives the coefficient scale-h, and then outputs the half-product matrix shift signal mantissa shift Η 〇 Figure 20 illustrates the mixed index calculation ALU1, similar to the mixed index calculation of the ηth graph. The circuit diagram of the 20th is symmetrical to the circuit of Fig. 19 except for some differences. One significant difference is that the circuit of Figure 2 contains a multiplexer 2〇〇1 that can be used to receive data combining ch_e and ch_l as well as a result index from the ALU〇 index channel. Figure 21 illustrates the mixed base data path ALlJ〇, detailing the data path of Figure u. The mixed base data path is similar to the long base data path of Figure 17. More special, similar to the first! Figure 7, multiplier 213丨 receives short format wheel

Client’s Docket No·: S3U04-0012-TW TT’s Docket N〇: 0608-A411 l〇-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 55 1335550 Enter the data high base and b0 low base. The multiplier 2133 receives the al low base and the low base. The multiplier 2135 receives the high base and the a low base. The multiplier 2137 receives the b0 high base and the a high base. The CASU 2139a receives the data from the multiplier 2131 and also receives the sign bit shift signal mantissa shift A*B high. The CASU 2139b receives the data shifted by the 13-bit shifter 2105 from the multiplier 2133. The base shift signals mantissa shift c and sign_c are also received. The CASU 2139c receives the data shifted by the 13-bit shifter 2109 and receives the mantissa shift c and sign-c. CASU 2139d also receives sign_c and base shift signals mantissa shift C and ch_m. The CASU 2139e receives the data shifted by the 13-bit shifter 2107 from the multiplier 2135, and receives the base shift signals mantissa shift A*B low and sign_l. The CASU 2139f receives data from the multiplier 2137 and also receives the base shift signals mantissa shift A*B high and sign_h. 1/2 MAD CSA Tree 2141a Receives data from CASU 2139a, 2139b, 2139c. The MAD CSA tree 2141b receives data from the 1/2MAD CSA tree 2141a and the CASU 2139d, 2139e, 2139f. The MAD CSA tree transmits the base data to the ALU1 and MAC CSA trees. The 2145〇MAD CSA tree 2145 also receives the data from the scratchpad 2143 from the CASU 2139g. The full adder and regularizer 2147 receives the input index and the MAC CSA tree 2145. The full adder and the regularizer 2147 produce a base to the combined dh and d]. Figure 22 illustrates the mixed base data path ALU1, which is symmetric to the data path of Figure 21. The circuit of Figure 22 is similar to the circuit of the 21st, except for some differences. It is worth noting that the ALU 1 mixed base data path of Fig. 22 includes the multiplexer 2202' which receives the ch_m and the base data from the ALU0 of Fig. 20. The circuit of Fig. 21 outputs the base number to dh and dl.

Client's Docket No.: S3U04-0012-TW TT's Docket No:0608-A41110-TW/Final/LukeLee/1,Feb, 2007 1335550 In order to process dual format floating point data on the same hardware architecture, we can Channels are calculated using separate indices because of their relatively small size. In addition, we can combine short base and long base processing paths on a single hardware architecture because it is difficult to duplicate hardware with both a short base and a long base data path without significant hardware cost. We can usually combine most of the hardware blocks for short bases and long bases, and add some extra logic to provide the correct short mode, long mode, and mixed mode operation. Potential modifications to this design may include (but are not limited to): 1) Select the basic architecture modified by the long exponential data path. 2) Add additional multiplexers to the transport and result paths to select the correct data for each processing mode. 3) Use the special gate logic controlled by the data format to separate all complements and alignment shift cells into two parts. 4) Separate the MACC register to two parts. 5) Separate the mAC CSA and the final adder with the normalizer to the two parts by special blocking logic. In addition, the following figures depict potential modifications to implement a dual mode ALU. Figure 23 illustrates the combined base data path, similar to the data path of Figure 11, and more particularly the 'multiplier 2333 receives the operand al high base and the operand b0 low base. The multiplier 2331 receives the low base of the operand al and the low base of the operand bl. The multiplier 2337 receives the high base of the operand bl and the low base of the operand aO. The multiplier 2335 receives the b0 high base and the a0 high base. CASU 2339a receives the output from multiplier 2333 and receives shift H0 and sign_h0. CASU 2339b receives data from multiplexer 2308, multiplexer 2308 from multiplier 2331

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 57 1335550 and 13-bit shifter 2306 receive data. The CASU 2339c receives data from the multiplexer 2310, and the multiplexer 2310 receives the data from the cl_m and 13-bit shifters 2302. CASU 2339c also receives sign_cl and shift CL. CASU 2339d receives ch_m, shift CH, and sign_ch. The CASU 2339e receives data from the multiplexer 2312 and receives shift L1 and signjl. The multiplexer 2312 receives data from the multiplier 2337 and the 13-bit shifter 2304. The CASU 2339f multiplier 2335 receives the data and also receives shiftHl and Sign_h. The CASU 2339g is separated into high-end and low-end parts by the fence circuit. The CASU 2339g receives the shift ACCH signal and the data from the register 2342a. The CASU 2339g low-end receives the shift ACCL signal and the data from the register 2342b. The register 2342 receives the MAC ' and the data from the [V] CSA tree 0 2345 and the clock signal from the MAC CSA tree 1 2345. The 1/2MAD CSA tree 2341a receives the data from the CASU 2339a, 2339b, and 2339c and transmits the processed data to the 13-bit shifter 2320. The multiplexer 2322 receives the shifted data and the unshifted data, and outputs it to the multiplexer 2316. The multiplexer 2316 also receives the data "〇". The MAD CSA tree 2341b receives the data from the multiplexer 2316 and the CASUs 2339d, 2339e, and 2339f, and outputs the processed data to the MAC CSA tree 1 2345. The MAC CSA Tree 1 2345 also receives data from the low end of the CASU 2339g. For short format, MAC CSA Tree 0 (2345) is separated from MAC CSA Tree 1 by a fence circuit. The MAC CSA Tree 0 (2345) receives data from the high end of the CASU 2339g and the multiplexer 2318. The multiplexer 2318 receives data from the 1/2 MAD CSA tree 2341a and the base data that the ALU0 transmits to the ALU1. MAC CSA Tree 0 2345 transmits data to CPAO 2347a, which is for short format, with a fence

Client's Docket No.: S3U04-0012-TW TT’s Docket No: 0608-A41110-TW/Final/LukeLee/1, Feb, 2007 1335550 The circuit is separated from the CPAl 2347b. CPAl 2347b receives data from the MAC CSA Tree 1 2345. The CPA1 2347b outputs data to the Leading Zero Detector (LZD) L 2330 and LZD1 2332, and the shifter 1 2334b. The CPAO 2347a outputs data to LZDL 2330, LZDO 2328 and Shifter 0 2334a. LZDO 2328 and LZDL 2330 transmit data to shifter 0 2334a. The LZDO 2328 also transmits data to the multiplexer 2325. The LZDL 2330 also transmits data to the shifter 1 2334b and the multiplexers 2325 and 2326°LZD1 2332 also transmits data to the shifter 1 2334b and the multiplexer 2326. Shifter 0 2334a and shifter 1 2334b transmit data to output latch 2340. CPA 2336a receives data from exponential multiplexer 2324, and multiplexer 2324 receives data from short exponential channels 0 and 1, long exponential channels, and mixed exponential channels. CPA 2336a also receives data from multiplexer 2325 and CPA 2336b. Gate barrier 2338 separates CPA 2336 a and CPA 2336b. The CPA 2336a and CPA 2336b transmit data to the output latch 2340. Output latch 2340 outputs s5el3m data to dl, sl0e26m data to (dh, dl), and s5el3m data to dh. In addition, many control signals are used as an example in Table 15 to set the multiplexers L0, CL, L1, and MUX1-5. The output of Table 15 can be switched due to the different data formats processed in the ALU. Mode / Multiplexer L0 CL L1 Muxl Mux2 Mux3 Mux4 Mux 5 ExpMX Long Mode 0 0 0 0 0 0 0 0 0 Mixed Mode 0 0 0 1 0 0 0 0 1 Short Mode 1 1 1 1 1 1 1 1 2 15 Table 24 shows the combined base data path of ALU1, symmetric to the 23rd

Clients Docket No.: S3U04-0012-TW TT's DocketNo: 0608-A41110-TW/Final/LukeLee (Li Zongxuan) / 1, Feb, 2007 59 1335550 Figure ALU0 data path 23 circuit, except for a 'more special The circuit of Figure 24 is similar to the first exception. The difference in Fig. 24 lies in the multiplexer 2302, which receives the result (dh, dl) of the ALU0. The multiplex result base and the operand ch_m. The control of this circuit driver is generally the same as for the consolidated ALU0 table. These multiplexers are available because the base data path is merged in ALUl as described in Table 16. Different data formats processed (4) Special input

Figure 25A illustrates a combined shift 舆 control logic circuit that can be used in the combined base and path shift control signals of Figures 23 and 24, as described above, and many of the changes made therein introduce several special multiplexers Provides a base path from a separate short format, long format, or mixed format index processing channel to merged. More specifically, the multiplexer 255 receives the shift h 〇 and the base shift signal mantissa shift h. The multiplexer 2552 also receives the shifu〇 and the base=bit signal mantissa shift h. The multiplexer 2554 receives the shift d and the base shift man number mantissa shift c. The multiplexer 2556 receives the Shlft MAC 〇 and the base shift signal mantissa shift MAC. The multiplexer 2558 receives the shift ch and the base shift signal mantissashiftc. The multiplexer 2560 receives the shiftU and the base shift signal mantissa shifth. The multiplexer 2562 receives the shifthl and the base shift number mantissashifth. The multiplexer 2564 receives the ShiftMACO and the base shift signal mantissa shift MAC.

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-TW/Final/LukeLee/1, Feb, 2007 1335550 Multi-mode 2566 receives shifthl and output from multiplexer 255〇. The multiplexer 2566 outputs Shift H0. The multiplexer 2568 receives the shlft hl and the output from the multi-mode 2552, and outputs ShiftL〇. The multiplexer 257 receives the spitting edge and the output from the multiplexer 2554, and then rotates the Shift CL. The multiplexer 2572 receives the Shift MAC1 and the output from the multiplexer 2556, and outputs the Shift.

AccH. The multiplexer 2574 receives the shift ch and the output from the multiplexer 2558, and outputs Shift CH. The multiplexer 2576 receives the Shift 11 and the output from the multiplexer 2560 and outputs Shift L1. The multiplexer 2578 receives Shift hi and the output from the multiplexer 2562 and outputs shift H1. The multiplexer 2580 receives the Shift MAC1 and the output from the multiplexer 2564, and outputs shift AccL. Table 17 illustrates the multiplexer control signal for shift control of each channel. What can be seen is that the length of these signals is fairly average, so we can adjust the two lines to control the multiplexers from the instruction decode state machine. Mode Shift H0 Shift L0 Shift CL Shift AccH Shift CH Shift LI Shift HI Shift AccL Short mode 2550:0 2566:1 2552:1 2568:0 2554:1 2570: 〇2556:1 2572:0 2558:1 2574:0 2560 :1 2578:0 2562:1 2578:0 2564:1 2580:0 Mixed mode 2550: X 2566:1 2552: x 2568:1 2554: x 2570: 1 2556: x 2572:1 2558: x 2574:1 2560 : x 2578:1 2562: x 2578:1 2564: x 2580:1 long mode 2550:0 2566:0 2552:0 2568:0 2554:0 2570: 0 2556:0 2572:0 2558:0 2574:0 2560 :0 2578:0 2562:0 2578:0 2564:0 2580:0 Table 17

Figure 25B illustrates a symbol path logic circuit that can be used to convert the symbol signals generated by the split channels to the pay signal of the combined dual format data path of Figure 23. The multiplexer 2582 receives sign h0 and sign h. The multiplexer 2584 receives sign 10 and sing 1. The multiplexer 2586 receives the sign cl and the sign C. The multiplexer 2588 receives the sign ch and the sign C. Multiplexer 2590 receives sing ]1 and

Client's Docket No.: S3U04-0012-TW TT's DocketN〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan yi, Feb, 2007 61 sign 1. Multiplexer 2592 receives sign hi and Sign h. Multiplexer 2594 receives Sign hl and the wheel from the multiplexer, then turn out, gn H0. The multiplexer 2596 receives the sign] and the output from the multiplexer 2584, and then outputs the SignLO. The multiplexer 2598 receives (10) and comes from multiplex The output of the device 2586, and then the Sign CL is rotated. The sign is from ¥ mac. The multiplexer 2599 receives the Sign ch and the output from the multiplexer 2588, and then outputs the Sign CH. The multiplexer 2597 receives the sign 11 and the multiplexer 259. The output of 〇, then output slgn u. The multiplexer 2595 receives the Slgn Μ and the output from the multiplexer 2592, and then outputs the Sign H1. The Sign AccL is from the Sign MAC. In order to generate the multiplexer switching signal, we need to provide each A multiplexer generates a special state machine for switching signals during special commands and when processing different data formats, as shown in Table 18. It can be seen that all multiplexers may be controlled by the same signal of the same state machine. Mode Mode Shift HO Shift L〇Sh Fift CL Shift AccH Shift CH Shift LI Shift HI Shift ArrT Short Mode Short 2550 2566 2550 2566 0 1 Τ ι 2552:1 2568:0 2552:x 2568:1 2554:1 2570: 0 2554: x 2570:1 2556 2572 2556 2572 1 0 X 1 2558 2574 ~2558 2574 1 0 X 1 2560:1 2578:0 1560: x 2578:1 2562:1 2578:0 2562: x 2578:1 2564:1 2580: 0 2564: x 2580.1 Mixed mode Mixed Long Mode Long 2550 2566 0 0 2552:0 2568:0 2554:0 2570:0 2556 2572 0 0 2558 2574 0 0 2560:0 2578:0 2562:0 2578:0 2564:0 2580:0 Table 18 Figure 26 illustrates the complement shift output and output format table, which can be used for the combined base data path of Figures 23 and 24. This table shows how actual output or wheeled data is treated, extended, interpreted, and/or modified into short, long, and mixed modes. The description of the data format is from left to right from top to bottom. All signal names are relative to the merged data path of 23, 24. The use of the input_output data format is to provide appropriate processing of the CSA data in the data path.

Client's Docket No.: S3U04-0012-TW TT's Docket Ν〇:〇6〇8·Α4111 〇-TW/Final/LukeLee(李宗轩)/1, Feb, 2007 , Actually 26-bit HO and HI output of the multiplier The U least significant bits (LSBs) of zero values can be extended. The outputs L0 and L1 of the other two multipliers can be extended by 13 LSBs and can be shifted to the right by 13 bits, with the Most Significant Bits (MSBs) being filled with zero values. The data input CH of the adder can be extended by 24LSB for subsequent use. The second 歹J displays the data format of the short-, long-mode, and mixed-mode complement shift unit input-output data paths. Figure 27A magnifies the partial base addition data path of Figures 23 and 24. As shown in the figure, the data format is converted between several units and multiplexers, and the correct processing of different data formats is provided at the terminal of the barrier MAC CSA tree. More specifically, the circuit of Figure 26 contains 1/2 river gossip 3 into the tree 27413. 1/21^ into 0 08 into the tree

The 2741a receives 37 bits H0, 39 bits l〇, and 37 bits cl. The 1/2MAD CSA tree 2741a outputs 2+26 bits or 1+40 bits to a 13-bit shifter 2752. After the received data is shifted, the 13-bit shifter 2752 transmits the data to the multiplexer 2754' which also receives the data from the wmaD CSA tree 2741a. The multiplexer 2750 receives data from the multiplexer 2754 and also receives signals from other inputs.

The multiplexer 2750 transmits the output data to the MAD CSA tree 2741b, which also receives 37-bit CH, 39-bit L1, and 37-bit H1. MAD CSA

Tree 2741b transmits 5+26 or 5+40 bit MSB to ALU1 base, and 2+40 MSB to multiplexer 2756. The multiplexer 2756 also receives data from the 1/2 MAD CSA 2741a. The multiplexer 2756 outputs data to the MAC CSA tree 0 2745a. The multiplexer 2756 also receives data from the MACC output. The short format fence circuit 2746 separates the MAC CSA tree 0 2475a and the MAC CSA tree 1 2745b to provide a processing of two short format operands in place of a long format operand. MAC

Client's Docket No.; S3U04-0012-TW TT’s DocketN〇: 0608-A41110-TW/Final/LukeLee/1 > Feb, 2007 63 1335550 CSA Tree 1 2745b receives the data from the MAD CSA Tree 2741a and MACC output. The processing format of the short mode, the long mode, and the mixed mode of Fig. 27B can be used in the CSA unit of Fig. 27A. More specifically, Figure 2780a shows the short mode processing of 1/2 MAD CSA. As shown, the data ho contains 26+11 bits and is input to the 1/2 MAD CSA tree 2741a, and L0 contains 26+13 bits 'CL contains 13 + 13 + 11 bits. The 1/2MAD CSA tree 2741a outputs 2+26 valid bits and 13 invalid bits. Figure 2780b illustrates the short mode processing of the MAD CSA 2741b. As shown, H0 contains 26+11 bit inputs to the MAD CSA tree. 2741b’ L0 contains 26+13 bits and CL contains 13 + 13+11 bits. In addition, 1/2MAD contains 0〇+〇〇+〇〇+〇 bits. The MAD CSA tree 2741b outputs 2+26 valid bits and 13 invalid bits. Figure 2780c illustrates the long mode processing format. More specifically, H0 contains 26+11+0 inputs to the 1/2MAD CSA tree 2741a, L0 contains 13+26 bits, and CL contains 13+13+11+0 bits. 1/2MAD CSA Tree 2741a Outputs 2+39 effective bits. Figure 2780d illustrates the long mode processing format. More specifically, H0 contains 26+11+0 inputs to 1/2MAD CSA tree 2741a, L0 contains 13+26 bits, CL contains 13 + 13 + 11+0 bits, and 1/2MAD contains 13+X+ X+26 bits. The MAD CSA tree 2741a outputs 3+39 significant bits. Figure 2780e illustrates the mixed mode processing format. More specifically, H0 contains 26+11+0 bits input to the 1/2MAD CSA tree 2741a, L0 contains 13+26 bits, and CL contains 13 + 13 + 11+0 bits. 1/2MAD CSA Tree 2741a Outputs 2+39 effective bits. Figure 2780f illustrates the mixed mode processing format. More specifically, H0 contains 26+11+0 bits input to 1/2MAD CSA tree 2741a, L0

Clients Docket No.: S3U04-0012-TW TT's Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb,2007 64 1335550 Contains 13+26 bits, CL contains 13 + 13 + 11+ 0 bits, and 1/2MAD CSA contains X+X+39 bits. The MAD CSA tree 2741a outputs 3+39 significant bits. Figure 27C continues to illustrate the processing format of Figure 27B. Figure 2780g illustrates the short mode processing format of the MAC CSA. More specifically, MAC CSA trees 0 and l (2745a, 2745b) receive X+X+26 bits from the MAD and 5X+26 bits from the MACC. The MAC CSA trees 0 and 1 ( 2745a, 2745b ) output 5+26 bits x2 channels. Figure 2780h illustrates the long mode processing format. More specifically, the MAD transmits 14+3X+11MSB to the MACCSA tree 0 2745a. The MAC transmits 12+5X+11MSB to the MAC CSA tree 0 2745a. MAC CSA Tree 0 2745a outputs 12+5X+11MSB, where 5+11 is a valid bit. Figure 2780i contains MAD transport 2+26LSB to MAC CSA tree 1 2745b°MAC transport 0+0+0 ten2+26LSB to MAC CSA tree 1 2745b. MAC CSA Tree 1 2745b outputs 0+0+0+2+26LSB, where 2+26 is a valid bit. It is worth noting that in order to provide short and long base processing modes on the same hardware, we can use gate blocking logic, which can be used to separate some CSAs and CPAs, as shown in Figures 23 and 24, and add some logic. Circuit to regular unit. Figure 28A illustrates the gate arrest circuit in the CPA, which can be used in the MACC of Figures 24 and 27. Using a special multiplexer controlled by mode bits, we can separate the long adder into two short parts. In the long format, we can pass the carry signal from one part of the adder to another part of the adder. In short format, we can only pass zero values. More specifically, the half adder 2875a receives data from the full adder 2876a. The full adder 2876a transmits data to the half adder 2875a and the full adder 2876d. Full adder 2876c receives the data from multiplexer 2877a and full adder 2876d. The multiplexer 2877a receives the signal "〇" and receives the capital from the full adder 2876e.

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-TW/Final/LukeLee (李宗轩)/ι,Feb, 2007 65 ^35550 ,. The fence circuit 2878a separates the multiplexer 2877a and the full adder 28 core. The half adder 2875b «full adder 2876e receives the data β full adder 2876e also transmits data to the full adder 2876f. The full adder 2876 § transmits the data to the full adder 2_. Figure 28B illustrates the fence circuit in CpA, the full adder and the normal unit of the complex. More specifically,; = Jie 2876j receives poor materials, and the full adder 2876j receives data from the multiplexer 287讣. The multiplexer 2878b receives the signal "〇" and the output from the full adder 2·. The shed circuit 2878b separates the multiplexer 2877b and the full adder. The full adder receives data from the half adder 2875c. Figure 29 illustrates the gate block circuit of the complement shift unit, which can be used for the data paths of Figures 22, 23, and 26. The top left corner is a top view of the gate block circuit applied to the mac cSA complement shift unit. More specifically, Fig. 29 details the child 2939a, the gate block circuit 2940, the CASU low 2939b, and the mode multiplex 2914a. The channel mode multiplexer 2914a receives the long operand data and also receives the data from the channel mode multiplex II 2914b. The mode multiplexer provides inputs to function blocks 2901 and 2902a. Function block 2901a computes a predetermined function (as exemplified) and outputs N bits to function block 29〇2a. Function block 29〇2& calculates a predetermined function (as exemplified) and outputs NZ bits to multiplexer n 29〇6&. The multiplexer 2906a also receives the inversion of the signal "〇", the base, and the base M H . The multiplexer 2906a outputs 5+26 bit data to the barrier shifter H 2910a. The cylindrical shifter H 2910a also receives the operand shift data from the mode multiplex cry 29 〇 8a, and the mode multiplexer 2908a receives the data of the long data and the channel 。. The cylindrical shifter H 2910a outputs 5 + 26 bits of data to the CSA tree, and a shiftoutH signal to the shift data multiplexer 2912a. Shift data

Client's Docket No.: S3U04-0012-TW TTs Docket No:0608-A41110-TW/Final/LukeLee/1,Feb,2007 66 I33555〇Multiplexer 2912a also receives the signal "〇" and outputs data to the column Shape shifter B 29l〇b. The gate block circuit 2940 separates the CASU 2939a and 2939b. The mode multiplexer 2914b receives the channel 1 data and the long operand. The mode multi-operation 2914b provides information to the function block MOib. 2902b. The function block 29 〇 lb leaves the predetermined function (as shown) and provides N bits to function block 2902b. Function block 2902b outputs NZ bits to multiplexer 3:1 2906b. The multiplexer 2906b also receives the signal "〇" and the base number M_L and the inverted base m_l. The multiplexer 2906b transmits the data to the cylindrical shifter L 2910b. The cylindrical shifter L 29l〇b also receives the operand shift signal from the mode multiplexer 2908b and outputs the data to the CSA tree. The mode multiplexer 2908b receives long operands and channels! data. Figure 30A illustrates a regular shifter that can be used in the combined base processing data path of Figures 23 and 24. More specifically, CPA 0 3047a receives 5+26 bits or 5+40 bits of data. CPA 0 3047a is separated from CPA 1 3047b by fence circuit 3048. CPA 1 3047b receives 5+26 bit data. The leading zero-batch detector LZDO 3029a receives data from CPA 0 3047a and transmits the data to shifter H 3034a. The leader zero detector LZDL 3030a receives data from CPA 0 3047a and CPA 1 3047b, and outputs data to shifter η 3034a and shifter L 3034b. The lead zero detector LZD1 3032a receives data from CPA 1 3047b and re-outputs the data to shifter L 3034b. The shifter L 3034b also receives data for LZDL 3030a, LZD1 3032a, and CPA1 3074b. The shifter L 3043b outputs ML13. Similarly, shifter H 3034a receives data for LZD0 3028a, LZDL 3030a, and CPAO 3047a. The shifter H 3034a outputs the data MH13. Figure 30B illustrates the fence circuit of Figure 30 in detail. In this example, increase

Client's Docket No,: S3U04-0012-TW TT's Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb,2007 67 1335550 Adding two shift amount control multiplexers to shift data transfer The tool is used to implement the gate block circuit and allow the unit to process two short operands or one long operand. More specifically, the mode multiplexer 3049 receives data from the LZDL 3030b and the LZDO 3028b. The mode multiplexer 3049 outputs the shift amount data to the shifter η 3034c, and the shifter Η 3034c also receives the 2+13 bit data and the output data to the shift data multiplexer 3045. The shifter H 3034c outputs 13 bits to the output latch 3040. The mode multiplexer 3041 receives data from the LZD1 3032b and the LZDL 3030b. The mode multiplexer 3041 transmits the shift amount data to the shifter l 3034d, and the shifter L 3034d also receives the 2+13 bit data. The shifter l 3034d transmits the data to the shift data multiplexer 3045, and the shift data multiplexer 3045 also receives the signal "0" and outputs to the shifter H 3034c. Shifter L 3034d transmits data to output latch 3040. The output latch outputs d (dh, dl), and dh. Figure 31 illustrates a process flow diagram for transferring data to a functionally separated ALU. More specifically, the computing system, as shown in Fig. 31, can determine whether the received data is short format floating point data (block 3132). After the discriminant data is short format floating point data, the computing system can functionally separate the first ALU into a plurality of channels for processing according to an instruction set (block 3134). The computing system can functionally separate a second ALU into a plurality of channels for processing according to the set of instructions (block 313 6). The ten nose system can deliver the processed negative material to a second functionally separated ALU having a plurality of short format data channels (block 3138). In some embodiments, the fish may include an SFU processing data 'where the SFU is used to receive data from the first ALU and the second ALU. The various flowcharts discussed herein illustrate possible implementations of many logic circuit architectures, functionalities, and operations. Therefore, each block can represent a module, a piece

Client's Docket No·: S3U04-0012-TW TT's Docket N〇:0608-A41110-TW/Final/LukeLee/1,Feb,2007 1335550 - Segment, or a piece of code, which may contain one or several Executable instructions to implement particular logic functions, circuits, or other types of logic circuits. It is to be noted that in some embodiments, the functions described in the blocks may not occur in the order illustrated. The present invention is not limited to the size of the data format described, and similar functionality can be achieved, such as processing data formats such as 34/68, 64/128 bits, and the like. Basically, any two related formats can be handled using the above principles. If the long format is not an integer multiple of the short format, some extra circuitry can be created in the data path if some bits are not being used. In addition, some embodiments may have several short format data ® channels and/or one long format data channel. It is specifically emphasized that the above-described embodiments are merely examples of implementing the invention, and are merely presented herein to clarify the principles of the disclosure. Many variations and modifications can be made in the above-described embodiments without substantially departing from the spirit and scope of the invention. All such modifications and variations are encompassed within the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS Many aspects of the disclosure are more readily understood by the following illustration. The components in the illustrations are not necessarily to scale and the emphasis is placed on the principles of the disclosure. In addition, in the figures, the same numerals indicate corresponding parts. The illustrations of the present invention are not intended to limit the invention to the embodiments. On the contrary, the disclosure is intended to cover all alternatives, modifications, and equivalents. Figure 1A is a flow chart illustrating the flow of data processing by a vector processing unit. Fig. 1B is a flow chart showing the flow data processing steps of a scalar processing unit, similar to the steps described in Fig. 1A.

Clients Docket No.: S3U04-0012-TW TT's Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb, 2007 69 1335550 Figure 1C is a stream processing SIMD architecture with complex mathematical functions Software implementation. Figure 1D shows a stream processing SIMD architecture, with the hardware implementation of complex mathematical functions, each ALU uses an individual SFU. Figure 1E shows a stream processing SIMD architecture. With the hardware implementation of complex math functions, all ALUs use a common SFU. Figure 1F shows a stream processing SIMD architecture, with the hardware implementation of complex mathematical functions interleaving a common SFU. Figure 1G is an example of reducing SIMD coefficients, vertices and triangles under a common SIMD architecture. Figure 2A is a flow chart illustrating a scalar processing unit similar to the flow chart of Figure 1, with a SIMD coefficient of four. Fig. 2B is a flow chart illustrating a scalar processing unit similar to the flowchart of Fig. 1 with a SIMD coefficient of one. Figure 2C is a flow diagram illustrating a scalar processing unit similar to the flow chart of Figure 1, with a SIMD coefficient of 8 and data in a short format. Figure 2D is a flow diagram illustrating a scalar processing unit similar to the flow chart of Figure 1, with a SIMD coefficient of 4 and data in a long format. Figure 3 is a logical architecture of an even-pair ALU that can handle dual formats. The processing features of Figures 1 and 2 illustrate the functions of the streaming ALU. Figure 4 is a stream processing unit with an even-pair scalar ALU in the long format processing mode, similar to the architecture of Figure 3, and showing higher order control circuits and memory. Figure 5A is a table showing the arithmetic function of the even-pair scalar ALU.

Client's Docket No.: S3U04-0012-TW TT,s Docket N〇:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb,2007 70 1335550 ' can be used as a basis for the development of numerical processing instruction sets, such as The ALU of Figures 3 and 4. Figure 5B shows an image processing unit architecture with a stream processor as the core of the operation. The stream processor is a resizable architecture and can contain 2 to 16 ALUs and a reduced number of SFUs. Figure 6 is a flow chart, and the logical architecture of a stream processor with four scalar ALUs and one SFU, similar to Figure 3 is the ALU of Figure 4. Figure 7A is a flow chart illustrating the vector ALU processing the normalized vector difference. Figure 7B is a flow chart illustrating the proposed processing routine for a stream of scalar ALUs incorporating a SFU. Figure 7C is a continuation of Figure 7B. Figure 8 shows an ALU module that implements the functions of the ALU in Figure 6. Figure 9 is a stream processor module with four ALUs, similar to the ALUs in Figures 3 and 4. > 10A-10C is a logical architecture and multiplication accumulation (Multiply

The data format of the Accumulate, MACC) unit, such as the multiply accumulate unit of Figure 8. Figure 11 is a multiply-accumulate unit architecture similar to the multiply-accumulate unit of Figure 8. Figure 12 illustrates a short index calculation, similar to the short index calculation in Figure 11. Figure 13 illustrates a short index calculation, combined with a mixed index, similar to

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-TW/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 Howling 550 Figure 11 is a short index calculation. Figure 14 illustrates the base of many channels. New base number path, detailing the πth block Block Le 15 diagram description Long 'number leaf calculation' detailed nth figure index calculation side Figure 16 illustrates another pair

11 graph length index calculation box. , LU long index calculation, detail I path. Figure 17 illustrates a long base data path, detailing the U map (4). Figure 18 illustrates that the other-dual auj filament is similar to the data path of Figure 11. _, '偟, and Figure 19 illustrate a mixed index calculation. ? The number of turns is different, and the Pingtudi 11 figure is mixed. The 20th figure illustrates the mixed index calculation of another dual ALU, similar to the mixed index calculation of Fig. 19. Figure 21 illustrates the mixed base data path detailing the nth material path. J. Fig. 22 illustrates another dual base data path, similar to the data path of Fig. 21. Figure 23 illustrates the combined base data path, which can handle short data formats and long data formats, detailing the data paths that may be implemented in Figure U. Figure 24 illustrates the combined base data path, similar to the data path of the uth. ' Figure 25A illustrates the combined shift and control logic, which can be applied to

Client's Docket No.: S3U04-0012-TW TT’s Docket N〇: 0608-A41110-Ding W/Final/LukeLee (Li Zongxuan)/1, Feb, 2007 72 1335550 23 and the multiply-accumulate unit of Fig. 24. Figure 25B illustrates symbol control logic that can be applied to the multiply-accumulate unit of Figures 23 and 24. Figure 26 is a table illustrating the format of the complementary shift input and output, which can be applied to the multiply-accumulate unit in Figure 11. Fig. 27A illustrates a base addition path which can be applied to the multiply accumulators of Figs. 23 and 24. Figure 27B illustrates the processing format applicable to the Multiply Add (MAD) Carry Save Adder (CSA) tree unit of Figures 23 and 24. Figure 27C is a continuation of the processing format of Figure 27B. Figure 28A illustrates a gate block application of a carry storage adder applied to the multiply accumulators of Figures 23 and 24. Figure 28B illustrates a fence application for the Carry Propagate Adder (CPA) applied to the multiply accumulators of Figures 23 and 24. Figure 29 illustrates a fence application of a complementary shifting unit applied to the multiply accumulators of Figures 23 and 24. Figure 30A illustrates a fence application for a normalized shifter that is applied to the multiply accumulators of Figures 23 and 24. Figure 30B illustrates the gate of Figure 30A in more detail. Figure 31 is a flow chart illustrating the processing that can be used to transfer data to a functionally separate ALU. [Main component symbol description]

Client's Docket No.: S3U04-0012-TW TT'sDocketNo: 0608-A41110-TW/Final/LukeLee (Li Zongxuan) / l, Feb, 2007 73 1335550 1A-B input buffer conventional memory 102 input buffer 4 groups positive Interleaved memory 122 vector ALU 104 scalar ALU 124 SFU 106 2A-B diagram ALUO 204a ALU1 204b ALU2 204c ALU3 204d element shuffler 226 Fig. 3 accumulating register 370 cache memory input data module 372 ALU portPO 376 ALU port PI 378 ALU port P2 380 Input multiplexer 382a 384a 382b 384b Delay register 383 Multiplier 386a 388a 390a 392a 386b 388b 390b 392b Adder 396a 399a 396b 399b Multiply accumulate unit 394a 397a 394b 397b 13-bit shift And enabling device 398a 398b bypass component 395 output CL data component 393 Figure 4 cache memory unit 472 memory output multiplexer 474 input portPO 476 port P1 478 port P2 480 input multiplexer latch 482a 482b delay 386 483 SIMD microcode controller 488 ALU control and addressing component 490 SFU 470 multiplexer 484 Figure 6 Input data 602a-d command decoder control and address signal 602e

Client's Docket No.: S3U04-0012-TW TT's Docket No:0608-A41110-TW/Final/LukeLee(李宗轩)/1,Feb, 2007 1335550 Common Data 602f SFU670 Delay Register 683a-q Output Buffer 604 Worker 672 Figure 8 Dual Format Multiply Accumulate Unit 872 Multiplexer 870 874 Delay Register 883a-e Write Back Register 876 Accumulator 878 Area ALU Staging Table Scratch SRAM 880 State Machine and Address Generator Area Control Unit 882 Figure 9 Multiplexer 970 SFU 980 Figure 11 SECS0 1120 LECS 1040 MESEC1 1130 Final Adder and Normalization Unit 1147 CASU 1139 1144 Multiply-Add Register 1143 MAD CSA Unit 1141 MAC CSA Unit 1145 Multiplier 1 13 1 1 133 1 135 1 137 Figure 12 Adder 1212 1214 1204 1206 1208 1216 1218 1222 1224 1241 1244 1246 Multiplexer 1210 1226 1232 1234 1236 MAC Index Register 1128 Priority Encoder 1220 Zero Index Detection 1202 Inverter 1250 1252 1254 or Circuit 1230 and Circuit 1240 Figure 13 Zero Value Index Detector 1302 MAC Register 1328 Multiplexer 1355

Client's Docket No.: S3U04-0012-TW TT's Docket N〇:0608'A41110-TW/Final/LukeLee(李宗轩)/1,Feb, 2007 75 1335550 Figure 14 Multiplier 1431, 1433, 1435, 1437 CASU 1439a- h multiplexer 1432 carry storage addition tree 1441a 144lb 1445a 1445b MAC short base number register 1430a 1430b full adder and normalizer 1447al447b multiplier 1431 1433 1435 1437 15-16 figure adder 1501 1503 1505 1507 1509 1257 1259 MAC index Register 1515 and circuit 1225 multiplexer 1511 1513 1521 1523 CAT unit 1517 multiplexer 1602 17-18 shifter 1743 1749 1753 1769 multiplier 1731 1733 1735 1737 CASU 1739a-g adder 1741a 1741b 1745 MAC base Register 1747 Full Adder and Normalizer 1747 Multiplexer 1805 19-20 Figure Adder 1903 1905 1907 1909 191 1 1915 1917 1919 1921 1949 1947 1945 Multiplexer 1913 1923 1935 1937 1939 2001 Encoder 192〇 Inverted 1929 1931 1933 MAC index register 1943 or circuit 1925 and circuit 1941

Client's Docket No.: S3U04-0012-TW TT's Docket No:0608-A411I0-TW/FinaI/LukeLee/1, Feb, 2007 76 1335550 21-22 Multiplier 2131 2133 2135 2137 Register 2143 13 Bit shifter 2105 2107 2109 multiplexer 2202 CASU 2139a-g 1/2 MAD CSA tree 2141a MAD CSA tree 2141b 2145 full adder and normalizer 2147 23-24 multiplier 2331 2333 2337 2339 CASU 2339a-g Register 2342a 2342b

Multiplexer 2308 2310 2312 2316 2318 2323 2325 2326 2402 13 bit shifter 2302 2304 2306 2320 MACCSA tree 2345 1/2MAD CSA tree 2341a MAD CSA tree 2341b CPA 2347a 2347b LZD 2328 2330 2332 Output flash 2340 shifter 2334a 2334b CPA 2336a 2336b Gate Block Circuit 2338 Figure 25A-B

Multiplexer 2550 2552 2554 2556 2558 2560 2562 2564 2566 2568 2570 2572 2574 2576 2578 2580 2582 2584 2586 2588 2590 2592 2594 2596 2598 2599 2597 2595 Figure 27A-B Figure 1/2MAD CSA Tree 2741a MAD CSA Tree 2741b MAC CSA Tree 2745a 2745b fence circuit 2746 multiplexer 2750 2754 2756

Client's Docket No.: S3U04-0012-TW TT's Docket No:0608-A41110-TW/Final/LukeLee (Li Zongxuan yi, Feb, 2007 77 1335550 28A-B Figure Half Adder 2875a-c Full Adder 2876a-k Figure 29 CASU 2939a 2939b Gate Block Circuit 2940 Mode Multiplexer 2908a 2908b 2914a 2914b Multiplexer 3:1 2906a 2906b Shift Data Multiplexer 2912a Function Block 2901a 2901b 2902a 2902b Inverter 2904a 2904b Column Shifter 2910a 291 Ob 30A-B CPA 3047a 3047b Fence Circuit 3048 LZD 3028a 3028b 3030a 3030b 3032a 3032b Shifter 3034a-d Mode Multiplexer 3041 3049 Shift Data Multiplexer 3045 Output Latch 3040

Client's Docket No.: S3U04-0012-TW TT’s Docket No:0608-A41110-TW/Final/LukeLee/1,Feb, 2007 78

Claims (1)

1335550 9 Case No. 096104282 September 20, 1999 Revision 10: Patent scope: 1. A stream processor that can process multiple formats. The stream processor includes: a first arithmetic logic unit (Arithmetic Logic Unit) , ALU ), for: processing a plurality of first sets of short format data in response to short format control signals received from an instruction set; Processing a first set of long format data in response to a long format control signal received from the set of instructions; and a second arithmetic logic unit for: processing a plurality of second set of short format data in response to the short received from the set of instructions Formatting a control signal; processing a second set of long format data, receiving processing data from the first arithmetic logic unit in response to the long format control signal received from the instruction set; and processing input data and from the first arithmetic logic unit The processing data is based on a control signal of the instruction set; wherein, when the output data of the first arithmetic logic unit is sent to the second arithmetic logic unit as an operation element of a long format mode, the instruction set is used to control a variable single instruction multiple data stacking mode; wherein an output data of a first channel of the first arithmetic logic unit is sent to a second of the first arithmetic logic unit by an operation element in a short format mode aisle. S3U04-0012-TW/0608-A41110-TW/Finall 79 1335550 2. The stream processor of claim 1 further comprising a special function unit (SFU) for providing the An arithmetic logic unit and an additional arithmetic function of the second arithmetic logic unit. 3. The stream processor of claim 1, wherein the first arithmetic logic unit is a scalar arithmetic logic unit. 4. The stream processor of claim 1, wherein the second arithmetic logic unit is a scalar arithmetic logic unit. 5. The streaming processor of claim 1, wherein the stream processor functionally partitions at least one pair of the arithmetic logic units to facilitate short format and long format in response to receiving the short format data The dual format processing is accompanied by a variable single instruction multiple data (SIMD) coefficient. 6. The stream processor of claim 1, wherein the instruction set includes an instruction to process the variable format data in a plurality of different modes. 7. The stream processor of claim 1, wherein the instruction set comprises at least one of: a normal type instruction, a mixed type instruction, and a cross-type instruction for application in a short format. Data processing and long format data processing. 8. The stream processor of claim 1, wherein the instruction set includes at least one instruction to process at least one of the following modes: a short format operand mode, a long format operand mode, and A mixed format operand mode. S3U04-0012-TW/0608-A41110-TW/Final 1 80 1335550. The stream processor of claim 1, wherein the special function unit is coupled to the first arithmetic logic unit and the second Arithmetic logic unit. 10. A method for processing a plurality of formats, the method comprising: determining whether the received data is short format data; and determining that the received data is short format data, functionally dividing a first arithmetic logic unit into a plurality of channels, according to an instruction set Functionally dividing a second arithmetic logic unit into a plurality of channels, processing according to the instruction set; processing data in the first arithmetic logic unit; and transmitting the processing data to the functionally separated second arithmetic logic unit, a channel with several short format data; S3U04-0012-TW/0608-A41110-TW/Finall 81 1335550 When the output data of the first arithmetic logic unit is sent to the second arithmetic logic unit as an operation element of a long format mode, the instruction set is used to control a variable single-instruction multi-data folding mode; wherein an output data of a first channel of the first arithmetic logic unit is sent to a second of the first arithmetic logic unit by an operation element in a short format mode aisle. 11. The method of claim 10, wherein the first arithmetic logic unit is configured to process short format data and I long format data. 12. The method of claim 10, wherein the second arithmetic logic unit is configured to process short format data and long format data. 13. The method of claim 10, wherein the first arithmetic logic unit operates as a scalar arithmetic logic unit. 14. The φ method of claim 10, wherein the second arithmetic logic unit operates as a scalar arithmetic logic unit and has at least one of the following: a plurality of short format data. Channel and channel for a long format data. 15. The method of claim 10, wherein the method of processing a plurality of format data further comprises processing data in a special function unit, wherein the special function unit is from the first arithmetic logic unit and the second arithmetic logic unit Receive data. 16. The method of claim 10, wherein the instruction set includes an instruction to process a plurality of different modes S3U04-0012-TW/0608-A41110-TW/Final 1 82 1335550 Variable format data. 17. The method of claim 10, wherein the instruction set comprises at least one of the following: a normal type instruction, a mixed type instruction, and a cross type instruction. 18. A streaming processor module capable of processing a plurality of format data, the streaming processor module comprising: a first arithmetic logic unit for receiving first input data and control data, the control data for indicating a format of the first input data, and the first arithmetic logic unit further processes the short format input data and the long format input data according to the control data; a second arithmetic logic unit for receiving the first arithmetic logic unit Controlling the data, the second arithmetic logic unit is further configured to process the second input data, and the second input data is related to the first input data, and the second arithmetic logic unit further processes the short format input data according to the control data. And a long format input data; a third arithmetic logic unit for receiving the control data from the second arithmetic logic unit, the third arithmetic logic unit further configured to receive the third input data, and the third input data and the The first input data is related to the second input data, and the third arithmetic logic unit is further based on the control poor Processing the short format input data and the long format input data, and a fourth arithmetic logic unit for receiving the control data from the third arithmetic logic unit, the fourth arithmetic logic unit further configured to receive the fourth input data, And the fourth input data is related to the first, second, and third input materials, and the fourth arithmetic logic unit processes the S3U04-0012-TW/0608-A41110-TW/Final 1 83 1335550 according to the control data. a format tribute and a long format tribute, wherein when the output data of the first arithmetic logic unit is sent to the second arithmetic logic unit as an operation element of a long format mode, the instruction set is used to control the variable single The instruction multi-data folding mode; wherein the output data of a first channel of the first arithmetic logic unit is sent to a second channel of the first arithmetic logic unit by an operation element in a short format mode. 19. The streaming processor module of claim 18, wherein the first arithmetic logic unit, the second arithmetic logic unit, and the third arithmetic logic unit are configured to receive a special function The operation data of the unit, the operation data is used to indicate the execution operation of the received input data. 20. The stream processor module of claim 18, wherein the first arithmetic logic unit is further configured to receive a common data, the first arithmetic logic unit transmitting the common data to the second arithmetic logic unit And the second arithmetic logic unit transmits the common data to the third arithmetic logic unit, and the third arithmetic logic unit transmits the common data to the fourth arithmetic logic unit. 21. The stream processor module of claim 18, wherein at least one of the following is for processing short format data and long format data: the first arithmetic logic unit, the second arithmetic logic unit, The third arithmetic logic unit, and the fourth arithmetic logic unit. S3U04-0012-TW/0608-A41110-TW/Final 1 84