1335131 » 九、發明說明： 【發明所屬之技術領域】 本發明提供一種晶片内建RC時間常數校正方法與裝置，尤 指一種具有RC時間常數精準自我校正方法以增進多相濾波器之 鏡像訊號(image)濾除(rejection)功能的積體電路調諧器晶片。 【先前技術】 癱 通常積體電路調諧器·晶片係使用多相濾波器處理來自.正交混 頻器的同相/正交訊號(I/Q signals)與射頻訊號之混頻訊號，以形成 一鏡像訊號濾除混頻器’並輸出所要之訊號。而其鏡像訊號濾除 功能的優劣係決定於對RC時間常數的精準調控。一般而言，積體 電路製程電阻的阻值誤差大約是+/-20%，而電容的容值誤差大約 是+M0% ’所以對RC時間常數的精準調控並非易事。因此多相濾 波器就特別需要一精準的RC時間常數校正方法以提高其鏡像訊 翁號渡除之功能。 在一案號為5,245,64ό的美國專利之先前技術中，揭露一種使 用一參考時脈以計數一由RC時鈞常數所決定的脈波。但由於其所 使用的參考時脈有頻率上的限制，而計數器的計數速度也同樣受 限，所以其整體效能並不特別優越。總之，提供一有彈性的及精 準的RC時間常數校正方法與裝置才是提高積體電路調譜器晶片 之鏡像訊號濾除功能的治本之道。 【發明内容】 電&本㈣提供一種使用晶#内建Rc時間常數校正方法的積艘 路；調雜曰。該積體電路_器包含一接收射頻訊號的接收電 一^正交混頻H ’給於該接收電路的輸出端；—多域波器； 地緩振盪器；以及一數位校正模組。 鲁 該多相渡波器包含一第-輸入端與-第二輸入端，該第一輸 端係雛於該正交混頻^的-輸出端，該數位校正歡包含一 2 士认及閘，其—第—輸人端耗接於娜緩振盪器的—輸出端；一 。十數器’其-輸入端耗接於該2輸入及閘的一輸出端；一有限狀 態機，包含-輸人端織於該計數器的—輸出端，—第一輸出端 耗接於該_振堡㈣一輸人端與該多相遽波器的第二輸入端， 以及一第二輸出端耦接於該2輸入及閘的一第妥輸入端。 ♦ . · φ 本發明另提供-種用於積體電路調譜器之多相滤波器的晶片 内建RC時間常數校正方法，該多相濾波器的鏡像訊號濾除功能係 由一晶片内建RC時間常數所控制《^亥方法包含由弛緩振盪器產生 一時脈，該時脈之週期係正比於該晶片内建Rc時間常數；該時脈 輸入數位校正模組中的計數器，由數位校正模組中的有限狀態機 發出一致此況號以設定一預定時間區秩，計數該時脈之週期以產 生一計數值；將該計數值與一期望值於有限狀態機内作比較以產 生一比較結果；以及根據該比較結果由數位校正模組更新該晶片 内建RC時間常數(rc_c〇de)至多相濾波器與弛緩振盪器。 1335131 【實施方式】 如上所述’案號為5,245,646的美國專利之先前技術中，揭露 • 一種使用一參考時脈以計數一由RC時間常數所決定的脈波。而本 發明技術則是產生一由RC時間常數所決定的時脈，並用以在一預 定時間區段内計數該時脈的週期以產生一週期計數值，再利用該 週期計數值與一期望值執行RC時間常數之校正，該預定時間區段 鲁越長則所校正的RC時間常數越精準’由於該預定時間區段並沒有 限制’所以RC時間常數就可達到任何所要求的精準度，因此可以 顯著提高積體電路調諧器晶片之鏡像訊號濾除功能。 请參閱第1圖，第1圖係顯示根據本發明具有晶片内建Rc 時間常數校正功能的積體電路調諧器1〇〇之電路示意圖。積體電 珞調諧器100包含一接收電路丨05，用以接收一射頻訊號；一正交 鲁混頻器110,耦合至接收·電路·1〇5的輸出·；以及一多相濾波器 rccr—combiner 120 ’耦合至正交混頻器11〇的輸出，用以處理來自 正交混頻器110的同相/正交訊號(1/(3 signals)與射頻訊號之混頻訊 號，以形成一鏡像訊號濾除混頻器，並輸出所要之訊號。多相濾 波器rccr_combiner 120包含複數個電阻與複數個電容，為了避免 輸出景d象失真，多相濾、波器rccr_combiner 120另接收一校正碼 rc一code(晶片内建rC時間常數)以調整其複數個電阻與複數個電 容的電路操作，用以執行假像訊號濾除之校正功能，因多相濾波 器rccr—combiner 120的操作原理係為習知技藝，所以不再贅述。 I335131 積艘電路卿器另包含有—⑽振盤器⑽與一數位校 正模組130。數位校正模組13〇包含一 2輸入及閉㈣、一計數器 160、以及-有限狀態機17Q ’肋更新與輸出校正碼&e〇de至 多相滤波器rccr—combinerl2〇與他緩振盈器14〇。他緩振堡器i4〇 而更新其縣鮮，並輸出具有更 新頻率之時脈OLK至触校正触13()，織正碼⑺-⑶如係可 不斷地被變更以校正相冑元件之操作。2輸人及閘】Μ具有一第一 輸入端第一輸入端、與一輸出端，第一輸入端係用以接收弛 緩振盪器M0輸出之時脈·CLK.，苐二輸入端係用以接收有限狀態 機Π0輸出之致能訊號EN，其輪出端係搞合至計數器16〇。 弛緩振S器140所輸出的_ CLK之週期係正比於晶片内建 RC時間常數校正碼rc—code。計數器16〇在預定的時間區段中由 鲁有限狀態機170輸出之敢能訊號伽㈣其啟動與停止計數，而計1335131 » IX. Description of the Invention: [Technical Field] The present invention provides a method and apparatus for correcting RC time constants in a chip, and more particularly to an accurate self-correction method with an RC time constant to enhance the image signal of the polyphase filter ( Image) Integrated circuit tuner chip for the rejection function. [Prior Art] 瘫 Generally, an integrated circuit tuner and a chip system use a polyphase filter to process a mixed signal of an in-phase/orthogonal signal (I/Q signals) and a radio frequency signal from a quadrature mixer to form a The image signal filters out the mixer' and outputs the desired signal. The quality of the image signal filtering function is determined by the precise control of the RC time constant. In general, the resistance error of the integrated circuit process resistor is about +/- 20%, and the capacitance error of the capacitor is about +M0% ', so precise regulation of the RC time constant is not easy. Therefore, the multiphase filter requires a precise RC time constant correction method to improve the function of the mirror signal. In the prior art of U.S. Patent No. 5,245,64, the disclosure of the utility of the utility of the present disclosure is to use a reference clock to count a pulse wave determined by the RC 钧 constant. However, since the reference clock used by it has a frequency limitation and the counting speed of the counter is also limited, its overall performance is not particularly advantageous. In summary, providing a flexible and accurate RC time constant correction method and device is the key to improving the image signal filtering function of the integrated circuit spectrometer chip. SUMMARY OF THE INVENTION Electric & (4) provides a product road using the built-in Rc time constant correction method of crystal #; The integrated circuit _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The multi-phase waver includes a first input terminal and a second input terminal, and the first input end is coupled to the output terminal of the orthogonal mixing circuit, and the digital correction filter includes a 2 s. The first-input terminal is connected to the output of the oscillator; The tensor device's input terminal is connected to an output terminal of the 2 input and the gate; a finite state machine includes an input terminal to which the input end is woven, and the first output terminal is consumed by the _ The second input end of the multi-phase chopper and the second output end are connected to a second input end of the 2-input and the gate. The invention further provides a built-in RC time constant correction method for a polyphase filter of an integrated circuit spectrometer, wherein the image signal filtering function of the polyphase filter is built in a chip. Controlled by the RC time constant, the method includes a clock generated by the relaxation oscillator, and the period of the clock is proportional to the built-in Rc time constant of the chip; the clock is input to the counter in the digital correction module by the digital calibration mode The finite state machine in the group issues the same status number to set a predetermined time zone rank, counts the period of the clock to generate a count value; compares the count value with an expected value in a finite state machine to generate a comparison result; And updating the on-chip RC time constant (rc_c〇de) to the polyphase filter and the relaxation oscillator by the digital correction module according to the comparison result. 1335131 [Embodiment] In the prior art of U.S. Patent No. 5,245,646, the disclosure of which is incorporated herein by reference. The technique of the present invention generates a clock determined by the RC time constant, and counts the period of the clock for a predetermined period of time to generate a period count value, and then performs the period count value and an expected value. Correction of the RC time constant, the longer the predetermined time period is, the more accurate the corrected RC time constant 'because the predetermined time period is not limited', so the RC time constant can achieve any required accuracy, so Significantly improve the image signal filtering function of the integrated circuit tuner chip. Please refer to FIG. 1. FIG. 1 is a circuit diagram showing an integrated circuit tuner 1B having a built-in Rc time constant correction function according to the present invention. The integrated power tuner 100 includes a receiving circuit 丨05 for receiving an RF signal, a quadrature lumixer 110 coupled to the output of the receiving circuit 1〇5, and a polyphase filter rccr The -combiner 120' is coupled to the output of the quadrature mixer 11A for processing the in-phase/orthogonal signals (1/signal signals) from the quadrature mixer 110 to form a mixed signal. The image signal filters out the mixer and outputs the desired signal. The polyphase filter rccr_combiner 120 includes a plurality of resistors and a plurality of capacitors. In order to avoid distortion of the output scene, the multiphase filter and the rccr_combiner 120 receive a correction code. Rc-code (chip built-in rC time constant) to adjust the circuit operation of its multiple resistors and complex capacitors to perform the correction function of the dummy signal filtering, because the operating principle of the polyphase filter rccr-combiner 120 For the conventional skill, it will not be described again. The I335131 integrated circuit module further includes a (10) vibrator (10) and a digital correction module 130. The digital correction module 13A includes a 2-input and a closed (four), a counter 160 And - have State machine 17Q 'rib update and output correction code & e〇de to polyphase filter rccr-combinerl2〇 and his slow vibrating device 14〇. He slows up the i4〇 and updates its county fresh, and outputs with updated frequency The clock OLK to touch correction touch 13 (), the weave code (7) - (3) can be continuously changed to correct the operation of the phase element. 2 input and gate Μ has a first input first input And an output terminal, the first input terminal is configured to receive the clock CLK. of the output of the flaccid oscillator M0, and the second input terminal is configured to receive the enable signal EN of the finite state machine Π0 output, and the turn-off terminal system The period of _ CLK outputted by the relaxation oscillator 140 is proportional to the on-chip RC time constant correction code rc_code. The counter 16 由 is in the predetermined time zone by the finite state machine 170 The output of the dare can signal gamma (four) its start and stop counting, while counting
數器16〇在該預定時間區段中計數他緩振魅M0輸出時脈CLK 之週期以產生週期計數值NP，有限狀態機17〇利用二分搜尋逼近 校正法根據計數器160輸出之週期計數值仰更新校正碼 rc—code，並提做狀校正碼錄緩振邮⑽與多相渡 波器 rccr_combiner 120。 閱弟 一 …，…，、似娜个节、明一較佳實施例的 續逼近搜尋校正法40G之流程圖。先將校正喝re」她所有位元 ^定為“ο”，數位校正模組13〇之有限狀態機】7〇輸出致能訊 以控制計數器⑽在—預定_區段中計數賊振盪器140 1時脈CLK之週期以差生週期計數值抑。其後，有限狀態機 70將週期&十數值卿與一期望值作比較，如果週期計數值仰大 於該期望值，職示崎減器14G的振細率太高，此時校正 碼rc—c〇de之一位元資料會被更新以增加RC時間常數。反之，如 果週期計紐NP小於該賊值，職雜緩録器14()的振盈頻 率太低，此時校正碼rc_c〇de之一位元資料會被更新以減少rc時 間常數。上述之比較與更新程序係不斷地執行，而校正碼^^⑺如 之每一位元資料即從最高有效位元到最低有效位元依序被更新。 連續逼近搜尋校正法400包含下列步驟： 步驟200 :開始； 步驟210 :將校正碼rc—code所有位元值的初值均設定為“〇，，，假 設校正碼rc_code為一 η位元二進碼，其位元索引值範 ·. · · . 圍設為從1至η’而η代表最高有效位元之索引值，1 代表最低有效位元之索引值，設一變數i，並將變數i 的起始值設定為η; 步驟220:有限狀態機170送出一啟動計數之致能訊號ΕΝ以啟動 計數器160的計數狀態，經一預定時間區段後，有限 狀態機170送出一停止計數之致能訊號ΕΝ以停止計 數器160的計k狀態; ' 步驟230:有限狀態機170將計數器160所產生之週期計數值Np 1335131 與-期望值比較’如果週期計數值灿大於該期望值則 執行步驟240，否則執行步驟250. -夕驟240:有限狀態機170將校正碼扣—⑶如中索引值為i之有效 彳ϋτο值設以提冑校正碼rc_eGde之值以降 低弛緩振蘯器140之振盪頻率，執行步驟26Q; 少驟250 .有限狀態機170將校正碼re—c〇(je中索引值為丨之有效 位元值設定為“〇’’’用以降低校正碼re_c〇de之值以提 ’ 尚他緩振盪器140之振盡頻率，執行步驟26〇; 步驟260 :有限狀態機170判斷變數丨之值是否大於丨，如果變 數1之值大於1則執行步輝270，否則執行步驟280; 步驟270 :將校正碼rc一c〇de +索引值為w之有效位元值設定為 “Γ，； 步驟280 :將變數i之值減1; 责驟290 :如果變數i之值不等於〇，就表示校正碼rc_c〇de尚未 .· ► 完成校正，跳回至步驟220，否則執行步驟300 ; 步驟300 :結束。 * · . * 上述連續逼近搜尋校正法4〇〇，在步驟21〇中，將校正碼 rc一code所有位元值的初值均設定為“〇”，係可變更為將校正碼 rc一code的最高有效位元設定為“丨”，而其餘非最高有效位元之至 少一個位元均設定為“〇，，，也就是說，先將校正碼 re code的初值 設定為-㈣值，雜開錢行連續逼近搜尋程序。總之，在不 影響校正碼rc—code的校正結果情況下，類似連續逼近法之均等變 12 1335131 化’皆屬本發明之涵蓋範圍。 請參閱第3圖，第3圖係顯示第1圖之弛緩振盪器140的内部 電路示意圖。弛緩振盪器14〇包含一第一電容區ci，包含有受校 正碼rc—code控制之晶片内建電容電阻組;一第二電容區C2，包含 • . · 有受校正碼rc_C0(le控制之另一晶片内建電容電阻組;一第一比較 器310;—第二比較器320;一第一 2輸入反及閘33〇;以及一第二2 輸入反及閘340。 第一電容區C1與第二電容區C2均包含複數個電容與複數個 電阻’用以模擬多相滤波器rccr_combiner 120所包含之複數個電 * . . , 容與複數個電阻之電路功能’使得弛緩振盪器14〇能有效地重現 目前校正碼rc_code作用在多相濾波器 rccr combiner 120 上的效 果0 第一電容區C1係耦合於節點N1與接地之間，其具有一輸入 端以接收校正碼rc一code。節點N1係耗合至一電盧源VI、第一比 較器310之負輸入端、以及一第一開關swi ,具有一控制輸入端 耦接於節點N4’也就是說第一開關SW1係由節點N4之節點電壓 VN4所控制，當節點電壓\^4為高準位時，第一開關係處於閉合 狀態，也就是將第一電容區C1設定為放電狀態，當節點電壓VN4 為低準位時，第一開關係處於開路狀態，也就是將第一電容區C1 設定為充電狀態，此時，第一電容區Cl利用校正碼rc c〇de控制 1335131 其晶片内建電容電阻組的電路操作以控制充電狀態之rc充電常 數0 第二電容區C2係耦合於節點N2與接地之間，其具有一輸入 端以接收校正碼rc_cocje，節點N2係耦合至一電壓源V2、第二比 較器320之負輸入端、以及一第二開關sw?，具有一控制輸入端 耦接於節點N5，也就是說第二開關SW2係由節點N5之節點電壓 鲁VN5所控制’當節點電壓彻為高準位時，第二開關係處於閉合 狀態，也就是將第二電容區C2設定為放電狀態，當節點電壓 為低準位時，第二開關係處於開路狀態，也就是將第二電容區C2 设定為充電狀態，此時，第二電容區C2利用校正碼江一⑶也控制 其晶片内建電容電阻組的電路操作以控制充電狀態之Rc充電常 數。 • 第一比較器310與第二比較器320的正輸入端均接收一能隙 (bamigap)參考電壓Vref，第一比較器31〇的輸出端係耦合到第一 2 輸入反及閘330的第一輸入端，第二比較器32〇的輸出端係耦合 到第二2輸入反及閘340的第一輸入端，第一 2輸入反及閘33〇 的第二輸入端與第二2輸入反及閘34〇的輸出端耦合於節點N5， 第一 2輸入反及閘340的第二輸入端與第一 2輸入反及閘33〇的 輪出端耦合於節點N4，而弛緩振盪器14〇的輪出時脈CLK即輸 出於節點N4。 1335131 • 第一 2輸入反及閘330與第二2輸入反及閘340係連接成一 RS閂鑌器(RS-Latch)，苐二2輸入反及間340的第一輸入端即為 Set輸入端，第一 2輸入反及閘330的第一輸入端即為Reset輸入 端，當Set輸入端與Reset輸入端均接收高準位訊號時，RS閂鎖 器(RS-Latch)係處於閂鎖狀態，也就是保持輸出狀態之記憶狀態， 特別注意此由二個2輸入反及閘所連接成的rs閂鎖器的閂鎖狀態 (記憶狀態)係不同於由二個NOR閘所連接成的rs閃鎖器，當set •輸入端接收高準位訊號而Reset輸入端接收低準位訊號時，第一 2 輸入反及閘330的輸出節點電壓VN4為高準位，而第二2輸入反 及閘340的輸出節點電壓VN5為低準位，當Set輸入端接收低準 • · 位訊號而Reset輸入端接收高準位訊號時，第一 2輸入反及閘33〇 的輸出節點電壓VN4為低準位，而第二2輸入反及閘340的輸出 節點電壓VN5為高準位。 φ 假没Set輸入端接收高準位訊號而Reset輸入端接收低準位訊 號，則如上述’節點電壓VN4為高準位而節點電壓預5為低準 位，即弛緩振盪器140的輸出時脈CLK處於高準位狀態，所以第 一開關被設定為閉合狀態而第各開關硃設定為開路狀態，也就是 將第一電容區C1設定為放電狀態，而將第二電容區C2設定為充 電狀態，此時因第一比較器31〇的負輸入端(節點N1)係被短路至 接地也就疋第一比較器31Q的負輸入端電堡小於正輸入端電壓 (能隙參考電壓Vref)，因此第一比較器31〇的輸出端(Reset輸入端） 訊號由低準位轉換為高準位，此時，Set輸入端與如奶輸入端均 5 15 1335131 接收高準位訊號’因此RS閂鎖器係處於閂鎖狀態，其輸出狀態不 變，也就是他緩振盪器140的輸出時脈clk保持於高準位狀態， 當節點電壓VN2從零電位充電到大於能隙參考電壓Vref時’第二 比較器320的輸出端(Set輸入端)訊號由高準位轉換為低準位，此 時，Set輸入端接收低準位訊號而Reset輸入端接收高準位訊號， 因此第一 2輸入反及閘330的輸出節點電壓VN4轉換為低準位， 而第二2輸入反及閘340的輸出節點電壓VN5轉換為高準位，也 *就是弛緩振盪器140的輸出時脈.CLK轉換為低準位狀態。 其後，第一開關被設定為開路狀態而第二開關被設定為閉合狀 態，也就是將第一電容區..C1設定為充電狀態，而將第二電容區 C2設定為放電狀態，此時因第二比較器32〇的負輸入端(節點N2) 係被短路至接地’也就是第二比較器320的負輸入端電壓小於正 輸入端電壓(能隙參考電壓Vrei)，因此第二比較器320的輸出端 魯（Set輸入端號由低準位轉換為局準位，此時，set輸入端與 輸入端均接收高準位訊號，因此RS閂鎖器係處於閂鎖狀態，其輸 出狀態不變’也就是他緩振盪器140的輸出時脈CLK保持於低準 位狀態，當節點電壓VN1從零電位充電到大於能隙參考電壓Vref 時，第一比較器310的輸出端(Reset輸入端)訊號由高準位轉換為 低準位’此時，Set輸入端接收高準位訊號而Reset輸入端接收低 準位訊號’因此第一 2輸入反及閘330的輪出節點電壓W4轉換 為咼準位，而第二2輸入反及閘340的輸出節點電壓轉換為 低準位’也就是弛緩振盈器140的輸出時脈CLK轉換為高準 1335131 - 位狀態。 ♦ · . 如上所述，第一電容區ci與第二電容區C2的充電狀態與放電 •狀態，不斷地交互變化而產生弛緩振盈器14〇的輸出振逵時脈 CLK ’而由於第一電容區ci與第二電容區C2在充電狀態時之時 間常數係正比於晶片内建RC時間常數校正碼^〇如，所以他緩 振盪器140輸出時脈CLK的振盪週期亦正比於晶片内建RC時間 籲常數校正碼rc__code。 由上述可知，本發明技術突破先前技術有關Rc時間常數校正 的限制’本發明技術利用—弛諼振盤器產生一由RC時間常數所決 定的時脈’並用以在-預定時間區段内計數該時脈的週期以產生 -週期計數值’再比較該週期計數值與—期望值以執行Rc時間常 數校正’該預定時間區段越長則校正碼rc—c〇de的有效位元數越 鲁多，而所校正的RC時間常數也就越精準。一般而言，校正誤差有 -種主要來源’其_為雜緩缝^内之比較賊造成的延遲誤 差，其二為啟動與停止計數時之同步計數誤差。本發明架構先進 的地方在這二種誤差均可藉由降低該他緩振盈器之振盈頻率與延 長該預糾_段而減相容許誤差以p也就是說較長的校 正時間可以提高校正精準度。所以Rc時間常數的校正就可達 何所要求的精準度，因此可以顯著提高積體電路調諧器晶片之梦 像訊號瀘哈幼能。 兄The timer 16 计数 counts the period of the damper M0 output clock CLK in the predetermined time period to generate the cycle count value NP, and the finite state machine 17 〇 uses the binary search approximation correction method to calculate the cycle count value according to the counter 160 output. The correction code rc_code is updated, and the correction code recording buffer (10) and the multiphase waver rccr_combiner 120 are provided. Read the flowchart of the continuation search correction method 40G of the preferred embodiment of the preferred embodiment of the present invention. First, the correction drink re" all her bits ^ is set to "ο", the digital correction module 13 〇 finite state machine] 7 〇 output enable signal to control the counter (10) in the - predetermined _ section count thief oscillator 140 The period of 1 clock CLK is suppressed by the differential period count value. Thereafter, the finite state machine 70 compares the period & ten value qing with an expected value. If the period count value is greater than the expected value, the gradation rate of the sag reducer 14G is too high, and the correction code rc_c 此时One of the de-bit data will be updated to increase the RC time constant. On the other hand, if the period NP is less than the thief value, the vibration frequency of the job buffer 14() is too low, and one bit of the correction code rc_c〇de is updated to reduce the rc time constant. The above comparison and update procedure is continuously performed, and the correction code ^^(7) is updated sequentially from the most significant bit to the least significant bit, as each bit data. The continuous approximation search correction method 400 includes the following steps: Step 200: Start; Step 210: Set the initial value of all the bit values of the correction code rc_code to "〇,,, assuming that the correction code rc_code is an n-bit binary Code, whose bit index value van · · · · is set from 1 to η ' and η represents the index value of the most significant bit, 1 represents the index value of the least significant bit, sets a variable i, and sets the variable The start value of i is set to η; Step 220: The finite state machine 170 sends a start signal enable signal ΕΝ to start the count state of the counter 160. After a predetermined time period, the finite state machine 170 sends a stop count. The enable signal 停止 is to stop the count k state of the counter 160; 'Step 230: The finite state machine 170 compares the cycle count value Np 1335131 generated by the counter 160 with the expected value'. If the cycle count value is greater than the expected value, step 240 is performed. Otherwise, step 250 is performed. - Step 240: The finite state machine 170 sets the correction code - (3) if the value of the effective value i ο of the index value i is set to the value of the correction code rc_eGde to reduce the oscillation frequency of the relaxation oscillator 140 , Step 26Q; less than 250. The finite state machine 170 sets the correction code re_c〇 (the index value of the index in je is set to "〇'" to lower the value of the correction code re_c〇de. Step 260: The finite state machine 170 determines whether the value of the variable 丨 is greater than 丨, and if the value of the variable 1 is greater than 1, executes the step 270, otherwise step 280 is performed. Step 270: Set the effective bit value of the correction code rc_c〇de + index value w to "Γ,; Step 280: Decrement the value of the variable i by 1; Responsible to step 290: If the value of the variable i is not equal to 〇, it means that the correction code rc_c〇de has not yet been completed.·· ►Complete the correction, jump back to step 220, otherwise go to step 300; Step 300: End. * · . * The above continuous approximation search correction method 4〇〇, in step 21〇 In the middle, the initial value of all the bit values of the correction code rc-code is set to "〇", and the most significant bit of the correction code rc-code is set to "丨", and the remaining non-most significant bits are set. At least one bit is set to "〇,,, that is, the correction code is re cod first. The initial value of e is set to a value of -(iv), and the hybrid money line continuously approaches the search program. In short, without affecting the correction result of the correction code rc-code, the equalization of the continuous approximation method is 12 1335131. Please refer to Fig. 3. Fig. 3 is a schematic diagram showing the internal circuit of the relaxation oscillator 140 of Fig. 1. The relaxation oscillator 14A includes a first capacitor region ci, which is controlled by a corrected code rc-code. The chip has a built-in capacitor resistor group; a second capacitor region C2, including: • another chip built-in capacitor resistor group controlled by the correction code rc_C0 (le; a first comparator 310; and a second comparator 320) A first 2 input reverse gate 33 〇; and a second 2 input reverse gate 340. The first capacitor region C1 and the second capacitor region C2 each include a plurality of capacitors and a plurality of resistors 'to simulate a plurality of circuits included in the polyphase filter rccr_combiner 120. The circuit function of the capacitors and the plurality of resistors The flaccid oscillator 14 〇 can effectively reproduce the effect of the current correction code rc_code on the polyphase filter rccr combiner 120. The first capacitor region C1 is coupled between the node N1 and the ground, and has an input terminal for receiving the correction. Code rc a code. The node N1 is coupled to a power source VI, a negative input terminal of the first comparator 310, and a first switch swi, and has a control input coupled to the node N4', that is, the first switch SW1 is connected to the node. The node voltage VN4 of N4 is controlled. When the node voltage \^4 is at a high level, the first open relationship is in a closed state, that is, the first capacitor region C1 is set to a discharge state, when the node voltage VN4 is at a low level. The first open relationship is in an open state, that is, the first capacitor region C1 is set to a charging state. At this time, the first capacitor region C1 uses the correction code rc c〇de to control the circuit operation of the chip built-in capacitor resistor group of 1335131. Controlling the state of charge rc charging constant 0 The second capacitor region C2 is coupled between the node N2 and the ground, and has an input terminal for receiving the correction code rc_cocje, and the node N2 is coupled to a voltage source V2 and a second comparator 320. The negative input terminal and the second switch sw? have a control input coupled to the node N5, that is, the second switch SW2 is controlled by the node voltage RN5 of the node N5' when the node voltage is completely high. Second open relationship In the closed state, that is, the second capacitor region C2 is set to the discharge state. When the node voltage is at the low level, the second open relationship is in an open state, that is, the second capacitor region C2 is set to the charging state. The second capacitor region C2 also controls the circuit operation of the chip built-in capacitor resistor group by the correction code Jiangyi (3) to control the Rc charging constant of the state of charge. • The positive input terminals of the first comparator 310 and the second comparator 320 both receive a bamigap reference voltage Vref, and the output of the first comparator 31〇 is coupled to the first 2 input inverse gate 330 An input end, the output of the second comparator 32A is coupled to the first input of the second 2-input anti-gate 340, the second input of the first 2-input and the gate 33〇 is opposite to the second 2-input The output of the gate 34〇 is coupled to the node N5, and the second input of the first 2-input and gate 340 is coupled to the node N4 of the first 2-input and gate 33〇, and the relaxation oscillator 14〇 The turn-out clock CLK is output to node N4. 1335131 • The first 2-input sluice gate 330 and the second 2-input sluice gate 340 are connected to form an RS latch (RS-Latch), and the first input end of the second input 340 is the Set input. The first input end of the first 2 input anti-gate 330 is the Reset input end. When the Set input end and the Reset input end both receive the high level signal, the RS latch (RS-Latch) is in the latched state. That is, the memory state of the output state is maintained, and it is noted that the latch state (memory state) of the rs latch connected by the two 2-input and the gate is different from the rs connected by the two NOR gates. The flash locker, when the set input terminal receives the high level signal and the reset input terminal receives the low level signal, the output node voltage VN4 of the first 2 input reverse gate 330 is at a high level, and the second 2 input is reversed. The output node voltage VN5 of the gate 340 is at a low level. When the Set input terminal receives the low level • bit signal and the Reset input terminal receives the high level signal, the output signal voltage VN4 of the first 2 input reverse gate 33〇 is low. The level is the same, and the output node voltage VN5 of the second 2-input NAND gate 340 is at a high level. φ If the Set input receives the high level signal and the Reset input receives the low level signal, then the node voltage VN4 is at a high level and the node voltage is 5 at a low level, that is, when the output of the oscillator 140 is relaxed. The pulse CLK is in a high level state, so the first switch is set to the closed state and the first switch is set to the open state, that is, the first capacitor region C1 is set to the discharge state, and the second capacitor region C2 is set to the charge state. State, at this time, because the negative input terminal (node N1) of the first comparator 31〇 is short-circuited to ground, the negative input terminal of the first comparator 31Q is less than the positive input terminal voltage (the energy gap reference voltage Vref). Therefore, the output (Reset input) signal of the first comparator 31〇 is converted from the low level to the high level. At this time, the Set input and the milk input end both receive 5 15 1335131 to receive the high level signal 'so RS The latch is in a latched state, and its output state is unchanged, that is, the output clock clk of the slow oscillator 140 is maintained at a high level, when the node voltage VN2 is charged from the zero potential to be greater than the bandgap reference voltage Vref. 'The input of the second comparator 320 The output (set input) signal is converted from the high level to the low level. At this time, the Set input receives the low level signal and the Reset input receives the high level signal, so the output of the first 2 input reverse gate 330 The node voltage VN4 is converted to a low level, and the output node voltage VN5 of the second 2 input inverse gate 340 is converted to a high level, and * is the output clock of the relaxation oscillator 140. CLK is converted to a low level state. Thereafter, the first switch is set to the open state and the second switch is set to the closed state, that is, the first capacitor region .. C1 is set to the charging state, and the second capacitor region C2 is set to the discharging state. Since the negative input terminal (node N2) of the second comparator 32 is short-circuited to ground 'that is, the voltage of the negative input terminal of the second comparator 320 is smaller than the voltage of the positive input terminal (the energy gap reference voltage Vrei), so the second comparison The output end of the device 320 is Lu (the set input terminal number is converted from the low level to the local level. At this time, the set input terminal and the input terminal both receive the high level signal, so the RS latch is in the latched state, and its output is The state is unchanged 'that is, the output clock CLK of the slow oscillator 140 is maintained at a low level state. When the node voltage VN1 is charged from the zero potential to be greater than the bandgap reference voltage Vref, the output of the first comparator 310 (Reset) The input signal) is converted from the high level to the low level. At this time, the Set input receives the high level signal and the Reset input receives the low level signal. Therefore, the first 2 input reverses the gate node voltage W4 of the gate 330. Convert to 咼 level, and second 2 input The output node voltage of the gate 340 is converted to a low level 'that is, the output clock CLK of the relaxation oscillator 140 is converted to the high level 1335131 - bit state. ♦ · . As described above, the first capacitor region ci and the second capacitor The state of charge and the state of discharge of the region C2 constantly change to generate a time constant of the output oscillation clock CLK' of the relaxation oscillator 14〇 and the state of charge of the first capacitor region ci and the second capacitor region C2. It is proportional to the built-in RC time constant correction code of the chip, so the oscillation period of the clock CLK output of the oscillator 140 is also proportional to the built-in RC time constant correction code rc__code of the chip. From the above, the technical breakthrough of the present invention is known. Prior Art Restrictions on Rc Time Constant Correction 'The present technique utilizes a relaxation oscillator to generate a clock determined by an RC time constant' and counts the period of the clock to generate during a predetermined time period - The cycle count value 're-compares the cycle count value and the - expectation value to perform the Rc time constant correction'. The longer the predetermined time zone, the more the number of valid bits of the correction code rc_c〇de is more The more accurate the RC time constant is. In general, the correction error has a main source of 'the _ is the delay error caused by the comparison thief within the stagnation seam ^, and the other is the synchronous counting error when starting and stopping the counting. In the advanced structure of the present invention, both of these errors can be improved by reducing the vibration frequency of the slow-vibrating device and extending the pre-correction segment by the phase-reduction tolerance, that is, the longer correction time can be improved. Correction accuracy, so the correction of the Rc time constant can achieve the required accuracy, so it can significantly improve the dream image signal of the integrated circuit tuner chip.
SS
㈣ΐ田型式的電1"且與電容，則Rc時間常數隨溫度與電 壓^匕所導至的變動量可降低到可忽略的情況，也就是說，R 響。·，只需在開機時， 作-人RC時間节數校正程序，其後就不需要再作校正。所以，較 ^的校正時間料會對完朗機校正程序後的電路工作造成任何 影響。本發騎提供的高辭度Rc _綠校正方絲裝置可 以確保鏡像訊號遽除功能只受限於多械波器之渡波解析度，而 又限於枝正程序之精準度。本發明架構與使用典型的電壓比較 器架構相味’可節省晶片面積和減低線路的複雜度。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 斤做之均等變化與修錦，皆應屬本發明之涵蓋範圍。 . . 【圖式簡單說明】 _第1圖為根據本發明之積體電路觸n的電路示意圖。 圖為本發明-較佳貫齡丨的二分搜尋逼近校正法之流程圖。 第3圓為第1圖之弛緩振盈器的内部電路示意圖。 【主要元件符號說明】 [Too'— • - η〇~·—- 積體1：路調諧·器 105. 接收電路 B〇 ~~~~-- 正交混頻器 〜 120 多相濾波器 150 數位校正模組 Ϊ40 他缓振盡器 L——_ 2輸入及閘 160 計數器 1335131 170 有限狀態機 310 第一比較器 320 第二比較器 330 第一2輸入反及閘 340 第二2輸入反及閘 rc_code 校正碼 I 同相訊號 Q 正交訊號 CLK 時脈 η 校正碼位元數 NP 週期計數值 ΕΝ 致能訊號 Cl 第一電容區 C2 第二電容區 SW1 第一開關 SW2 第二開關 Vref 能隙(Bandgap)參考電 VI ' V2 電壓源 壓 N1'N2'N3> 節點 VN1 ' VN2 > 節點電壓 N4'N5 VN4 ' VN5 400 流程 200-300 步驟(4) The electric type 1" of the Putian type, and with the capacitance, the variation of the Rc time constant with temperature and voltage can be reduced to negligible conditions, that is, R is ringing. · It is only necessary to make a -man RC time-segment correction procedure at power-on, after which no further correction is required. Therefore, the correction time of ^ is expected to have any influence on the circuit operation after the completion of the calibration procedure. The high-resolution Rc_Green Correction square wire device provided by this ride ensures that the image signal removal function is limited only by the wave resolution of the multi-machine, and is limited to the accuracy of the program. The architecture of the present invention is comparable to the use of a typical voltage comparator architecture to save wafer area and reduce line complexity. The above description is only the preferred embodiment of the present invention, and all the equivalent variations and modifications of the patent application according to the present invention are within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a contact circuit of an integrated circuit according to the present invention. The figure is a flow chart of the binary search search correction method of the present invention. The third circle is a schematic diagram of the internal circuit of the relaxation oscillator of Fig. 1. [Description of main component symbols] [Too'- • - η〇~·-- Integrated body 1: Road tuning device 105. Receiving circuit B〇~~~~-- Orthogonal mixer ~ 120 polyphase filter 150 Digital Correction Module Ϊ40 He Slow Vibration Detector L——_ 2 Input and Gate 160 Counter 1335131 170 Finite State Machine 310 First Comparator 320 Second Comparator 330 First 2 Input Reverse Gate 340 Second 2 Input Reverse Gate rc_code Correction code I Non-inverting signal Q Orthogonal signal CLK Clock η Correction code bit number NP Cycle count value 致 Enable signal Cl First capacitor region C2 Second capacitor region SW1 First switch SW2 Second switch Vref Energy gap ( Bandgap) Reference Power VI 'V2 Voltage Source Voltage N1'N2'N3> Node VN1 'VN2 > Node Voltage N4'N5 VN4 ' VN5 400 Process 200-300 Step