TWI333600B - - Google Patents

Description

1333600, wherein one of the charging signal VCHG generated in the multiplication and division unit of the creation is generated by a first multiplier signal VE and a sawtooth wave signal VSAW, and the sawtooth wave signal VSAW is generated by a divisor signal VAC. The sawtooth signal VSAW is converted from the divisor signal VAC by a current 11 , but the divisor signal VAC generates a current II having a resistance (reference numeral 122 in the previous figure) 'due to the product of different processes There is an error between the body circuit, so the resistance of the current source (122) is relatively opposite to the external resistance value, and the generation of the current II through the resistor (122) produces a process variation. The divisor signal VAC is generated by the current 11. Therefore, the divisor signal VAC also contains an error caused by the process variation, and the error is proportional to the divisor signal VAC, so the output generated by the creation is φ ® The error between the temperature and the process variation produces (10)2, and the multiplier with error is used in the continuous current mode. The active power factor correction circuit will cause the efficiency to be adjusted when the current phase is adjusted. The ideal value needs to be improved. SUMMARY OF THE INVENTION In view of the fact that the prior art does not eliminate the error caused by temperature and process variation, the primary object of the present invention is to propose a multiplier that can perform multiplication and division, and the multiplier has the above-mentioned error To reduce the impact of the error, the result of the calculation is closer to the ideal value. , the invention department - a multiplication and division method with error reduction function, the towel includes - a buffer, a resistor, . Three sets of differential converters, two dividers, two multipliers, and a pulse generator; wherein the multiplication φ, the device is composed of a peak detector and a voltage integrator controlled by the divider for one cycle; „Composed of _ shape generators, these waveform generators are functionally independent and pass their structures through the warfare mode to the lower-level multipliers. In the pulse waver, there are two _units and a silk segment. The wave device resets the square wave production relationship of the unit _ the above-mentioned composition circuit of the present invention, the voltage and electric charge line of the capacitor 11

Pc=M and use this formula to derive the calculation formula of 1333600 'Using two basic calculation formulas to use 丨VC, and the cum% and! The axis current is obtained by the electric current and the division of the Nagata County

Digital transmission diagram! Road block diagram 'This circuit includes - multiply three divisor input terminals noisy first input; = v - second divisor input terminal. And the second divisor signal Vr and a third divisor signal Ve,:: the first number -, - the middle of the multiplier input terminal η and the first differential conversion of the output of the buffer 2 Connected to the first divisor input terminal 12, the number of input terminals 12 - capacitor, by the first - multiplier signal == rr =, reduce the sampling of 』 == 2 Π 7__31 H Er diconverter 32 The first-new job % and ^: ^ number = section ac, the pulse generator 4 receives a divisor conversion signal Iav and generates a pulse signal CLK1 and a second pulse signal CLK2. The second pulse output terminal outputs, and the first dividing unit 51 receives, divides the =3 signal lav, the second divisor signal Vr and the first pulse signal clki to perform a division output, a first, quotient signal SMP1 The first multiplication unit 61 receives the first quotient signal and receives the multiplier conversion signal Iae output by the second differential converter 32 and the first calculation of the first quotient signal and the multiplier conversion signal Iac The product of the product multiplies the j-product signal Va, and the third differential converter 33 receives the first product signal % conversion wheel to output a product conversion signal la; the second dividing unit 5 2 receiving the divisor conversion signal ^ and the second pulse signal CLK2 to calculate an output - the second quotient signal valve 2, and the second two unit 62 receives the product of the output of the third differential converter 33 without a signal ^ The second quotient signal SMP2 and the second pulse signal CLK2 form the product conversion signal to be multiplied by the second line signal 7 1333600 'SMP2 to output the signal Vo; the first-differential converter 3 The second differential conversion benefit 32 and the third differential converter 33 have a function of converting the voltage into a current according to a certain ratio 'Because the first differential converter 3 and the second differential converter 32 are the third difference The dynamic converter 33 is generated by the same-process towel, and thus has the same error wire: the divisor conversion signal (6) generated by the first-differential converter 31 passes through the first division table in the process of generating the output signal v〇 Το 51 and the second division unit 52 perform two reading operations to eliminate two error coefficients to form a division error; and the second differential converter 32 generates a multiplier conversion signal as the first multiplication list 7G 61 Generating the first product signal Va, the first product signal... The third differential converter 33 is converted into a product conversion signal Ia, such that the first multiplier signal Vac also passes through the φ first differential converter 32 and the third differential converter 33 to multiply the error coefficient twice. Forming a multiplication error, so that the product multiplication signal Ia is multiplied by the second quotient signal SMP2 in the second multiplication unit 62, and the error coefficient of the two slave error records and the 帛 multiplication is offset by two. There is no error coefficient in the output signal Vo. For the implementation circuit of the present invention and the waveforms of the respective nodes, please refer to FIG. 2 and FIG. 3 , the first multiplier signal Vac is connected to the second differential _ 32 via a buffer 2 to form the multiplier conversion signal lac. The back end of the buffer 2 is connected to the first divisor input terminal π via a resistor 21, and the first divisor input terminal 12 is connected to a capacitor to form the first divisor signal Vav. The first divisor signal Vav Inputting the first differential converter 31 to form a divisor conversion signal Iav, the divisor switching signal lav and the first divisor signal Vr are input to the first dividing unit 51, and the first dividing unit 51 comprises a switch a square wave generator composed of a component S2 and a capacitor C3 and a square wave generator formed by a comparator U7, wherein the divisor conversion signal is shaped during the magical disconnection of the switching element; g^C3 Charging 'the two input terminals of the comparison S U7 are connected to the capacitor C3 and the second divisor signal Vr, and a sawtooth wave voltage is input through the linear charging circuit to input the square wave generator of the first dividing unit 70 51 and the first Comparing the two divisor signals Vr, the comparator U7 is at the peak of the capacitor C3 And outputting a high level when the voltage exceeds the second divisor signal Vr, and the output of the first dividing unit 51 is formed by dividing the second divisor signal γΓ with the divisor conversion signal Iav for one time period; The second dividing unit 52 is composed of a 闸R gate uu, an AND gate U4 and a comparator υΐ0, and the comparator υιο obtains the divisor of the divisor conversion signal lav and the third The divisor signal Ve is also divided by comparing the magnitude of the divisor conversion signal 8 1333600 lav and the third divisor signal Ve to obtain a time period through which the OR gate U11 and the AND gate are connected. The input to the second multiplication unit & the pulse generator 4 includes a first gate unit 41 and a second flash gate unit 42, and the first flash unit 41 and the second flash unit 42 can be used. The two SR type flip-flops (SR_flip fl〇p) are formed, and the input and output relationship between the first-flash gate unit 41 and the second flash gate unit 42 are well known to those skilled in the art, and are not described here. 'The output of the first dividing unit 51 and the second dividing unit 52 are respectively connected And inputting one of the first flashing unit μ and the second flashing unit 42 to match the outputs of the first dividing unit 51 and the second dividing unit 52, the first flashing unit 41 and the second flashing unit 42 The output terminal outputs the first pulse signal clki and the second φ pulse signal CLK2 ′. The first flash unit 41 and the second flash unit 42 further comprise a one-day ship circuit, and the cycle limiting circuit includes- a switching circuit S6 and a capacitor C4 form a linear charging circuit and a comparator U8 and a constant voltage source. The output of the period limiting circuit is connected to the other input terminals of the first-thrush gate unit 41 and the second gate unit 42. The charging time of the period limiting circuit is caused by the first pulse signal CLK1 (four), and when the capacitance of the circuit is higher than the constant voltage source, the output pulse sends the first pulse signal CLK1 and the second pulse signal. CLK2 becomes a low level; the first pulse signal CLK1 is controlled by a reverse blocking (Ν〇τ is still controlled, the switching element S2 of the linear charging circuit in the first dividing unit 51, thereby controlling the action of the first dividing unit 51 Timing 'the first pulse signal CLK1 passes the reverse closing (n〇t • U5 is then connected to the first multiplication unit ό1 via a reverse gate (10) R gate; the first multiplication unit 61 is composed of a -peak detector and a voltage integrator, and the voltage integrator is It is composed of an H-off element S5 and a -capacitor C5. The turn-on and turn-off of the gate element % is controlled by the first pulse signal CLK. The capacitor C5 is connected to the second differential converter 32. The capacitor C5 is fresh. - Μ CLK CLK1 is fresh _ 雠峨 silk to charge, and the scale detector is formed by a sampling switch S7, a capacitor C6 and a comparator χ 3, when the first quotient of the first division 兀 51 output When the signal SMpi is at a high level, the sampling switch S7 of the peak detector is turned on. The first quotient signal SMpi is the same for the first multiplication unit & the time lion used for the ray, the peak detection ^The integrated power of the voltage integrator, sampling, so that the capacitor C6 is charged to the same voltage level as the capacitor ^, and the first flash gate το 41 also outputs the first pulse signal CLK1, after the reverse (n〇t g(10)u5 9 1333600 TCLRI = ^

Va and _ IacxTcLRi C5^ (4) (5)

Where TCLRI is the time when lac charges C5, and (4) is substituted into (5)

Va

IacxVrxC3 C5

Vn - IaxTCLRl Cl~~ .(6) .(7) •(8) where TCLR2 is the time for la to charge Cl, and substituting equations (3), (6), and (7) into equation (8) V〇= M3xM2xC3^ χ VrxVacxVe

ClxC5xMl2 Vav^ ......(9)

M2=M3 = 1X Ml = coefficient, and the root mean square value of Vav= (2>/^/π) x Vac is obtained: (π/2) X where X is the error of the differential converter Vrms Where Vrms is the first multiplier signal y〇-0.5xVrxVexVac Vrms) v〇 in the calculation formula because the conversion coefficients M2 and M3 of the second differential converter 32 and the third differential converter are located in the numerator, 3⁄4 denominator It is the square of the conversion coefficient 吣 of the first differential converter 31. Therefore, the error coefficient X of the M2 and the M3 towel is offset, so the variables related to the process or temperature are M2, NO, (: Bu C3 and C5) All of them cancel each other out to achieve the purpose of offsetting the error caused by the temperature coefficient and the process. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can not deviate from the spirit of the present invention. And within the scope, and some of the changes made with 1333600 = her application for the application of the patent, in summary, the circuit of the present invention is more conventional, and the progressive patent of the French patent, the patent of the wheel effect novelty Ask for a case, to encourage creation, to the sense of virtue. 'Stomach Bureau approved this piece BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of the circuit of the present invention. Fig. 2 is a circuit diagram of the implementation of the present invention. Fig. 3 is a waveform diagram of the real Wei scale. Point [Description of main components] 12 13 14 15 2 21 31 32 33 4 41 42 51 52 61 62 11 · · · · Multiplier wheel input terminal First divisor input terminal Second divisor input terminal Third divisor input terminal wheel terminal buffer resistance first difference Transducer second differential converter third differential converter pulse generator first latching unit second latching unit first dividing unit second dividing unit first multiplying unit second multiplying unit 12

Claims (1)

1333600 Patent application scope: 1. - Surface with error compensation function (4), made in offset temperature difference 'utilization-multiplier input terminal, one first divisor input terminal, one t-th third divisor input terminal a first multiplier signal, a first divisor 2 rounds=subdivision signal and a third divisor signal' have the output output of the operation result, and the multiplier with the error cancellation function includes: /, Zhongxun H moves 11, the material - except the ship's sag split output New Divisor conversion number; - the second differential converter, which obtains the first multiplier signal and outputs at least one multiplier conversion signal - two pulses, The generator 'receives its-divide-converted signal to generate the first-pulse signal, the first-pulse signal, the other--the first pulse output and the second pulse output, and the first-division unit , in addition to the conversion-off, the first-pulse divisor signal to generate a first quotient signal; the first two divisions are private, receive, receive the divisor conversion signal, the second pulse divisor signal to generate a second quotient signal; a brother-first-multiply yarn element, receiving the practice The signal, the first-pulse quotient signal generates a first product signal by operation; the second signal is transmitted by the second differential converter, and receives the first-product signal and outputs at least a 'product conversion-second wire single it. Receiving the _conversion 峨, the second pulse signal and the second quotient= to calculate the generation-output signal; the divisor conversion signal generated by the first-differential converter is subjected to two division operations by the above operation process Forming a division error, and the multiplier conversion signal and product conversion signal generated by the converter:: disc: differential Han:: yield 4 times ί error 'in the second multiplying unit, the second differential converter ^ The product error generated by the two differential converters is offset by the division error generated by the first-differential converter, and the output of the output signal with the offset error function is achieved. (1) A multiplier with error cancellation function according to the scope of claim 2, wherein the wire input terminal and the first differential switch further comprise a buffer (four), and the bet end and the first 13 1333600 divisor A resistor is connected between the input terminals, and the difference is described in the first item of the "3". The function multiplication and division device =: division early 4 receives the division _ exchange number _ second divisor m Convert the result of the comparison into a first-quotient signal. "There is a square wave to produce 4. If the application is special (4), the error field Wei Zhisi is divided into a single-hearted money ship, and the clock is converted into a second quotient signal. 5·=Please refer to the patent for the error offset described in the item. The Wei Zhicheng generator includes - the -_ unit and the second compensation unit, each (4) secret ugly unit and the first " Receiving the business signal and the second quotient signal, the other input terminals of the first flashing unit and the second flashing unit are connected to the Peng, and the first-only unit and the second (10) unit are: =:: The output end generates a first pulse signal and a second pulse signal, and the output level of the other output end of the first and the first pulse unit is the first pulse signal 6 The error circuit described in the item includes a linear charging circuit, a certain voltage source and a comparator. '7·Multiplier with error cancellation function as described in claim 6 The towel, the charging circuit includes a switching element and a capacitor, the switching element The timing is opposite to the high and low level of the first pulse signal. 8. The multiplier and the error canceling function according to claim 5, wherein the cycle is limited, and the output is connected to the first The flash gate unit and the second flash gate unit, the high level output of the period limiting circuit causes the first pulse signal and the second pulse signal to be converted to a low level. The error counteracts the Weizhisi method, wherein the first-latch gate turns out the output of the first pulse signal to the output of the NOT gate disk - the reverse gate (N〇Rgate). The yarn applicator with error cancellation function according to claim 5, wherein the second latching unit outputs the output of the second pulse signal to connect three reverse gates (N〇Tgab). The ft-to-day correction replacement page j 1L is a multiplier with error cancellation function as described in claim i, wherein the first differential conversion H and the square wave generator of the first division unit are further Including - a linear charging circuit forms a mineral tooth wave voltage input through a hybrid charging circuit The square divider of the first dividing unit is compared with the second divisor signal. 12. The multiplier and the error canceling function according to claim 11, wherein the linear charging circuit further has a switching element. Turning on or off the switching element is controlled by the first pulse signal 'and off-charging", such as the error-compensating power tool described in claim U, wherein the linear charging circuit is red The square wave generator of the second division unit is compared with the three divisor signal. M. The error multiplication division method described in claim 1 of the patent fine item 1, wherein the first multiplication method The unit includes a peak detector and a voltage integrator. 15. An error-compensating Weizhi wire device as claimed in claim 14 wherein the peak detector comprises a sampling switch, a capacitor and a comparator. 16_ If the error is offset by the fifteenth item of the claim, the period of the sampling switch is controlled by the first quotient signal output by the first dividing unit. 17. The multiplier and divider with error cancellation function according to claim 14, wherein the integrator comprises two capacitors and a switch, the capacitor is connected to the multiplier conversion signal to charge 'the switching element The conduction and disconnection are controlled by the first pulse signal. 18. The multiplier and multiplier with error cancellation function as described in claim 17 of the patent application, wherein the first pulse of the county high-level office of the high-level office of the _ component conducts the electric The component _, _ number turn to the rhyme of the ^ pressure integrator capacitor charging. 19.2. The multiplier of the error cancellation function described in claim 15 wherein the peak waver samples the voltage integrated by the voltage integrator, and forms the multiplier conversion signal and the first quotient through the comparator. The first product signal multiplied by the signal. The multiplier of the error cancellation function described in claim 1 is wherein the second multiplying unit comprises a peak detector and a voltage integrator. 21. The multiplier and multiplier with error cancellation function according to claim 20, wherein the peak 15 1333600 value detector comprises a sampling switch, a capacitor and a comparator 22. As claimed in the scope of claim 2 The multiplication and division mode of the error cancellation function is controlled by the lion. The third division is the third quotient of the single actor, and the middle quotation is 23. The ambiguous function as described in the 2G item of the patent application scope. The second pressure integrator of the device includes a capacitor disk, a switch element #, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , . 24. If you apply for the special case, please refer to the article 23, the second pulse signal is the fresh charge of the open and the capacitor is discharged. The second pulse ^« For the high-standard gift to touch the Guan Yuan, the wire is not charged with the capacitor of the voltage integrator. 25. The multiplier and the error canceling function according to claim 21, wherein the peak detector samples the voltage integrated by the voltage integrator, and the comparator converts the signal and the second The output signal of the quotient signal multiplied. 26. The multiply-divider with error cancellation function of claim 1, wherein the first, second, and third differential converters convert a voltage into a current. 27. A multiplier/divider with error cancellation function as described in claim 1 wherein the gains (GAIN) of the second and third differential converters are the same. 28. The multiplier and divider with error cancellation function according to claim 1, wherein the gain of the first differential converter is the second differential converter and the third differential converter (π/ 2) 1333600 Ramp2 Vn 1 1 1- L·^_L— 1 Ramp3 1 1 1 1 SMP2 i ir~ _Π_!_L TCLR2 i 1 | 1 1 Q_U14 1 1 1 | 1 1 - 1 -1- ——1= t(ms) Figure 3 Figure 19