TWI331805B - A single poly, multi-bit non-volatile memory device and methods for operating the same - Google Patents

Description

1331805 IX. Description of the Invention: [Technical Field] The embodiments of the present invention relate to non-volatile memory elements, and in particular to a single-layer polycrystalline germanium non-volatile compatible with a complementary metal oxide half field effect transistor process. Memory component. [Prior Art] Many non-volatile semiconductor memory systems are based on the well-known metal oxide semiconductor structure (MOS). In other words, it includes a gate structure separated from a substrate by a dielectric layer. The diffusion region is implanted in the substrate and below the corners of the gate structure. When an appropriate voltage is applied to the diffusion region and the control gate, a channel can be created in the upper layer of the substrate, between the diffusion regions, and below the gate structure. Carriers such as electrons can move in the channels between the diffusion regions. If there is a strong electric field component in the direction of the gate structure, a carrier such as an electron can be attracted to the gate structure. If the electrons have sufficient energy to overcome the energy barrier of the dielectric layer, these carriers can be implanted through the dielectric layer. For example, Figure 1 illustrates a conventional floating gate memory element 100. It can be understood that the floating gate component can be used as a basic memory structure of a conventional flash memory component. The floating gate element 100 includes a substrate 102 in which diffusion regions 104 and 106 are implanted. In the example of Figure 1, element 100 is an NMOS device, i.e., substrate 102 is a P-type substrate, and diffusion regions 104, 106 are N-type diffusion regions. It can be understood that a specific memory element can also use a PMOS structure, that is, the substrate 102 is an N-type substrate, and the diffusion regions 104, 106 are P-type diffusion.

Chinese spec.-MXIC_P940187_fina! 1331805 area. A dielectric layer 11 is then formed on the substrate between the diffusion regions ι 4 = 106. The dielectric layer is typically a dioxo (si〇2) dielectric layer, which may be referred to as a pass-through oxide layer. - The floating interpole 112 is formed above dielectric = 〇. The floating gate 112 is typically formed from a multi-layer layer, and the layer 2 is deposited on the substrate 102 and is _ to an appropriate size. An interlevel dielectric layer 114 is then formed over the floating gate 112, and a control gate 116 is then formed over the interlayer dielectric layer 114. Like the floating gate m, the control gate 116 is typically formed by etching a polycrystalline layer to an appropriate size. When a suitable voltage is applied to the control gate 116 and the diffusion region /, 106, a channel can be formed in the channel region (10) of the substrate 102. It is known that the voltage applied to the control gate 116 will be pure to the control gate ι 2 for the field component required to attract the carrier in the channel region 1G8 to the floating (four) pole ι2. It can be understood that the light connection between the (four) gate 116 and the floating gate depends on the voltage applied to the control gate 116 and depends on the control gate m, the interlayer dielectric layer 114, and the floating gate. size. π One can further understand that 'in terms of non-volatile semiconductor memory technology, the degree, degree and cost are important driving factors. A large demand for non-volatile semi-elements makes these memories have to be manufactured in a large-scale, low-cost manner. In addition, 'non-volatile semiconductor memory elements for new applications' will require more capacity and smaller size. The elements of Figure 1 prevent several considerations in this regard. First, because the floating gate m and the control gate 116 are shaped by multiple (four) layers

Chinese spec.-MXlC^P940187_final 6 1331805, so the 7L piece 100 is manufactured by a "double layer polysilicon" process. This would make the fabrication of component 100 incompatible with existing CMOS technology because existing CMOS technology is a single polysilicon process. Therefore, in order to manufacture the piece 100, a special manufacturing process will be required. Furthermore, component 1〇〇 stores only one bit of information on month b, which in turn limits the density that can be achieved using component 1〇〇. SUMMARY OF THE INVENTION The present invention discloses a non-volatile memory device that includes a substrate and a dielectric layer formed on the substrate. A control gate is formed on the dielectric layer, and a second ocean gate is also formed on the substrate and located on both sides of the control gate. Therefore, the non-volatile memory element can be fabricated using a single polysilicon process = gas, and thus compatible with existing complementary metal oxide half field effect transistor processes. This component stores dual bit data at each floating gate. According to one aspect of the present invention, the element is formed with two diffusion regions in the substrate, each adjacent to each floating gate. According to another aspect of the present invention, the element may include four diffusion regions adjacent to each of the edges of each of the floating gates. According to still another object of the present invention, the coupling between the gate, the diffusion region and the floating gate is used to form a channel in the substrate to allow operation of the device. In accordance with yet another embodiment of the present invention, channel hot electron technology is used to program the component. According to yet another object of the present invention, ultraviolet radiation (UV) can be used to erase the component.

Chinese spec.-MXIC_P94〇187_final 7 1331805 In accordance with another aspect of the present invention, a band-to-band thermal hole injection (BTBHHI) technique can be used to erase the component. The structure and method of the present invention are described in detail below. SUMMARY OF THE INVENTION The purpose of the section is not to define the invention. The invention is defined by the scope of the patent application. The embodiments, features, objects and advantages of the present invention will be fully understood from the following description of the appended claims. [Embodiment] Each of the embodiments described below relates to a non-volatile memory element including a substrate and a dielectric layer formed on the substrate. A control gate is formed on the dielectric layer, and then two floating gates are deposited on the dielectric layer to control both sides of the gate. The diffusion region is formed in the substrate. The voltage applied to the control gate and the diffusion region can be coupled to the floating gate to form a channel in the substrate, and is provided to enable the carrier in the channel region to penetrate the dielectric layer and enter the floating gate The electric field required. It can be understood that any size, measurement result, range, φ test result, data data, etc. described herein are close to reality and are not used as accurate data. Its proximity to reality will depend on the nature of the material, the content and implementation of the particular embodiment used.

Figure 2 illustrates a non-volatile memory element configured in accordance with an embodiment of the present invention. Element 200 includes a substrate 202 with diffusion regions 212 and 214 formed in the substrate. In the embodiment of Fig. 2, the substrate 202 is a P-type substrate, and the diffusion regions 212, 214 are N-type diffusion regions. Therefore, component 200 is an NMOS component. It can be appreciated, however, that in other embodiments component 200 can be a PMOS device that includes a N 8 Chinese spec.-MXIC_P940187_final 1331805 type substrate and a P-type diffusion region. A dielectric layer 204 is then formed over the substrate 202. Floating gate structures 206 and 210, and control gate structure 208 are then formed over dielectric layer 204 using a single polysilicon process. In other words, the floating gate 206, the control gate 208, and the floating gate 210 are formed from a single polysilicon layer, and the single polycrystalline layer is formed on the dielectric layer 204. The polysilicon layer and dielectric layer 204 are then etched using a conventional lithography technique to form the gate structure and gate dielectric layer shown in FIG. Thus, component 200 can be fabricated using a single polysilicon process, making it compatible with conventional CMOS process technology. An exemplary process for fabricating component 200 is as detailed below. FIG. 3 illustrates an exemplary embodiment of a non-volatile memory element 300 that is configured in accordance with another embodiment of the present invention. In the embodiment of Figure 3, component 300 includes additional diffusion regions 220 and 222. The operational differences between components 200 and 300 will be detailed below. In addition, the differences in the process steps for fabricating components 200 and 300 will also be detailed below. Referring to Figure 2, each of the floating gates 206 and 210 is configured to store a charge representing a bit of information, such as a logic "1" or a logic "0". Thus, component 200 is configured for multi-bit operation, which in turn can increase density, reduce component size, reduce manufacturing time, and/or reduce cost. The voltage applied to control gate 208 can be coupled to floating gates 206 and 210 to assist in the staging, erasing and reading of floating gates 206 and 210. Thus, for example, to program the floating gate 206, the voltage applied to the control gate 208 is coupled to the floating gate 206 to create a channel region 216 in the substrate 202 below the floating gate 206. Coupling to the floating gate 9 English spec.-MXIC_P940187_.fina) The voltage of the pole 206 may also provide the electric field required to induce the carrier to penetrate the dielectric layer 204 into the floating gate 206 in the channel region 216. Similarly, the voltage applied to control gate 208 can also be coupled to floating gate 210 to allow for stylizing, erasing, and reading of the bits stored in floating gate 210. This coupling can be further understood by FIGS. 4 and 5. Figure 4 illustrates the capacitance formed between the gates and layers in component 200 and floating gate 206. It can be understood that the vehicle system for the floating gate 210 is also the same. Therefore, for the sake of brevity, the description of the coupling mechanism associated with the floating gate 210 will be omitted. Similarly, it can be appreciated that the coupling mechanism of component 300 is also the same as component 200. Therefore, for the sake of brevity, the description of the coupling mechanism associated with component 300 will be omitted. As shown in FIG. 4, when a voltage is applied to control gate 208, this voltage will be coupled to floating gate 206 via a control gate capacitance (CCG). The floating gate 206 is then coupled to the substrate 202 via a body capacitor (CB). In addition, when a voltage is applied to the diffusion region 212, the floating gate 206 can be coupled to the diffusion region 212 via the junction capacitance (Cj). This capacitive coupling mechanism generates the electric field required to cause the carriers in the channel region 216 to penetrate the dielectric layer 204 into the floating gate 206. Figure 5 illustrates an exemplary size associated with component 200 in accordance with a particular embodiment. These dimensions can be used to illustrate the coupling that component 200 can produce. First, the control gate capacitance (CCG), junction capacitance (Cj), and bulk capacitance (CB) are obtained by the following equation: CCG = e(H*W)/Ll (1) CB = s(L3*W) /T (2) 10 Chinese spec.-MXIC_P940187_final

Cj = s(L4*W)/T , (7) where ε is the dielectric constant; and w is the width of the gate entering the page Η is the height of the gate L1 is the length of the sidewall between the gates L3 is the dielectric layer The length under the gate does not include L4 L4 is 'the length of the electrical layer under the floating gate, the length of the diffusion region is the thickness of the dielectric layer. Therefore, the control gate capacitance (Ccg) is equal to ε multiplied by the control. The pole (10) is multiplied by the width of the control closed pole and divided by the space between the control poles 2〇8 and the two poles 206. The body capacitance (Cb) is then equal to c times the length of the J electrical layer 204 written at the floating gate (excluding the portion overlapping the diffusion region 212) 'multiplied by the width of the floating gate write, then divided by the dielectric layer The height of 204. The junction capacitance (Q) is equal to 4 to the width of the long-lived gate 206 of the dielectric layer 2〇4 below the floating interpole 206, over the diffusion region 212, and then divided by the dielectric layer 2〇4 The thick overall capacitance is obtained by the following equation: CT 〇T = Cj + CCG + CB (4) The following equation is obtained between the control gate 208 and the floating gate 2〇6: acG ~ Ccg/Ct〇 t (5) The following equation is obtained between the diffusion zone 2] 2 and the floating pole:

English ^c -MXJC P940187 fmai 11 1331805 (Xj = Cj/Ct〇t . (6) Therefore, the voltage on the floating gate 206 can be obtained by the following equation: VfG = (VcG*aCG) + (VN*aJ)(7) Wherein, the VCG is the control gate voltage, and the VN is the diffusion region voltage. For example, in one embodiment, one of the non-volatile memory elements configured according to the system and method of the present invention may include the following dimensions: Η = 1000 angstroms; φ L1 = 200 angstroms; L3 = 400 angstroms; L4 = 200 angstroms; and Τ = 100 angstroms. Therefore, the overall capacitance is obtained by equation (4):

Ctot = Cj + Ccg + Cg = sllW The coupling ratio between the control gate 208 and the floating gate 206 is obtained by equation (5): cxcg = Ccg/Ct〇t = ε5 "W/ε 11W = 5/11 The coupling ratio between the diffusion region 212 and the floating gate 206 is then obtained by equation (6): aj = Cj / Ct 〇 t = b2W / 811W = 2 / 11 voltage on the floating gate 206 , can be obtained by the following equation:

VfG = (VcG*aCG) + (Vn*CIj) = Vcg*5/11 + Vn*2/11 It will be appreciated that the dimensions described herein may vary with the needs of a particular invention; however, it is understood Yes, no matter what size you use, you must have 12 Chinese spec.-MXIC_P940187_final 1331805 to achieve sufficient coupling. Therefore, the actual size of an embodiment must be sufficient to provide the required coupling. For example, in other embodiments, the above dimensions may fall within the following approximate ranges: Η = 800-1500 angstroms;

Ll = 160-300 angstroms; L3 = 300-500 angstroms;

L4 = 160-300 angstroms; and T = 50-250 angstroms. Figure 6 illustrates an exemplary stylized operation of floating gate 206 of component 200, in accordance with an embodiment of the present invention. First, a high voltage can be applied to control gate 208, which is simultaneously coupled to floating gate 206 as described above. A voltage can also be applied to the diffusion regions 212, 214 to create a large transverse electric field across the channel region. In this case, a low voltage is applied to the diffusion region 214 (here acting as a source region) and a high voltage diffusion region 212 (here acting as a drain region) is applied. The high voltage applied to the diffusion region 212 is also coupled to the floating gate 206 as described above. The high voltage coupled to the floating gate 206 must be sufficient to allow the inversion channel region 216 to be formed below the floating gate 206, thereby allowing the large transverse electric field to induce a carrier (here, electron 602), and the carrier is in channel 216. The medium flows from the diffusion region 214 to the diffusion region 212 and finally flows into the floating gate 206. The voltage coupled to the floating gate 206 must be sufficient to cause at least a portion of the carrier 602 to be injected into the floating gate 206 via the dielectric layer 204. The injected carrier is then stored in floating gate 206, which in turn changes the threshold voltage (VT) and thus the state of floating gate 206. 13 Chinese spec.-MX!C_P940187_final 1331805 It can be appreciated that the carrier 602 must have sufficient energy to overcome the energy barrier height of the electrical layer 2〇4. For example, if the dielectric layer is the second layer, the electric layer, the carrier must have more than 3 plus energy, and the energy barrier height of the layer 102 is taken. In the first embodiment, generally referred to as channel hot electron (CHE), the main form is shown in the embodiment of Fig. 6, and the high voltage system is about to be applied to two (6). A high voltage of about 5 volts is applied to the diffusion region' while the extended region 214 is maintained at about / for example, and the actual ^ mussels vary in the manner of the mode. For example, the electric dust applied to the control gate can be between about 8 and η volts, and the fourth (four) can be (four) 4 to 6 volts. FIG. 7 is an embodiment of the present invention. In the program: exemplify the CHE method. Here, the lateral direction must be two = the st channel 218, the carrier from the diffusion region 2: the plant road 218 is applied to the control interpole 2. 8 movement = 33 ' is generated by floating so that at least part of the carrier is required Sufficient for 210. Injected by the "Electrical layer, the floating gate 2: true and = domain committed' while the diffusion region 214 is applied to the diffusion zone X; the electric galaxy is used as an example only, And the actual two = changes in the needs of the specific implementation of the attacker. For example,

English 5^..^1(:_„4〇|87 fina| 1331805 > In the case of 4 to 6 volts of 丨 2 volts, the voltage applied to the control gate 208 may be between approximately and applied to The electric potential of the diffusion region 212 may be between about 0. It can be understood that in the J-stone method illustrated in FIGS. 6 and 7, the donor tracks 216 and 218 are the lengths of the region of the substrate 202 from the bar mw. The steamer region 212 extends to the diffusion region 214. These channels are generated by the voltage applied to the control, and the voltage is between the floating gates 206 and 21 Μ „ 〇 2〇8 < +, Coupling Figure 8 shows an exemplary method for erasing the first position of the element 2〇〇 according to an embodiment of the invention. In the embodiment of Fig. 8, the belt is brought to the stage with thermoelectricity. A hole (ΒΤΒΗΗ) implantation technique is used to erase the floating idler. The use of the tape to the hot hole injection system is generated by generating a gate induced drain leakage current (GIDL) between the floating gate 206 and the diffusion region 212. The negative force is biased to the floating gate 206 and a positive bias is applied to the diffusion region, and a gate-induced drain leakage current is generated. The negative voltage in Figure 8 is applied to the control gate 208. This large negative voltage is coupled into the non-volatile pole 206, thus applying a negative bias to the floating gate 206. Diffusion region 212. Diffusion region 214 is maintained at a low voltage (= 〇 volts) to prevent strip to the hot hole to erase floating gate 2 & ' in the state of Figure 8, under floating gate 206 And a large portion of the N-type diffusion region 212 near the channel 216 is erased. The electric field across the dielectric layer 204 is sufficiently large, and the doping/density of the diffusion region 212 is between about 1 and 18. When in the range of 1019cnT3, the hole 802 can pass through the 'channel w electrical layer 204 and flow into the floating gate 206' and erase all the electrons stored in the floating gate 206. 15 Chinese spec.-MXIC_P940187_final 1331805 The voltages depicted in Figure 8 are for illustrative purposes only, and the actual voltage may vary with the requirements of a particular implementation. For example, in certain embodiments, applied to a control gate The voltage of the pole 208 can be between about -15 and -25 volts, and The voltage applied to the diffusion region 212 can be between about 4 and 6 volts. FIG. 9 illustrates an example of a second band of the component 200 being erased to a hot hole in accordance with an embodiment of the present invention. Therefore, it applies a large negative voltage (for example, -20 volts) to the control gate 208 to apply a negative bias φ to the floating gate 210. In this example, the diffusion region 214 is applied with a positive bias. (eg, 5 volts), while the diffusion region 212 is maintained at a low voltage (ie, 0 volts) to avoid stripping the floating gate 206 to the hot hole. The electric field generated by the bias applied to the floating gate 210 and the diffusion region 214 and across the dielectric layer 204 will consume some of the electrons in the diffusion region 214 and begin to be generated in the dielectric layer 204. The tape of the secondary carrier 902 is injected into the floating gate 210 with a thermal hole, and the electrons previously stored in the floating gate 210 are erased here. φ Similarly, it will be appreciated that the voltages shown in Figure 9 are for illustrative purposes only and that the actual voltage will vary with the requirements of a particular embodiment. For example, in a particular embodiment, the voltage applied to control gate 208 can be between about -15 and -25 volts, and the voltage applied to diffusion region 214 can be between about 4 and 6 volts. FIG. 10 illustrates an exemplary method for erasing component 200, in accordance with an embodiment of the present invention. According to Fig. 10, ultraviolet light 1004 is irradiated over the element 200. The energy of the ultraviolet light 1004 provides energy sufficient to penetrate the electrons of the dielectric layer 204 and leak into the substrate 202. 16 Chinese spec.-MXIC_P940187_final 1331805 FIG. 11 illustrates an exemplary reverse read operation of the floating gate 206 for reading an element, in accordance with an embodiment of the present invention. First, a high voltage must be applied to the control gate 208. A high voltage can also be applied to the diffusion region 214 and a low voltage is applied to the diffusion region 212. In the implementation of Fig. 11, a high voltage (e.g., about 6.6 volts) ranging from 5 to 9 volts can be applied to the control gate period. Simultaneously apply - a high voltage (e.g., about 16 volts) to about 2 to 2.5 volts to the region 2M. Diffusion region 212 can be maintained at a low voltage of approximately one volt volt. Similarly, the voltage system shown in Figure U is for illustrative purposes only, and the actual voltage will vary with the needs of a particular implementation. In accordance with an embodiment of the present invention, an exemplary reverse reading operation of the pre-operation gate 210 is shown. Here, the voltages of the mouth to the diffusion regions 212 and 214 are opposite, so that the bits on the left side of the storage member 200 can be read. In the embodiment of the ancient Fig. 12, a range of between about 5 and 9 volts is applied to the control gate 208. And applying a high-ink with a sensitivity of about i to 2.5 volts (for example, about Μ = 212, the diffusion region 214 can be maintained at about volts. The voltage shown in volts is only used as an example, and actually The change of the embodiment is in accordance with the requirements of the embodiment. The third figure is based on the present invention - a stylized operation. Like the flute / tamping " exemplification of the example 300 (CHE) λ η Figure 6 In the embodiment, the use of channel hot electrons is considered to include the first bit of the three-form!_匕=300. The component 300 can be field 214, 220, and the memory is replaced by the oceanic gate 21G and the diffusion region, and an access voltage Crystal by control gate 208 and diffusion

Chinese spec.-MXlC_P940!87_finaJ 17 1331805 The area 220, 222 is constructed, and a second storage element is composed of a floating gate 2〇6 and diffusion regions 222, 212. In order for the current to flow in the channel region 216 to program the floating gate 206, the access transistor must be open. Therefore, a high voltage can be applied first to the control gate 2〇8. Supply to the voltage of the pole 208 will open the & control crystal including the control gate 2〇8. At the same time, a voltage can be applied to the diffusion regions 212 and 214 to produce: a large transverse electric field across the channel region. In this case, a low voltage is applied to the diffusion region 4 214 while a high voltage is applied to the diffusion region 212. The high voltage applied to the diffusion region 212 is also simultaneously coupled to the floating pole 206, as shown above. The high (four) connected to the floating gate 206 must be sufficient to allow a reversal channel region 216 to be formed under the floating gate and cause the electrons 13 〇 2 in the carrier to be in this region by a large transverse electric field. The voltage induced and flowing from the diffusion region 222 to the diffusion gate 206 in the channel 2丨6 must also be sufficient to cause at least a portion; 1302 injects a floating gate write via the dielectric layer 2〇4. Note = Yes, it will be stored in the floating secret, and its critical power (Vt) will be changed, and then the state of the oceanic gate 2〇6 will be programmed. It can be understood that the energy of the carrier 13〇2 must have a barrier height of 2〇4. For example, if the dielectric layer is transferred to the Xixi dielectric layer, the energy of the carrier 1302 must be higher than the energy barrier height of the 3 2e^, = yttria layer 204. In the embodiment of Fig. 13, an approximation is applied to the control gate and a maximum of about 5 volts is applied.

Chinese spcc.-MXlC_P94〇187_final 18 1331805 The scattered region 212, and the diffusion region 214 is understood to be that the voltage system described herein is only used as a temple. The voltage can vary with the requirements of the particular embodiment and the actual voltage can be applied to the control gate 2G8. In the case of = and the force of the TM is applied, the voltage can be two. An example of a floating element according to an embodiment 3 (9) of the present invention is that the channel element must be reversed so that the carrier 14〇2 is in the pass, the transverse region 220 flows into the diffusion region 214, and diffuses to the control pole. The m of the diffusion region 214 and the diffusion region 214 are formed below the floating gate 210 due to the applied dissipation. The coupling, 21 = voltage, must be sufficient to cause at least a portion of the carrier 2; (iv) the dielectric layer 204 to be implanted into the floating gate 21 〇. In the embodiment of Fig. 14, the application of _ approximately two volts 2 〇 8 ′ and a high voltage of approximately 5 volts is applied and the diffusion region 212 is maintained at approximately 〇 volts. It can be used as an example, and the actual electricity is real; the demand changes. For example, in a particular=歹, the electricity applied to the control gate is between about ^1 (1) dogs: and the dust applied to the diffusion region 214 can be between about 4 and 6 volts - a large negative charge is applied. Dust to control 208 β this big as negative

Chinese spec.-MXIC_P940I87_finaI 19 1331805 . Hybrid to floating pole 206' to apply negative dust to floating (five) poles. High dust can then be applied to the diffusion region 212. The diffusion region 214 is maintained at

- Low voltage (ie 0 volts) to avoid stripping the pole 210 to the hot hole. J In the condition of Figure 15, a large portion of the diffusion region below the floating gate 2〇6 and close to the channel region 216 #N will be erased. When the electric field across the dielectric layer 204 becomes sufficiently large, the hole 15〇2 can be injected into the floating gate 通过 through the dielectric layer 204 and erased there. Any previously stored in the floating gate 206 Electronics. It will be appreciated that the voltages described in Figure 15 are for illustrative purposes only and that the actual voltage will vary with the requirements of a particular embodiment. For example, in a particular embodiment, the voltage applied to control gate 2〇8 can be between about -15 and -25 volts, and the voltage applied to diffusion region 212 can be between about 4 and 6 volts. between. Figure 16 is a diagram showing a tape-to-belt method for erasing a second bit of an element 3A, in accordance with an embodiment of the present invention. Therefore, a large negative voltage (e.g., volts) is applied to the control gate 208 to apply a negative bias to the floating gate 21. In this example, the diffusion region 214 is applied with a positive bias (e.g., 5 volts). And the diffusion region 212 is maintained at a low voltage (eg, volts) to avoid stripping the floating gate 2〇6 to the hot hole. The electric field across the dielectric layer 2〇4 is generated by the bias applied to the floating gate 210 and the diffusion region 214, which eliminates some of the electrons in the diffusion region 214 and is generated in the dielectric layer 204. The secondary carrier 16〇2 begins to be taped into the thermal via to the floating gate 210, where the electrons previously stored in the floating gate 21 are erased. 20 English spec.-Mxic_p94〇lg7_fmai 1331805 Similarly, it can be understood that the voltage system described in Fig. 16 is only used as an example, and the actual voltage will vary with the demand of the financial system. For example, in a particular embodiment, the electrical waste applied to the control gate can be between about -15 and 25 volts' and the voltage applied to the diffusion region 214 can be between about 4 and 6 volts.

Figure 17 is a diagram showing an exemplary erase operation of component 3 (8) in accordance with an embodiment of the present invention. In the embodiment of Fig. 17, the ultraviolet rays 7 are applied to the element 300. The energy of the ultraviolet light 1704 provides an electron 1702 with sufficient energy to penetrate the dielectric layer 204 and leak into the substrate 2〇2. Figure 18 is a diagram showing an exemplary reverse read operation of the floating gate 206 for reading an element, in accordance with an embodiment of the present invention. First, a voltage must be applied to the control gate 208. A high voltage can also be applied to the diffusion region 214' while applying a low voltage to the diffusion region 212. The high voltage applied to the control gate 208 turns on the access transistor including the control gate 2〇8. In the embodiment of Fig. 18, a high voltage (e.g., about 6.6 volts) ranging from 5 to 9 volts can be applied to the control gate 2〇8. Simultaneous application -

A high voltage (e.g., about 16 volts) ranging from about 1 to 2.5 volts is applied to the diffusion region 214. The diffusion region 212 can be maintained at a low voltage of about -about volts. Similarly, the voltage system shown in FIG. 18 is used as an example only, and it can be understood that the actually used f-voltage will be implemented with specific implementation. And change. Similarly, Fig. 19 illustrates an exemplary reverse read operation of the floating gate 210 for the borrowing component 300, in accordance with an embodiment of the present invention. Here, the NMOS applied to the diffusion regions 212 and 214 is reversed, and can be stored on the left side of the element 300. °

English spee, MXIC_P940187_final 21 1331805 In the embodiment of Fig. 19, a high voltage (e.g., about 6.6 volts) ranging from 5 to 9 volts can be applied to the control gate 208. A high voltage (e.g., about 1.6 volts) ranging from about 1 to 2.5 volts is applied simultaneously to the diffusion region 212. The diffusion region 214 can be maintained at a low voltage of about 0 volts. Similarly, the voltage shown in FIG. 19 is for example only, and it will be appreciated that the actual voltage used will vary with the particular implementation. Change in demand. Thus, the non-volatile memory elements described above, and related methods, can provide higher density, lower cost, and less power consumption. In addition, the above components are compatible with the conventional single polysilicon manufacturing process, which can further reduce costs and increase production. 20-24 are cross-sectional views of particular process steps for fabricating a non-volatile memory element configured as an element 200 in accordance with an embodiment of the present invention. First, as shown in Fig. 20, the process can be started by a substrate 2002. In the embodiment of Fig. 20, the substrate 2002 is a P-type germanium substrate, however, it will be appreciated that an N?-type germanium substrate can also be used in accordance with embodiments of the present invention. A gate dielectric layer 2004 is then formed over the substrate 2002. For example, the gate dielectric layer 2004 can be a germanium dioxide (SiO 2 ) layer. The gate dielectric layer 2004 can be deposited by chemical vapor deposition (CVD), particularly by depositing the gate dielectric layer 2004 using a high density plasma chemical vapor deposition (HDPCVD) process. A polysilicon layer 2006 is then deposited over the gate dielectric layer 2004. The polysilicon layer 2006 can also be deposited by a chemical vapor deposition process. As shown in Fig. 21, the polysilicon layer 2006 is then patterned using a photoresist mask formed by a photoresist layer 22 Chinese spec.-MX!C_P940187_final I33l8〇5 2008, and the photoresist layer 2008 is applied to Above the polycrystalline stone layer 2006. Photoresist layer 2008 can be coated and patterned (or defined) using conventional photolithographic techniques. As shown in Fig. 22, once the photoresist layer 2008 is as defined in Fig. 21, the polycrystalline layer 2006 and the gate dielectric layer 2004 can be engraved to form a gate structure 2010, 2012, 2014. Since the vertical sidewall gate structure 2010, 2012, 2014 must be 'optional' to use an anisotropic etch process to etch the polysilicon layer 2006 and the gate dielectric layer 2004. The defined photoresist % layer 2008 can then be removed using, for example, plasma ashing. As shown in Fig. 3, the oxide sidewall spacers 2016 are then formed on the sides of the gate structures 2010, 2012, 2〇14. For example, oxide sidewall spacers 2016 may be formed by depositing an oxide layer on substrate 2002 and then removing (etching) unwanted portions. As shown in Fig. 24, the diffusion regions 2, 18, 2020 can then be formed in the substrate 2002. Figure 25 is a diagram showing the process steps for manufacturing a component. Therefore, the fabrication of the component 300 can be performed in accordance with the method of fabricating the component 200 in the above FIGS. 20-22; however, as shown in FIG. 25, once the gate structure 2010, 2012, 2014 is formed, the diffusion region 2018 can be performed. Implantation of 2020, 2022, 2024. Once the implantation of the diffusion regions 2〇18, 2〇2〇, 2022, 2024 is completed, the oxide side wall 2016 can be formed as shown in Fig. 23. It will be appreciated that the above steps do not represent all of the steps required to make a non-volatile § element. It can be understood that other pre- and subsequent process steps such as a cleaning step, a grinding step, and a polycrystalline step 23 Chinese spec.*MXIC_P940187_final are also required. Therefore, (4) can be used to solve the above-mentioned memory elements:: off = all the non-volatile needs of the invention are not required to be used to specify the manufacture of the components - the preferred implementation For the sake of description, the creation of B 2 W for our replacement is not limited by the detailed description. The Shigu 1 ^ style system has been suggested in the previous description, and the pottery style will be considered by those skilled in the art. February; February: The structure and method of the invention, all of which have components that are substantially the same as this month. The combination of (4) and the results of the present invention is the same as that of the invention. Accordingly, all such alternatives and modifications are intended to be in the scope of the appended claims and their equivalents. Any patent application and printed text mentioned in the foregoing section are references to this case. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a conventional floating gate memory element; FIG. 1 is a diagram showing a configuration of a non-volatile memory second element according to an embodiment of the present invention. FIG. In one embodiment, an example shows a configuration of a non-volatile memory element; FIG. 4 illustrates that the element in FIG. 2 is coupled to a floating gate; and FIG. 5 illustrates an exemplary size of the element in FIG. 6 is an illustration of an exemplary method for programming a first bit in a second image element, in accordance with an embodiment of the invention;

English spec.-MXiC P940I87 final 24 1331805 FIG. 7 illustrates an exemplary method for programming a second bit of the second image element according to an embodiment of the present invention; FIG. 8 is an embodiment of the present invention, An exemplary method for erasing the first bit in the second image is shown; FIG. 9 is a diagram illustrating the second bit in the second image according to an embodiment of the invention. Illustrative method; ° FIG. 10 illustrates an exemplary method for erasing two bits in the element of FIG. 2 according to another embodiment of the present invention; FIG. 11 is a diagram showing an embodiment of the present invention An exemplary method for inversely reading a first bit in a second picture element; FIG. 12 is a diagram illustrating an exemplary method for inversely reading a second bit in the second picture element, in accordance with an embodiment of the invention; FIG. 13 is a diagram showing an exemplary method for programming a first bit in a third figure element according to an embodiment of the invention; FIG. 14 is a diagram showing a third form for programming according to an embodiment of the invention. An exemplary method for the second bit in the diagram element; FIG. 15 is a diagram illustrating the erasing of the third in accordance with an embodiment of the present inventionAn exemplary method of the first bit in the component; '° Fig. 16 is a diagram for erasing the third in accordance with an embodiment of the present invention. An exemplary method of the second bit in the component; ** P is an exemplary method for erasing two bits in the third component according to an embodiment of the invention; " Figure 18 is based on An embodiment of the present invention is an exemplary method for inversely reading a first bit in a picture element. FIG. 19 is a diagram showing an inverse reading of a third bit according to an embodiment of the invention.

Chinese spec.-MXic^P94〇I87

JinsA 1331805 1002 Electronics 1004 UV 1302 Electronics 1402 Electronics 1502 Hole 1602 Hole 1704 UV 2002 z ray substrate 2004 Gate dielectric layer 2006 Polycrystalline layer 2008 Photoresist layer 2010, 2012, 2014 Gate structure 2016 Side wall 2018, 2020, 2022, 2024 diffusion area

27 Chinese spec.-MXTC_P940187_final

Claims (1)

I?31805 The Republic of China invention patent application No. 095120682 No-line application patent scope replaces the Republic of China on May 1999. The application scope is as follows: 1. A non-volatile memory component, comprising: a substrate; a dielectric layer formed on the substrate; a control gate formed on the dielectric layer; a first floating gate formed on the dielectric layer and located at the control gate a second floating gate formed on the dielectric layer and located on the other side of the control gate; a first diffusion region formed in the substrate adjacent to the first floating gate a pole; and a second diffusion region formed in the substrate proximate the second floating gate. 2. The non-volatile memory device of claim 1, wherein the substrate is a 基板-type substrate. 3. The non-volatile memory device of claim 1, wherein the substrate is an n-type substrate. 4. The non-volatile memory device of claim 1, wherein the first and second floating gates and the control gate are fabricated using a single polysilicon process. 5. The non-volatile memory element according to claim 1, wherein the f gate and the first diffusion region are configured to be applied to the control gate and the first diffusion region. And it is lightly combined with the first floating gate. ^ As in the non-volatile memory element described in claim 5, the h is at the height of the (-) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Divided by the distance between the control closed pole and the floating idler. 22. The non-volatile memory element described in item 6 of the patent application scope, the height of the control _ in 1 is about _ to!埃(四)strGm)t ^ & as claimed in the sixth item of the tenth is between the control gate _ to 300 angstroms. The distance between the first sweating poles is about the non-volatile memory element of the medium (4) item = item 1, the capacitance between the pole and the first diffusion region is below the floating gate, The first diffusion region is then divided by ": thick" multiplied by the width of the first floating gate. The non-volatile memory element of the two items, the length of the dielectric layer, is about 29 1331805, eight The non-volatile memory element described in the ninth aspect of the patent has a thickness of about 50 to 250 angstroms. The non-volatile memory element described in item 1 of the circumference, the control U: The second diffusion region is configured to be coupled to the second floating gate member by applying a voltage to the second diffusion region, and the second floating gate member The non-volatile memory element is widely produced, and the height of the gate is multiplied by the control gate distance Γ divided by the piece 13 g between the control pole and the floating gate The non-volatile memory element and the height of the open end of the work are about 800 to 1500 angstroms. The non-volatile record described in item 13 of the patent scope of 15 The distance between the gate of the 160^3〇〇1 gate and the second floating electrode is the non-volatile memory element of the first range of the paste range, and the width of the capacitance between the dielectric layers. '- electricity 30 below the second floating gate and above the second diffusion region on the non-volatile memory element of claim 16 of the patent application scope under the "::^:= and The length of the second diffusion region is about 100 to 300 angstroms. The non-volatile memory element according to item 9 of the second aspect, wherein the thickness of the tantalum layer is about 5 〇 to 25 〇. For example, in the non-volatile memory element described in claim 1, the second diffusion region and a fourth diffusion are formed in the substrate close to the first floating space: two: / fourth diffusion region Formed in the substrate proximate to the second floating gate and the control gate. ^0. The non-volatile memory component of claim 1, wherein the component is configured to store information of two bits. a fi. includes a substrate, a dielectric layer, a first floating gate, a jth floating gate, and a control gate formed on the dielectric layer, and the first diffusion region is formed on the first diffusion region A method for forming a fourth non-volatile memory device in the substrate adjacent to the first floating gate and a second diffusion region in the substrate, wherein the method is: Applying a voltage to the control gate, wherein the control gate is configured to apply a voltage of 31 1331805, the voltage applied to the first floating gate of the 3H to be below the first floating gate in the substrate Generating a channel; and applying a force voltage to the first diffusion region and applying a low voltage to the second diffusion region 'to generate a high level electric field between the first and second diffusion regions. The method of claim 21, wherein the high voltage applied to the edge control gate is about 8 to 12 volts. The method of claim 21, wherein the high voltage applied to the first diffusion region is about 4 to 6 volts. The method of claim 21, further comprising: injecting a charge into the second floating gate, wherein the step of charging a charge to the second floating gate comprises: adding a voltage to the control a gate, wherein the control gate is configured to combine the applied electric dust with the second floating gate to generate a channel at a lower floating gate of the substrate in the substrate; and apply a Applying a high voltage to the second diffusion region and applying a low voltage to the region to generate a high level electric field in the first and second diffusions. The method of claim 21, wherein the component is further a third diffusion region is formed in the substrate near the first floating gate and the control gate, and a fourth diffusion region is formed on the substrate 32 (3) 1805 and the control gate, and wherein The horizontal electric field of the injection and the person's manual gate is between the β筮1 and the third diffusion region. /, in the first package two (four) 21 method 'where the component is more polar with the domain it formed? The substrate is adjacent to the first floating gate, and the fourth diffusion region is formed at the substrate pole and the control pole, and is used for injecting a second The high level electric field is formed between the second and fourth diffusion regions. Forming a first diffusion region formed in the dielectric layer, including a substrate, a dielectric layer, a first floating gate, a dirty gate, and a control gate. a method in the substrate adjacent to the first floating gate, and a second diffusion region formed in the non-volatile memory element in the substrate adjacent to the second floating electrode, a method for erasing the component, including Applying a large negative voltage to the control gate, the control gate being configured to couple the applied voltage to the first floating gate; applying a high voltage to the first diffusion region, wherein the An electric field between the first floating gate and the first diffusion region generates a secondary carrier in the = diffusion region and provides sufficient energy for the secondary carriers to implant the dielectric layer, And injecting into the first floating gate; and applying a low voltage to the second diffusion region. 33. The method of claim 27, wherein the large negative voltage applied to the gate is about -15 to -25 volts. The method of claim 27, wherein the high voltage applied to the '-first diffusion region is about 4 to 6 volts. 30. The method of claim 27, further comprising causing the second floating gate to be electrically charged, wherein the step of causing the hole to be injected into the pole comprises: cutting "a J applied - a large negative voltage to the a control electrode configured to couple the applied voltage to the second floating gate; applying a high voltage to the second diffusion sequence, wherein the second electrode and the second diffusion region are generated An electric field that generates a secondary carrier in the U-diffusion region and provides sufficient energy for the secondary carriers to penetrate into the dielectric layer and into the second floating gate; and apply a low The method of claim 27, wherein the non-volatile member further comprises a third diffusion region formed in the substrate proximate the 苐-soil gate and the control a gate portion 'and a substrate adjacent to the second floating interpole and the control electrode. The postal-J moving ^ has a substrate, a dielectric layer, a - first floating gate, a brother -: a gate and a control gate are formed on the dielectric layer and a first diffusion region Formed in the substrate proximate to the first-floating electrode 34, and the second diffusion region is formed in the substrate to be adjacent to the second floating flute non-volatile (four) & The method of erecting the galvanic gate includes: applying a high voltage to the control gate; applying a low voltage to the first diffusion region; and applying a high voltage to the second diffusion region. The method of claim 32, wherein the high voltage applied to the control gate is about 5 to 9 volts. The method of claim 32, wherein the method is applied to the second The method of claim 32, wherein the low voltage applied to the first diffusion region is about volts. The method of claim 5, wherein the non-volatile memory element further comprises a third diffusion region formed in the substrate near the first floating gate and the control gate, and a fourth diffusion region formed on the substrate Approaching the substrate a floating gate and the control gate. 37. A substrate, a dielectric layer, a first floating gate, a second floating gate, and a control gate are formed on the dielectric layer Above, a first diffusion region is formed in the substrate near the first floating gate, and a second diffusion region is formed in the non-volatile memory device in the substrate near the gate of the second floating 35 U31805 a method of floating between two poles, comprising: applying a high voltage to the control gate for applying a high voltage to the control gate; applying a high voltage to the first diffusion region; and applying a low voltage to the second diffusion region 38. The high voltage of the control gate as described in claim 37 of the patent application is about 5 to 9 volts. The law is added to the 39. As described in the 37th article of the patent application. The high voltage of a diffusion region is about! The low voltage system is about Q volts as applied to the second diffusion region of the 37th aspect of the patent application. 〃 applied to the method described in item 37 of the 5th bis. 2 wherein the non-volatile portion;:=== region Γ shape in the substrate is close to the second floating two in the substrate:: control:::: region Forming a method for manufacturing a non-volatile memory element, comprising: forming a control gate structure on a substrate; · forming a structure-"4 a floating closed-pole structure on the substrate, located in the control a first diffusion region is formed on the other side of the second axis interpole structure substrate on the other side of the bit control idler 36 1331805, and the first diffusion region is adjacent to the first floating structure; and the gate is formed A second diffusion region is adjacent to the second floating gate structure in the substrate. The method of claim 42, further comprising forming a third diffusion region at the substrate + proximate the first-floating gate structure and the control gate structure. The method of claim 43, further comprising forming a fourth diffusion region in the substrate proximate to the second floating gate structure gate structure. The method of claim 42, wherein the step of forming the second electrode, the structure, the second floating gate structure, and the step of controlling the gate structure comprises: depositing one a dielectric layer on the substrate; 'Ultra-polycrystalline layer on the dielectric layer; defining the polycrystalline layer by a photoresist layer; and etching the defined polysilicon layer and the dielectric layer. 46. The method of claim 45, wherein the dielectric layer 3 is deposited by chemical vapor deposition. 37 (4) Dielectric layer The method of claim 42 further includes forming an oxide sidewall between the gate structures. 38