TWI331804B - Thin film transistor substrate and manufacturing method thereof and display panel incorporating the same - Google Patents

Description

1331804

- DIAMOND NUMBER: TW2448PA - IX. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor (TFT) substrate, a method of manufacturing the same, and a display panel using the same, and in particular The invention relates to a display panel which is applied to a thin film transistor substrate manufactured by a three-mask process and a manufacturing method thereof. [Prior Art] • With the development of liquid crystal display panel (LCD panel) manufacturing technology, its advantages such as lightness, power saving, and low radiation have gradually led to the widespread use of liquid crystal display panels such as LCD TVs and digital cameras. In all kinds of electronic products. The liquid crystal display panel using the thin film transistor substrate is more popular in high-order electronic products because of its high brightness and large viewing angle. A conventional thin film transistor substrate and a method of manufacturing the same are described below. • Refer to Figures 1A to 1E for a cross-sectional view of a conventional thin film transistor substrate. Here, a partial cross-sectional structure of a single element is taken as an example. First, a first mask process is performed in Fig. 1A to form a gate 110 on a glass substrate 100. Next, as shown in FIG. 1B, a second mask process is performed to sequentially form a gate insulating layer 120, an amorphous silicon (a-Si) germanium semiconductor layer 130, and a doped N-type. The (N+) semiconductor layer 140 is over the glass substrate 100. The gate insulating layer 120 covers the gate 110, and the a-Si germanium semiconductor layer 130 is formed in the gate insulating manner corresponding to the gate 110. 6 1331804

- Sanda number: TW2448PA 'On layer 120, 'N+ semiconductor layer H0 covers the a-Si germanium semiconductor layer 13 terminal. Then, as shown in FIG. 1C, a third mask process is performed, γ, a drain 160 and a source 165 are formed on the gate insulating layer 12 160 160 and the source 165 to correspond to the a_si 矽 semiconductor layer. The two ends of the 13" cover the N+ semiconductor layer H0 spaced apart from each other, and are electrically contacted by the two ends of the N+ semiconductor 140 and the a-Si. Gate (10): The a-Si 矽 semiconductor layer 130, the drain 16 〇 and the source 165 constitute a thin film φ crystal 150. 'Next' performs a fourth mask process as shown in Fig. 1D to form a protective layer 170 over the gate insulating layer 120. Protective layer I?. Covering the a_Si 矽 semiconductor layer 130, the drain 160 and the source 165, and having a contact hole 17;!, the contact hole 171 is used to expose a portion of the drain 160 °. Finally, as shown in FIG. 1E, A fifth mask process is performed to form an indium tin oxide (IT0) pixel electrode 18 on top of the protective layer. The ITO halogen electrode 180 is in electrical contact with the drain 160 through the contact hole 171. At this point, the thin film transistor substrate 2 is finally finished. The above conventional thin film transistor substrate and its manufacturing method require a total of five mask processes. Therefore, under the consideration of reducing the cost of the process, it is not enough. Therefore, how to reduce the mask process steps to significantly reduce the cost of the process or even shorten the process time is obviously the goal that the industry is currently trying to achieve and the problem to be solved. 1331804

- Sanda number: TW2448PA - [Invention] In view of the above, an object of the present invention is to provide a novel thin film transistor substrate and a manufacturing method thereof using the display panel thereof, which greatly eliminates the process of the conventional thin film transistor substrate Design flaws. The thin film transistor substrate of the present invention can be manufactured by using only three mask processes, which can reduce the process cost and shorten the process time. In accordance with the purpose of the present invention, a thin film transistor substrate is provided comprising a substrate, an insulating layer, a pixel electrode, a conductive layer, and a thin film dielectric crystal. The insulating layer is disposed on the substrate. The halogen electrode and the conductive layer are disposed on the insulating layer spaced apart from each other. The thin film transistor is disposed on the substrate and includes a gate, a semiconductor layer, a gate and a source. The gate is disposed between the substrate and the insulating layer in a manner corresponding to the relationship between the halogen electrode and the conductive layer. The germanium semiconductor layer is disposed between the insulating layer, the germanium electrode and the conductive layer so as to correspond to the gate, and the two ends of the germanium semiconductor layer are in electrical contact with the first end of the germanium electrode and the conductive layer, respectively. The drain and the source are respectively disposed on the first end of the halogen electrode and the conductive layer in a manner corresponding to the two ends of the germanium semiconductor layer, respectively, and respectively pass through the first end of the halogen electrode and the conductive layer and the germanium semiconductor The two ends of the layer are in electrical contact. According to another object of the present invention, a method of manufacturing a thin film transistor substrate is proposed. First, a substrate is provided. Next, a first mask process is performed to form a gate over a substrate. Then, a second mask process is performed to form an insulating layer and a germanium layer over the substrate, the insulating layer covering the gate, and the germanium semiconductor layer covering a portion of the insulating layer in a manner corresponding to the gate. Then, a third mask process is performed to form a 汲 8 1331804

- Sanda number: TW2448PA - a pole, a source, a halogen electrode and a conductive layer on the insulating layer, one of the first ends of the halogen electrode and the conductive layer are spaced apart from each other and the two ends of the germanium semiconductor layer Electrical contact, the drain and the source respectively cover the first end of the halogen electrode and the conductive layer in a manner corresponding to the two ends of the germanium semiconductor layer, and the drain and the source respectively pass through the first end of the pixel electrode and the conductive layer and The two ends of the germanium semiconductor layer are in electrical contact. According to still another object of the present invention, a display panel comprising a substrate and a thin film transistor substrate disposed in parallel with each other is provided. The thin film transistor substrate φ plate comprises a substrate, an insulating layer, a halogen electrode, a conductive layer, and a thin film transistor. The insulating layer is disposed on the substrate. The halogen electrode and the conductive layer are disposed on the insulating layer spaced apart from each other. The thin film transistor is disposed on the substrate and includes a gate, a germanium semiconductor layer, a drain and a source. The gate is disposed between the substrate and the insulating layer in a manner corresponding to the pixel electrode and the conductive layer. The germanium semiconductor layer is disposed between the insulating layer, the halogen electrode and the conductive layer in a manner corresponding to the gate, and the two ends of the germanium semiconductor layer are in electrical contact with the first end of the germanium electrode and the conductive layer, respectively. The drain and the source are respectively disposed on the first end of the halogen electrode and the conductive layer in a manner corresponding to the two ends of the semiconductor layer, and respectively pass through the first end of the halogen electrode and the conductive layer and the germanium semiconductor layer The second end is electrically contacted. The above described objects, features, and advantages of the present invention will become more apparent from the description of the appended claims. 9 1331804

*3D: TW2448PA' [Embodiment] Please refer to FIG. 2A to FIG. 2B. FIG. 2A is a plan view showing the structure of a thin film transistor substrate according to a preferred embodiment of the present invention, and FIG. 2B is taken along A cross-sectional view of the structure of the thin film transistor substrate as viewed in section line 2b-2b' of Fig. 2A. Here, Fig. 2A omits the drawings and reference numerals of the protective layer 270. As shown in Figs. 2A to 2B, the thin film transistor substrate 300 includes a substrate 201, an insulating layer 220, a halogen electrode 280a, a conductive layer 280b, and a thin film transistor 250. The insulating layer 220 is disposed on the substrate 201. • The halogen electrode 280a and the conductive layer 280b are disposed above the insulating layer 220 spaced apart from each other. The thin film transistor 250 is disposed on the substrate 201 and includes a gate 210, a germanium semiconductor layer 235, a drain 265a and a source 265b. The gate 210 is provided between the substrate 201 and the insulating layer 220 so as to correspond to the space between the halogen electrode 280a and the conductive layer 280b. The germanium semiconductor layer 235 is disposed between the insulating layer 220, the germane electrode 280a and the conductive layer 280b corresponding to the gate 210, and the two ends of the germanium semiconductor layer 235 and the first end of the germane electrode 280a and the conductive layer respectively 280b electrical contact. The rake pole 265a and the source 265b are respectively disposed on the first end of the halogen electrode 280a and the conductive layer 280b in a manner corresponding to the two ends of the Shihua semiconductor layer 235, and respectively pass through the first end of the pixel electrode 280a. And the conductive layer 280b is in electrical contact with both ends of the germanium semiconductor layer 235. According to the present invention, the thin film transistor substrate 300 further includes a storage capacitor 214 having a first electrode 212 and a second electrode 213. The first electrode 212 is disposed between the substrate 201 and the insulating layer 220 in a manner spaced apart from the gate 210, and the second electrode 213 is a halogen electrode 1331804.

- Sanda number: TW2448PA 'One of the second ends of 280a. In addition, the thin film transistor substrate 300 also includes a protective layer 270 ′ disposed on the insulating layer 220 for covering the germanium semiconductor layer 235, the drain 265a, the source 265b, the first end of the pixel electrode 280a, and the conductive layer 280b. And the exposed portion of the pixel electrode 280a. Furthermore, the thin film transistor substrate 300 further includes a doped N-type (N+) semiconductor layer 246 disposed between the two ends of the germanium semiconductor layer 235, the first end of the pixel electrode 280a, and the conductive layer 280b. However, the materials of the first electrode 212 and the gate 210 of the storage capacitor 214 may be the same or different, and the materials of the halogen electrode 280a and the conductive layer 280b may be the same or different. In this embodiment, the material of the first electrode 212 and the gate 210 is a metal or a metal alloy such as a metal such as a metal such as Ming, Key, Copper, Co., or Chin, or an alloy thereof, and a halogen electrode 280a and a conductive layer 280b. The material is a transparent conductive oxide (TC0) such as indium tin oxide (ITO), indium zinc oxide (IZ0) or the like. The thin film transistor substrate 300 further includes a plurality of scan lines SL and a plurality of data lines DL. The scan lines SL and the data lines DL are disposed on the substrate 201. The adjacent two parallel scan lines sl and the adjacent two parallel data lines DL are alternately defined as a pixel. The thin film transistor 25A, the pixel electrode 280a and the storage capacitor 214 are disposed in the pixel, the source 265b of the thin film transistor 250 is coupled to the data line DL, and the gate 210 of the thin film transistor 250 is a portion of the scan line SL. structure. Therefore, Figure 2A only shows a partial area of the alizarin. Furthermore, the thin film transistor substrate 3 further includes a plurality of common electrode lines CL, and the common electrode line C]L is parallel to the scanning line S]L and 1331804

- Sanda number: TW2448PA • Staggered. The first electrode 212 of the storage capacitor 214 is a part of one of the common electrode lines CL. The area where the pixel electrode 280a overlaps the common electrode line CL is the second electrode 213 of the storage capacitor 214. That is, a region where the halogen electrode 280a and the common electrode line CL overlap each other forms a storage capacitor 214. The method of manufacturing the thin film transistor substrate of the present embodiment will be described below by way of example, but the technique of the present embodiment is not limited to this. Referring to Figure 3, there is shown a flow chart of a method of fabricating a thin film transistor substrate in accordance with a preferred embodiment of the present invention. First, the substrate 201 is provided in step 301. Next, proceeding to step 302, a first mask process is performed to form the gate 210 over the substrate 201. Then, in step 303, a second mask is formed to form the insulating layer 220 and the broken semiconductor layer 235 over the substrate 201. The insulating layer 220 covers the gate 21A, and the germanium semiconductor layer 235 covers the insulating layer 220 of the portion corresponding to the gate 21〇.

Finally, in step 304, a third mask process is performed to form the drain 265a, the source 265b, the halogen electrode 28A and the conductive layer 28 on the insulating layer 220, and the first electrode of the halogen electrode 280a Step B = 缒 and conductive layer 280b

The two ends 4α A ^ % of the germanium semiconductor layer 235 are electrically connected to each other, and the drain electrodes 5a and 265b respectively correspond to the first layer of the germane electrode 280a and are electrically conductive. For the Λ and source 265b, respectively, through the halogen electrode 28〇a, the second pole 28〇b is electrically contacted with the two ends of the germanium semiconductor layer 235. The end and the guiding layer 12 1331804

- Sanda number: TW2448PA - The film transistor substrate 300 has been completed so far. However, the detailed description of how to perform the mask process in each step is as follows. However, the technique of this embodiment is not limited thereto. Referring to Figure 4-8, a process cross-sectional view of a thin film transistor substrate in accordance with a preferred embodiment of the present invention is shown. The first mask process in step 302 further includes the following sub-step. As shown in FIG. 4A, the gate 21A and the first electrode 212 are formed on the substrate 2〇1, and the gate 210 and the first electrode 212 are spaced apart from each other. In step 3〇2, the scan line SL and the common electrode line CL of FIG. 2A can be formed on the substrate 201, and the gate 210 and the first electrode 212 are respectively the scan line SL and the common electrode line CL of FIG. Part of the structure. The second mask process in step 303 further includes the following sub-steps. First, as shown in FIG. 4B, the insulating layer 220, the germanium semiconductor material layer 230, the doped N-type material layer 24, and the first patterned photoresist layer PR1 are sequentially formed on the substrate 2〇1. . The insulating layer 220 covers the gate 210 and the first electrode 212'. The semiconductor material layer 230 covers the insulating layer 220. The N+ material layer 240 covers the germanium semiconductor material layer 230, and the first patterned photoresist layer PR1 covers the N+ material layer 240. The first patterned photoresist layer PR1 has a first thick region PR1a and a first thin region PRib, and the first thick region PRia corresponds to the gate 210. In the present embodiment, the first patterned photoresist layer PR1 covers the N+ material layer 240 by exposing a first photoresist layer having a uniform thickness to a first half-tone mask. Wherein, the germanium semiconductor material layer 230 may be amorphous or polycrystalline. Then, as shown in FIG. 4C, the first thin region PRib and the thinned 13 1331804 are removed.

Sanda number: TW2448PA A thick area PRla is a second thin area PRlc. The second thin region pRlc is a portion of the exposed N+ material layer 240. Here, the thickness of one of the first patterned photoresist layers PR1 can be uniformly thinned by etching the gas in an oxygen (?2) ashing manner. Then, as shown in Fig. 4D, a portion of the germanium semiconductor material layer 230 and the N+ material layer 24 are removed to form a germanium semiconductor layer 235 and a patterned N+ material layer 245. Here, a portion of the germanium semiconductor material layer 23 and the N+ material layer 240 may be sequentially removed or simultaneously removed by etching. • Next, as shown in Fig. 4E, the second thin region pRiy is removed, and the second thin region PRlc can be removed through a stripper. The third mask process in step 304 further includes the following sub-steps. First, as shown in FIG. 4F, a first conductive material layer 280, a second conductive material layer 260, and a second patterned photoresist layer PR2 are sequentially formed on the insulating layer 220, and the first conductive material layer is formed. 280 covers the germanium semiconductor layer 235 and the patterned N+ material layer 245. The second conductive material layer 260 covers the first conductive material layer 280, and the second patterned photoresist layer PR2 covers the second conductive material layer 260. The second patterned photoresist layer PR2 has a second thick region PR2a, a third thin region PR2b, and an opening PR2o. The second thick region PR2a corresponds to two ends of the germanium semiconductor layer 235, and the opening PR2o corresponds to the germanium semiconductor layer 235. Central. In this embodiment, the second patterned photoresist layer PR2 covers a portion of the second conductive material layer 260 by exposing a second photoresist layer having a uniform thickness to the second gray scale mask. Next, as shown in Fig. 4G, a portion of the second conductive material layer 260' is removed to form a patterned conductive material layer 265. Here, it can be etched 1331804

* Sanda number: TW2448PA. A portion of the second conductive material layer 260 is removed in an engraved manner, wherein the second conductive material layer 260 may be a metal material such as aluminum, molybdenum, steel, road, titanium or the like and alloys thereof. Then, as shown in Fig. 4H, a portion of the first conductive material layer 280' is removed to form the halogen electrode 280a and the conductive layer 280b. The material of the halogen electrode 280a and the conductive layer 280b is the same, for example, a transparent conductive material (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like. . • The second end of the halogen electrode 280a is the second electrode 213, and the first electrode 212 and the second electrode 213 constitute a storage capacitor 214. Here, a portion of the first conductive material layer 280 can be removed by a surname. Next, as shown in Fig. 41, a portion of the patterned material layer 245' is removed to form an N+ semiconductor layer 246. Here, a portion of the patterned N+ material layer 245 can be removed by a surname. Then, as shown in Fig. 4J, the third thin region PR2b and the thinned second thick region PR2a are removed as a fourth thin region PR2c. The fourth thin region PR2c exposes the patterned conductive material layer 265 of the reference portion. Here, a thickness of the second patterned photoresist layer PR2 can be uniformly thinned by etching gas oxygen (〇2) ashing. Next, as shown in Fig. 4K, a portion of the patterned conductive material layer 265 is removed to form the drain 265a and the source 265b. Further, the data line DL of Fig. 2A is formed therein, and the gate electrode 210, the germanium semiconductor layer 235, the drain electrode 265a, and the source electrode 265b constitute a thin film transistor 250. Here, a portion of the patterned conductive material layer 265 can be removed by etching. 15 1331804

'Three-face number·· TW2448PA • Then' As shown in Fig. 4L, the fourth thin region PR2C is removed. Here, the fourth thin region PR2C can be removed by the stripper. In addition, as shown in FIG. 4L, after the third mask process, a laser patterning process can be performed to form the protective layer 27 or the gate 201, the gate 265a and the source 265b are used from the substrate 201. The back side performs a back mask process to form a protective layer 270. The protective layer 270 is used to cover the germanium semiconductor layer 235, the drain 265a, the source 26%, the first end of the halogen electrode 280a, and the conductive layer 280b ° or perform a fourth mask after the third mask process. 'To form a protective layer 270. However, those skilled in the art to which the present invention pertains can also be understood that the technology of the present embodiment is not limited thereto. For example, in the second mask process, as shown in Fig. 4B, the first photoresist layer is exposed by the first gray scale mask such that the first patterned photoresist layer pR1 has another opening. The other opening corresponds to the scanning line SL outside the display area, and exposes a portion (Ν+ material layer 240. Then, before the 4th C picture, a portion of the n+ material layer 240, the germanium semiconductor material layer 23, and the insulating layer are sequentially removed. Another contact hole is formed, for example, by a surname. This contact hole exposes the scanning line SL outside the display area of the portion. Then, as shown in Fig. 4C, the first, thin region PRlb is removed. Next, as shown in the milk map, a portion of the N+ material layer 240 and the germanium semiconductor material layer 23 are removed outside the display area. The fourth electrode is formed into a 4H-thick pixel electrode 28〇a and electrically conductive. Layer 28卟> If the material of the first conductive material layer 280 is IT〇, the display area outer line SL can be in electrical contact with the other contact hole through the other contact hole. The field idler 210 can pass through the scan line S1. And ΙΤ0 and outside drive Christine = this, 16 1331804

- Sanda number: TW2448PA - Connection. It should be noted that the above-described step of forming another contact hole outside the display area can be elastically adjusted. First, a portion of the N+ material layer 24 and the germanium semiconductor material layer 230 are removed to form another contact hole front body. Next, the first thin region PRlb is removed to expose the material layer 240. Then, a portion of the insulating layer 220 is removed to form another contact hole. Here, another contact is formed by etching the insulating layer 220 and the N+ material layer 240 is not easily etched. Please refer to FIG. 5, which is illustrated in accordance with the present invention. A schematic view of a display panel of a preferred embodiment of the invention. In Fig. 5, the display panel 500 includes a substrate 501 and the above-described thin film transistor substrate 300. The thin film transistor substrate 300 is disposed in parallel with the substrate 501. The display panel 500 may be an organic light emitting diode (OLED) display panel or a liquid crystal display panel. When the display panel 500 is a liquid crystal display panel, the display panel 500 further includes a liquid crystal layer 502 disposed between the substrate 501 and the thin film TFT substrate 300. The substrate 501 may be a color filter substrate. In addition, the display panel 500 can be disposed between a first polarizing plate and a second polarizing plate, and the first polarizing plate and the second polarizing plate abut the thin film transistor substrate 300 and the substrate 501, respectively. The light of the first polarizing plate and the second polarizing plate - the direction of the transmission axis are perpendicular to each other. In addition, the first polarizing plate can be adjacent to a backlight module, and the first polarizing plate is disposed between the display panel 300 and the backlight module, and the display panel 500 and the backlight module sandwich the first polarizing plate. Therefore, the backlight module, the first polarizing plate, the second polarizing plate, and the display panel 5〇〇 constitute 17 1331804

- Sanda number: TW2448PA - A liquid crystal display device. If the display panel 500 is an organic light emitting diode display panel, an anode, an organic light emitting material layer and a cathode may be sequentially disposed on the thin film transistor substrate 501. The novel thin film transistor substrate and the method of manufacturing the same disclosed in the above embodiments of the present invention are applied to the display panel of the conventional thin film transistor substrate. The thin film transistor substrate of this embodiment can be manufactured by using only three mask processes, which can reduce the process cost and shorten the process time. In view of the above, the present invention has been disclosed in a preferred embodiment, and is not intended to limit the present invention. Any changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

18 1331804

- Sanda Number: TW2448PA - [Simplified Schematic Description] FIGS. 1A to 1E are schematic cross-sectional views showing a conventional thin film transistor substrate; FIG. 2A is a view showing a thin film transistor according to a preferred embodiment of the present invention. A top view of the structure of the substrate; FIG. 2B is a cross-sectional view showing the structure of the thin film transistor substrate taken along line 2b-2b' of FIG. 2A, and FIG. 3 is a view of a preferred embodiment of the present invention. A flow chart of a method of manufacturing a thin film transistor φ substrate; FIGS. 4A to 4L are cross-sectional views showing a process of a thin film transistor substrate according to a preferred embodiment of the present invention; and FIG. 5 is a view showing a comparison according to the present invention. A schematic diagram of a display panel of a preferred embodiment.

19 1331804

- Sanda number: TW2448PA - [Description of main component symbols] 100: Glass substrate 110, 210: Gate 120: Gate insulating layer 130: Amorphous germanium semiconductor layer 140, 246: N+ semiconductor layer 150, 250: Thin film Crystal 160, 265a: drain 10 165, 265b: source 170, 270: protective layer 171: contact hole 180: indium tin oxide oxide electrode 200, 300: thin film transistor substrate 201: substrate 212: first electrode 213: second electrode • 214: storage capacitor 220: insulating layer 230: germanium semiconductor material layer 235: germanium semiconductor layer 240: N+ material layer 245: patterned N+ material layer 260: second conductive material layer 265: patterned conductive material Layer 20 1331804

... Sanda number: TW2448PA - 280: First conductive material layer 280a: Alizarin electrode 280b: Conductive layer 500: Display panel 501: Substrate 502: Liquid crystal layer CL: Electrode line PR1: First patterned photoresist layer • PRla: First thick region PRlb: first thin region PRlc: second thin region PR2 · second patterned photoresist layer PR2a: second thick region PR2b: third thin region PR2c: fourth thin region PR2o: opening • SL: Scan line DL: data line 21

Claims (1)

1331804 . Sanda number: TW2448PA. X. Patent application scope: 1. A thin film transistor substrate, comprising: a substrate; an insulating layer disposed on the substrate; a pixel electrode and a conductive layer, mutual Separatingly disposed on the insulating layer; and a thin film transistor disposed on the substrate, and comprising: a gate disposed between the substrate and the insulating layer; a semiconductor layer to Corresponding to the gate is disposed between the Φ insulating layer, the halogen electrode and the conductive layer; and a drain and a source are respectively disposed in a manner corresponding to the two ends of the germanium semiconductor layer The first end of the halogen electrode and the conductive layer are respectively electrically connected to the first end of the halogen electrode and the conductive layer to the two ends of the germanium semiconductor layer. 2. The thin film transistor substrate according to claim 1, wherein the halogen electrode and the conductive layer are made of the same material. 3. The thin film transistor substrate according to claim 1, wherein the halogen electrode and the conductive layer are made of a transparent conductive material. 4. The thin film transistor substrate of claim 1, further comprising: a storage capacitor disposed on the substrate and having a first electrode and a second electrode, the first electrode The gates are disposed between the substrate and the insulating layer in a spaced apart manner, and the second electrode is a second end of the halogen electrode. The thin film transistor substrate of claim 4, wherein the first electrode and the gate are made of the same or different materials. 6. The thin film transistor substrate of claim 4, wherein the first electrode and the gate are made of a metal or a metal alloy. 7. The thin film transistor substrate of claim 1, further comprising: a passivation layer disposed over the insulating layer to cover the germanium semiconductor layer, the drain, the source a pole, the second end of the halogen electrode, the first end and the conductive layer. 8. The thin film transistor substrate of claim 1, further comprising: a doped N-type (N+) semiconductor layer disposed on the two ends of the germanium semiconductor layer, the first of the germanium electrodes Between the end and the conductive layer. 9. A method of fabricating a thin film transistor substrate, comprising: providing a substrate; performing a first mask process to form a gate on the substrate; performing a second mask process to form An insulating layer and a semiconductor layer over the substrate, the insulating layer covering the gate, the germanium semiconductor layer covering the insulating layer in a manner corresponding to the gate; and performing a third mask process Forming a germanium, a source, a germanium electrode, and a conductive layer over the insulating layer. The drain and the source respectively cover the pixel in a manner corresponding to the two ends of the germanium semiconductor layer The first end of the electrode and the conductive layer, the drain and the source respectively pass through the picture 23 1331804 * three number: TW2448PA. The first end of the element electrode and the conductive layer and the second layer of the germanium semiconductor layer Electrical contact at the end. 10. The manufacturing method according to claim 9, wherein the halogen electrode and the conductive layer are made of the same or different materials. 11. The manufacturing method according to claim 9, wherein the halogen electrode and the conductive layer are made of a transparent conductive material. 12. The manufacturing method of claim 9, wherein the step of performing the first mask process further comprises: φ forming a first electrode and the gate on the substrate, the first The electrodes are spaced apart from the gate. 13. The method according to claim 12, wherein the first electrode and the gate are made of the same or different materials. 14. The manufacturing method according to claim 12, wherein the first electrode and the gate are made of a metal or a metal alloy. 15. The manufacturing method of claim 12, wherein the step of performing the second mask process further comprises: φ sequentially forming an insulating layer, a germanium semiconductor material layer, and a doped N-type (N+) a material layer and a first patterned photoresist layer over the substrate, the insulating layer covering the gate and the first electrode, the N+ material layer covering the layer of the semiconductor material, the first patterning The photoresist layer covers the N+ material layer, the first patterned photoresist layer has a first thick region and a first thin region, the first thick region corresponding to the gate; removing the first thin region and thinning The first thick region is a second thin region; the portion of the germanium semiconductor material layer and the N+ material layer are removed to form 24 1331804 - Sanda number: TW2448PA • into the Si Xi semiconductor layer and a patterned N+ material layer And removing the second thin zone. 16. The manufacturing method of claim 15, wherein the step of performing the third mask process further comprises: forming a first conductive material layer, a second conductive material layer, and a second patterning a photoresist layer over the insulating layer, the first conductive material layer covering the germanium semiconductor layer and the patterned N+ material layer, the second conductive material covering the first conductive material layer, the second patterned photoresist The layer covers a portion of the first: conductive material layer, the second patterned photoresist layer has a second thick region, two third thin regions, and an opening corresponding to the second end of the germanium semiconductor layer The opening corresponds to the center of the germanium semiconductor layer; the portion of the second conductive material layer is removed to form a patterned conductive layer; the portion of the first conductive layer is removed, the electrode of the pixel electrode and The second electrode constitutes a removed portion of the patterned layer; a layer of electrical material to form the halogen electrode and - the second end is a second electrode, the first storage capacitor; the N + material layer to form an N + semiconductor stone 颂 颂 , , , , , m 守守 / brother a thick area is the 〆笫 four 浔 area, the source; and μ θ /, a layer of conductive material to form the drain and the removal of the fourth thin area. The manufacturing method of claim 9, further comprising: overlying the insulating layer to cover the germanium semiconductor 25 1331804 - three-number: TW2448PA, layer, the drain, the source, the germanium electrode The first end and the conductive layer. 18. The method of claim 17, wherein the forming the protective layer further comprises: performing a fourth mask process to form the protective layer. 19. The method of claim 17, wherein the forming the protective layer further comprises: performing a back light from the back side of the substrate by using the gate, the drain, and the source A mask process is performed to form the protective layer. The manufacturing method of claim 17, wherein the forming the protective layer further comprises: performing a laser patterning process to form the protective layer. 21. A display panel comprising: a substrate; and a thin film transistor substrate disposed parallel to the substrate and comprising: a substrate; an insulating layer disposed on the substrate; • a halogen electrode and a conductive layer disposed on the insulating layer spaced apart from each other; and a thin film transistor disposed on the substrate and comprising: - a gate * disposed between the substrate and the insulating layer; a germanium semiconductor layer disposed between the insulating layer, the germane electrode and the conductive layer, and a drain and a source corresponding to the gate, to correspond to the two ends of the germanium semiconductor layer And respectively disposed on the first end of the halogen electrode and the lead 26 1331804. No. 3: TW2448PA. Above the electric layer, respectively passing the first end of the halogen electrode and the conductive layer and the germanium semiconductor layer The two ends are in electrical contact. 22. The display panel of claim 21, wherein the halogen electrode and the conductive layer are made of the same or different materials. 23. The display panel of claim 21, wherein the halogen electrode and the conductive layer are made of a transparent conductive material. The display panel of claim 21, wherein the thin film transistor substrate further comprises: a storage capacitor disposed on the substrate and having a first electrode ring and a second electrode, The first electrode is disposed between the substrate and the insulating layer in a manner spaced apart from the gate, and the second electrode is a second end of the halogen electrode. 25. The display panel of claim 24, wherein the first electrode and the gate are made of the same or different materials. 26. The display panel of claim 24, wherein the first electrode and the gate are made of a metal or a metal alloy. The display panel of claim 21, wherein the thin film transistor substrate further comprises: a passivation layer disposed on the insulating layer to cover the emitting semiconductor layer, 〉 and the pole, the source, the first end of the halogen electrode and the conductive layer. The display panel of claim 21, wherein the thin film transistor substrate further comprises: a doped N-type (N+) semiconductor layer disposed on the germanium semiconductor layer 27 1331804 - Sanda number: TW2448PA. The two ends, between the first end of the halogen electrode and the conductive layer. 29. The display panel of claim 21, further comprising: a liquid crystal layer disposed between the substrate and the thin film transistor substrate. 30. The display panel of claim 29, wherein the substrate is a color filter substrate. 31. The display panel of claim 29, disposed between a first polarizing plate and a second polarizing plate, and sandwiching a first polarizing plate with a backlight module, wherein the thin film is electrically The crystal substrate is adjacent to the first polarizing plate. The display panel of claim 31, wherein the first polarizing plate and the second polarizing plate have a light transmission axis direction perpendicular to each other. 33. The display panel of claim 21, which is an organic light emitting diode (OLED) display panel. 28