TWI329994B - Delay line and delay lock loop - Google Patents

Description

1329994 IX. Description of the Invention: [Technical Field] The present invention relates to a Delay Lock Loop (DLL), and more particularly to a delay lock loop having a low power consumption delay line. [Prior Art] In recent years, the speed and performance of Very Large Scale Integrated Circuits (VLSI) are increasing, and the reference clock signals required for each integrated circuit are becoming higher and higher. Circuit designers have focused on high-speed digital circuit design to suppress clock skew and clock jitter. Therefore, Delay Lock Loop (DLL) and Phase Locked Loop (PLL) are widely used in high-speed digital circuits, such as microprocessors and memory interfaces. , communication integrated circuit chip (communication 1C). Among them, the delay-locked loop is widely used in clock error correction because of the ease of design and stability of the delay-locked loop. However, wafers have evolved toward a highly integrated and high-speed operation, so wafers are becoming more and more energy intensive, and it is increasingly important to reduce the energy consumption of various circuit components within the wafer. SUMMARY OF THE INVENTION In view of the above, the present invention provides a delay line including a decoder, a first delay matrix, a second delay matrix, and a multiplexer. Decoder reception

Client’s Docket No.: VIC06-0028 TT*s Docket No: 0608-A41006TWfiDavidChen/2007/02/02 - Control signal to generate delay control, 垆 ^ signal. The first delay matrix is connected to the source control signal and the selection wheel and controls the clock signal according to the delay and the delay control signal. The second delay matrix is connected to output the first-delay matrix matrix clock signal and the delay control signal, and the second delay matrix is turned on according to the power control signal or the delay matrix is based on the delay ^2, and the array is in the startup state, the _r First, =:=; = pulse signal: say, the first delay matrix ° receive k select the round control message according to the selected output control; two delay matrix clock signal, and delay the matrix clock signal to: the first delay: Pulse signal or second first =: more;:::1 late phase-locked loop, delay-locked loop includes and counting control _ i inverting 11, phase (four) (four), divider number to generate a first control signal delay one clock The signal-delay signal produces a two-degree delay of 180 degrees to produce an inverse two-delay = 夂 phase 仏唬. The phase detector compares the phases of the second delay and the inverted L number to produce a phase control signal. The counting controller receives the phase control signal to generate a control signal to cause the second delayed signal and the inverted === division 11 to divide the clock signal to generate a reference clock signal. [Embodiment] To make the above and other aspects of the present invention The objects, features, and advantages will be more apparent and understood. The preferred embodiments are described below, and in conjunction with the drawings,

Client's Docket No·: VIC06-0028 TTs Docket No: 〇6〇8-A41〇〇6TW£a)avidChen/2007/02/02 The following is a detailed description: Figure 1 shows the delay phase lock according to an embodiment of the present invention. Loop 100. The delay phase locked loop 100 includes a first delay line 110, a second delay line 1 two phase detector 13A, a count controller 14A, an inverter 15A, a divider 160, and a multiplexer $17. The multiplexer 17 receives the two clock signals CLK1 and CLK2' and determines one of the output clock signals CLK1 and CLK2 according to the control signal 172 to the inverter 15 〇, the divider 16 〇 and the first delay line U 。. The following takes the multiplexer 17〇 output clock signal CLK1 as an example, the inverter 150 inverts the clock signal CLK1 18〇 to output the inverted signal REVCLK to the phase detector 13〇β first delay line 11〇 according to The control signal CNT delays the clock signal CLK1 by a delay time to output the delay signal CLK3 to the second delay line 12A. Similarly, the second delay line 12 延迟 delays the delay signal CLK3 according to the control finger CNT for a delay time to output the delay signal FBCLK to the phase detector 13 〇, so the phase difference between the delay signal FBCLK and the clock heart number CLK1 is 180 degrees. . The phase detector 130 compares the phases of the delay signal FBCLK and the inverted signal REVCLK. In addition, the divider 160 divides the clock signal CLK1 by a value (e.g., 4) to generate the reference clock signal CLKR to the counter controller 14 as the reference clock of the count controller 140. When the phase of the delay signal FBCLK leads the phase of the inverted signal REVCLK 'that is, when the delay signal FBCLK is faster than the inverted signal REVCLK', the phase detector 130 outputs the phase control signal up to 1, and the counting controller 140 increases the meter. Value (n=n+i). Therefore, when the count value of the counter controller 140 increases, the first delay line 110 and the second delay line

Client's Docket No.: VIC06-0028 TT5s Docket No: 0608-A41006TWfiDavidChen/2007/02/02 8 1329994 120 will increase the delay time to delay the clock signal clKI to make the phase of the delayed signal FBCLK and the phase of the inverted signal reVCLK consistent . When the phase of the delay signal FBCLK falls behind the phase of the inverted signal REVCLK, that is, when the delay signal FBCLK is slower than the inverted signal REVCLK, the phase detector 130 outputs the phase control signal Up, and the counting controller 140 reduces the meter. Value ^ Therefore, when the count value of the count controller 140 is decreased, the first delay line u 〇 and the second delay line 12 〇 reduce the delay time to delay the clock signal CLK1 to make the phase of the delay signal FBCLK and the inverted signal REVCLK The phases tend to be consistent. Finally, the delay phase-locked loop 100 reaches a stable state, and the phase of the delay signal FBCLK and the phase of the inverted signal REVCLK are the same, wherein the first delay line 110 and the second delay line 12 each produce a phase difference of 90 degrees. 2 shows a delay line 2 包括 according to another embodiment of the present invention. The delay line 200 includes a decoder 250, a first delay matrix 210, a second delay matrix 220, a third delay matrix 230, and a fourth delay matrix 240. And multiplexer 260. According to an embodiment of the invention, the delay line 2A may be the first delay line 110 or the second delay line 12A of FIG. In addition, the delay line 2〇〇 is not limited to four delay matrices, and the delay line 2〇〇 may be composed of one or more delay matrices. The following description is to describe the delay line 200 as the first delay line no, and the multiplexer 170 outputs the clock signal CLK1 as an example. The first delay line Π0 delays the clock signal CLK1 by a delay time according to the control signal Cnt, and according to The power control signal PDB determines whether to turn on or off the second delay matrix 220, the third delay matrix 230, and the fourth delay matrix 240 to reduce

Client’s Docket No.: VIC06-0028 TT's Docket No: 0608-A41006TWfiDavidChen/2007/02/02 1329994 Less power consumption. The SFT solution 250 丄 receives the control signal CNT to generate a delay control signal (4) the source control, the number ΡΜ and the selection output control signal DEC. The first-signal CLK1 delays the clock by the output of a == SEL. The first delayed matrix clock signal CLKal is supplied to the multiplexer 260 and the second delay matrix 22π. First, the control PDB, the flute, and the second delay matrix 220 receive power. ~ Delay matrix clock signal CLKal and delay control signal SEL, and the second syndrome is delayed. The old M ^ delay matrix 220 is based on the power control signal PDb, the second delay of the stomach (10) is the startup delay matrix 220 according to the delay control, the signal cxKal _" delays the _delay matrix clock (9) delay matrix clock signal CLKa2 to the pirate 260 And the third delay matrix 23 controls the signal, the second delay two, the (four) matrix 23G receives the power signal SEL, and the third delay == number 2 * delay control is turned off or on. When the third delay moment according to the power control signal delay matrix 230 according to the delay control 俨,,,, the start state, the second delay signal CLKa2 to output the second delay matrix delay clock w4 late matrix clock signal CLKa3 At most 370 and fourth delay matrix 24 less control signal PDB, third delay car: delay matrix 240 receives power signal SEL, and fourth delay pulse signal (10) 3 and delay control

M pa . ^wood error delay matrix 240 according to the power control signal PDB η 夕 四 delay matrix (10) is the start state, the fourth extension

Delay matrix 240 series delay __SEL signal CLKa3 read W call late matrix clock (4)

Client’s Docket No.: VIC06-0028 TT's Docket No: 0608-A41006TWfirDavidChen/2〇〇7/〇2/〇2 1329994 260. The multiplexer 260 selects one of the first delay matrix clock signal CLKal, the second delay matrix clock signal CLKa2, the third delay matrix clock signal CLKa3, or the fourth delay matrix clock signal CLKa4 according to the selection rounding control signal DEC. To the clock output CLKOUT. Since the second delay line 120 works in the same manner as the first delay line 11〇, it will not be described here.

Fig. 3 shows a delay matrix 210 according to another embodiment of the present invention. The delay matrix 210 includes eight delay devices 211 to 218 and eight switches SE0 to SE7. As shown in FIG. 3, the delay matrix 210 receives the clock signal CLK1 or CLK2 from the clock receiving terminal 219, and turns on one of the eight switches SE0 to SE7 according to the delay control signal SEL to control the delayed clock signal CLK1 or CLK2. The delay time is to output a first delay matrix clock signal CLKal, wherein each of the delay devices 211 218 218 is delayed by an equal delay unit time. Additionally, delay matrix 210 is not limited to eight delay devices, and delay matrix 210 may be comprised of one or more delay devices. 4 is a diagram showing a delay matrix 400 according to another embodiment of the present invention. The delay matrix can be applied to the second delay matrix 220 of FIG. 2, the third delay moment $230, and the fourth delay matrix 24A. The delay matrix 働 includes a receiving end 411, an output terminal 412, eight delay devices, and a Z switch SW0 to SW7. As shown in FIG. 4, the delay matrix is used as the second delay matrix 220 as an example. The delay moment number is received, and the first signal and the reception delay control signal SEL are received from the receiving end 411, and according to the electric pulse 5#υ CLKal burst power control signal PDB is off

Client's Docket No.: VIC06-0028 TT's Docket No: 〇6〇8-A41〇〇6TWf/DavidChen/2007/〇2/〇2 11 < S ) 丄j ay 94 or start delay attack 4〇1~4 〇 8. When the delay devices 408 of the delay matrix 4 are in an active state, each of the delay devices 4〇1 to 4〇8 delays the delay time of the first delay matrix clock signal CLKal_, respectively, and the delay matrix shed is turned on according to the delay control signal SEL. The eight switches SW0 to SW7 are controlled to delay the delay time of the first-delay matrix clock signal 1 CLKal to be output to the output terminal 412. The delay line 2〇〇 of the delay phase-locked loop of the present invention determines the delay clock signal by a delay time according to the control_仏唬CNT, and the decoder 250 of the delay line 2〇〇 generates a corresponding signal according to the control signal CNT. The power control signal PDB turns off the unused delay matrix (eg, the second delay matrix of FIG. 2, the second delay matrix, and the fourth delay matrix) to reduce unnecessary power consumption, thereby achieving a reduced delay phase-locked loop 1〇〇 power consumption. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a delay phase locked loop according to an embodiment of the present invention; FIG. 2 is a diagram showing a delay line according to another embodiment of the present invention; and FIG. 3 is a diagram showing another embodiment according to the present invention. The delay matrix of the example; and the fourth figure shows a delay matrix according to another embodiment of the present invention. [Main component symbol description] 100: Delayed phase-locked loop

Client's Docket No.: VIC06-0028 TT's Docket No: 〇6〇8-A41006TWfmavidChen/2007/〇2/02 12 1329994

210, 220, 230, 240: delay matrix 211~218, 401~408: delay device 219: clock receiver 250: decoder 260: multiplexer 411: receiver 412: output

110: First delay line 120: Second delay line 130: Phase detector 140: Counting controller 150: Inverter 160: Divider 170: Multiplexer 172: Control signal 200: Delay lines CLKal, CLKa2, CLKa3 CLKa4: Delay matrix clock signal CLK1, CLK2: B pulse signal CLK3: Delay signal CLKR: Reference time 腋 signal CLKOUT: Clock output terminal CNT: Control signal DEC: Select output control signal FBCLK: Delay signal

Client's Docket No.: VIC06-0028

13 ( S TT's Docket No: 0608-A41006TW£/DavidChen/2007/02/02 1329994

REVCLK : Inverted signal PDB : Power control signal SEO ~ SE7, SWO ~ SW7 : Switch SEL : Delay control signal up : Phase control signal

Client's Docket No.: VIC06-0028 TTss Docket No: 0608-A41006TWfiT)avidChen/2007/02/02

Claims (1)

X. The scope of application for patents······················································································· a first-expansion land* first-delay matrix' receives the above-mentioned power supply control, upper, and f筮 matrix clock signals and the above-described delay control H, the above-mentioned first delay, or the above-mentioned fourth (four): hitting, and according to the above power control In the signal state, the above delay 矩阵 Μ 田 田 田 田 上 上 上 上 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 这 第一 第一 第一 第一 第一 第一 第一 第一a signal; and an array clock signal and the second delay 1 described first delay moment control money _ loading the above selection of the output matrix clock signal to output - the first delay delay =; ^ money the second delay delay The above-mentioned first-delaying complex-delay device, the first delay matrix of the first delay matrix is delayed by the clock signal to output the third delay matrix as described in the application specification - the first delay device and - the first Delay: set: = first; the pulse signal is delayed by one unit time to generate two, and the above-mentioned first-delay clock signal is transmitted to the second delay loading Client's Docket No: VIC06-0028 TT's D〇eket Nt): _- A side 6TWDavidche〇/2__2 15 (the s-bit delay t device delays the above-mentioned first delayed clock signal to delay the single top to generate a second delayed clock signal. Xiongping 4. As described in claim 3, «Up_late (four) signal output on === or on the second ^ as the second delay main clock signal to the above multiplexer and the above-mentioned ^ tiger switch and a -" gate HI item 4 delay The line ' further includes a first said second open said first switch or a second delayed time clock., (late clock signal or the above-mentioned certificate, the delay line described in the first paragraph of the patent scope of the claim 4 , wherein the upper-sense-l delay matrix comprises a complex delay device of _, and the above-mentioned second delay matrix is in the L-moving state; the == matrix is a delay signal for delaying the delay-control matrix of the first-delay matrix Clock signal. Don't give the above delay. 7. Delay as described in the cap patent scope! The delay matrix includes a third delay device and a fourth delay. When the delay matrix is in an inductive state, the third delay is set to delay the first-matrix clock money-(four) single 4 first delay transmission The third delayed clock signal is to the fourth time hard number, and the delay unit of the third delayed clock signal is delayed by a fourth delayed clock signal. [^] 8 is generated as the full-time g item 7 In the delay line, when the two delay matrix is in the startup state, the second delay matrix outputs the third delayed clock signal or the late delayed pulse signal according to the second signal = Client's Docket No.: VIC06-0028 TT's Docket No·· 0608-A41006TWei) avidChen/2007/02/02 To the above multiplexer. A delay-locked loop, comprising: a first delay line, delaying a clock signal according to a control signal to generate a first delay signal; and a second delay line delaying the first delay signal according to the control signal to generate a second delay signal; an inverter, inverting the clock signal 18 degrees to generate a Phase _|| 'Compare the phase of the second delay signal and the inverse tree to generate a phase control signal; - the juice number controller 'receives the phase control signal number to make the second delay money and the inverse complement phase And a divider for dividing the clock signal to generate the counting controller; wherein the first delay line comprises: a reference clock signal - decoding 11 'receiving the control signal to generate - delay control to break, - Power control number and - select output control Weng; ° God I late 'Wei Shang material pulse signal and the above delay control butterfly slightly · " age - output a delay matrix clock signal; 』Shan Le - - The second delay matrix 'receives the above-mentioned power supply control, Μ, 启动, +·, +- β field, the first delay matrix described above -: late moment:. The ί second delay matrix delays the material matrix clock signal according to the delay control signal to output a second delay matrix. . _2 17 CS; and the late matrix clock selection control signal, the above-mentioned first-selection round-off control signal selects the upper matrix clock signal' and according to the above-mentioned selection of the 'transferred material pulse record or the second-front利:: The delay phase-locked loop described in item 9, further comprising: a signal or a second J2 7-wheel control signal reception-first clock • & signal. The first-delay matrix includes a ==== phase-locked loop, wherein the first delay is passed through the first delay device, the delay signal is transmitted, and the delay time unit is transmitted to generate a delay line. The second delay line delay=^delays the clock signal to the second extension time to generate a second delay clock money: delaying the clock signal, the delay is the __ loop described in item 11 of the above (4), wherein the clock Signal increase-delay delay matrix. % Yumai (4) to the above multiplexer and the second phase 2 3 = 延迟 patent range, the delay phase-locked loop described in item 12, and the JLt second pass, the delay control difficulty number determines the first: "Ge One of the first switches is turned on to output the first extension number or the second delayed clock signal. "5 14 · The delay phase-locked loop described in item 9 of the patent scope, the above-mentioned brother in the basin The delay matrix includes a cascaded complex delay device when the second delay moment Clienfs Docket No.: VIC06-0028 TT's Docket No: 〇608-A41006TWmDavidChen/2007/02/02 18 < S 1^29994 car is a startup tree The delay delay control signal of the second delay matrix delays the first delay matrix clock signal according to the delay matrix clock signal. (1) The above-mentioned ID. A, the patent scope of the 7th reverse B delay phase-locked return failure, the second delay matrix includes - the third delay device and - the fourth extension When the second delay matrix is in the startup state, the third delay device delays the delay matrix clock signal by a unit time to generate a third delay shame. And transmitting the third delayed clock signal to the fourth delay, wherein the fourth delay device delays the delay unit of the third delayed clock signal to generate a fourth delayed clock signal. The delay phase-locked loop of claim 15, wherein when the second delay matrix is in an activated state, the second delay matrix outputs the third delayed clock signal according to the delay control signal or The fourth delayed clock signal is sent to the multiplexer. Client’s Docket No.: VIC06-0028 TT's Docket No: 〇608-A41〇〇6TWmDavidChen/2007/02/02