TWI328746B - A system for performing peer-to-peer data transfer - Google Patents

Description

1328746 发明, INSTRUCTION DESCRIPTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to data transmission within a computer environment, and more particularly to point-to-point data transmission within such a computer environment. [Prior Art]

In modern computer environments, a large number of devices are widely interconnected to provide processing speed and resiliency within the computer environment. To create this computer environment, various devices are connected to another device via an interconnect structure such as a network or bus-slot architecture. The devices connected to the interconnect structure typically include local memory that is used by a device during a computational process.

An example of such a computer environment is for image processing, in which a plurality of image processing units (GPUs) are connected to another GPU through an interconnect structure, and each GPU is coupled to a frame buffer (ie, Local memory). The frame buffer stores image data processed by the individual GPUs. In general, a large amount of data needs to be processed by the GPU to draw materials and create other image information for display. In order to achieve fast processing, the processing is divided by the number of GPUs, so the components of the job can be executed in parallel. Occasionally, in this computer environment, the image processing unit may need to use information stored in a frame buffer of an endpoint GPU, or may need to write information to a frame buffer of an endpoint GPU, such that The endpoint GPU can use this information on the local end. Currently, many interconnection structure standards 6 1328746

The implementation is like AGP, PCI, PCI-ExressTM, switching, etc., which can enable the endpoint to write information to another address space, but does not enable the address to read at another endpoint. . As a result, the image processing units will redouble their efforts to create the completed material because they do not have a frame buffer that accesses an endpoint in the endpoint address space of the endpoint, and a GPU can achieve certain The processing of the information; if the data is still needed, the creator can write the information to a commonly available system memory system through any one of the connections to the GPU. However, using normal system memory gives this a processing that consumes time and adds extra expense. What remains unchanged is the use of the memory to slow down the image processing. Therefore, there is a need in the art for methods and apparatus for improving the transmission of information in a computer peer-to-peer. SUMMARY OF THE INVENTION A particular embodiment of the present invention is generally directed to a method and apparatus for providing peer-to-peer data transmission. The more the requirement is in an interconnecting fabric to enable a first device to be read/written in the local memory of the data device. Even when the i of the interconnect structure allows such transmissions, such data transfer methods can still be executed (advance the information between the bits of the endpoints to create the rights stored in their endpoint information. This is an endpoint Memory. The type of data transmission of the interconnected structure. The internal midpoint of the common system is transmitted through an intervening invention through the pass-through read and write/from a second protocol. 7 1328746

[Embodiment] FIG. 1 shows a computer environment 100 including at least one system level computer 102, an interconnection structure 104, and a plurality of endpoint devices 1 0 3 105. The endpoint device, although it can be any form of computer device, including a computer system, a network application device, a storage device, an integrated circuit, a micro-processor, etc., in the specific embodiment of FIG. 1 Apparatus 103 105 includes at least image processing units (GPUs) 106 and 108. Although only two devices 1 0 3 and 1 0 5 are described, those skilled in the art will recognize that the invention is applicable to any number of devices. As described below, the present disclosure provides a method and apparatus for facilitating data transfer between the endpoint devices 103 and 105. The system computer 105 is a general purpose processing computer system including at least a central processing unit (CPU) 126, a system memory 128, a resource processor 129, and a support circuit 130. In one embodiment of the invention, the system computer is a "master board" of a computer or server. The system uses the devices 103 and 105 to provide a particular type of calculation (e.g., image processing). The CPU 126 can be any of the forms of a general purpose microprocessor or microcontroller. The system memory contains a combination of random access memory, read-only memory, removable storage devices, disk drive storage devices, or any record device. The resource manager 192 configures the address information to the device, such as devices 1〇3 and 1〇5, within the computer environment, and generates a memory image to the system memory 128. The support circuit 130 is a known circuit for the functionality of the computer system 1 , 2, which includes a time circuit, a cache, a power supply, an interface circuit system, and the like. Layer and packet control with this clear package, brain map and memory record 8 1328746 The interconnect structure 1 〇 4 (hereinafter simply referred to as the "structure") contains at least one of many forms of architecture, It is like enabling data to be transferred from one endpoint device to another endpoint device or to system memory. The architecture includes a look-ahead switching network or a bus bridge that supports AGP, PCI-ExpressTM or PCI bus protocol or any other form of architectural interconnect that can be used to host endpoint devices. An example of an interconnect structure 104 known in the art is an Intel® North Bridge wafer.

Although in Figure 1, the endpoint device 10 is distinct from the endpoint device 105, in some embodiments of the present invention, the logic and software for each of the endpoint devices 103 and 105 may be the same. The endpoint device 103 includes a primary GPU 106 coupled to a frame buffer 110 and supports circuitry 116. Inside the main GPU 106 is a memory management unit (MMU) 167, a fabric interface 166, a page table 136, and host side logic 134. The fabric interface 166 couples the host side logic 1 3 4 to the structure 104. The host side logic 134 includes at least a read completion message 140 and a label 142. The frame buffer 110 is basically a random access memory of some form having a very large capacity, for example, in the order of two gigabyte units or more. The memory management unit 167 couples a frame buffer 110 and a proxy 168 to other units internal to the primary GPU 106. The agent 168 contacts the primary GPU 106 with one or more clients (e.g., processing or hardware within the computer environment). The support circuit 116 includes at least known circuitry that facilitates the functionality of the primary GPU 106, which includes a clock circuit, an interface hardware, a power supply, and the like. 9 1328746

The endpoint device 105 includes at least one frame GPU 108 and a support circuit 124. The frame buffer has a very large capacity random access memory in a form of a gigabyte unit or more. Within the 108 is a structural interface 174 and host side logic 172. The 174 couples the host side logic 172 to the structure 1〇4. The host side includes at least one read mail 匣 16 一, one write data mail 匣 write address mail 匣 156. The support circuit 124 includes at least the known circuitry of the functionality of the GPU 108, the circuit package, the interface hardware, the power supply, and the like. In operation, a data transfer process begins with one of the users requesting access to a frame buffer 11 or n data. The client 112 is in communication with the primary GPU 106. The agent 168 communicates with the memory management unit ι 67 to determine whether the request needs to be accessed to a map frame buffer box buffer Π 0, or to determine whether the request needs to be accessed to the frame buffer, such as a frame. Buffer Π 8. In accordance with the present invention, in a computer environment, the user is allowed to access data within an endpoint buffer 118 that is adapted to indicate which physical location is accessed in the endpoint frame buffer 118. A specific virtual address that is the read or write request issued by the client 112. The page table The resource manager 129 is generated during the initial process to reflect the image, such as the local end, system, endpoints, and the like. On the page buffer is a certain J as in the 2 target GPU structure interface logic 1 72 1 5 4 and a proxy 1 6 8 that promotes the internal clock terminal 1 1 8 8 , the unit 'like Figure 1 Endpoint diagram client 1 12 grid 136 series memory location should be from the grid 136 from the memory table 1 36 10 1328746 inside an attribute field can identify whether the data is associated with a map frame buffer 1 1 0, is still associated with the system memory 128, or associated with the frame buffer 118, or is not associated with a memory. As previously described above, the memory management unit 167 uses the page table 136 to use the material associated with the read or write request issued from the client 112 for the read or write address, and Based on this, it is judged whether the address is inside the endpoint frame buffer 1 1 8 .

In more detail, the information used to identify and decode information in a local or remote frame buffer is the input stored in the page table 136 and used by the requesting endpoint device 103. The page form inputs are maintained by the resource management software and interpreted by the memory management unit 167. Importantly, the entity address and the data type of each page referenced at a request from the client 112 are stored by the resource manager 129 in the page table 136. The target endpoint device 105 needs this information to provide the required information to the requesting endpoint device 103. For the purposes of this description, "data type" may include (but is not limited to), terminal requirements, compressed format, data structure organization, information about how the data is described, and any relevant when extracted or stored from a local end. , how the information will be referenced or converted, information, system or endpoint address space or any combination of the above. The details of reading data from an endpoint frame buffer 1 1 8 are presented in the following section regarding FIG. 3, and the details of writing data into an endpoint frame buffer 118 are related to FIG. Presented in the following sections. Figure 2 shows one of the functional areas of the computer environment in Figure 1 1 1328746

The figure, in particular, the interconnectivity of the endpoint devices 103 and 105. The mutual end device 103 accesses (reads or writes) the endpoint device frame buffer 1 1 8 without modifying the structure 104 or the fabric 174. As such, the interfaces 1 66 and 1 74 of the structure 104 itself can be any standard interconnect structure and are associated with the interface of the endpoint devices 〇 3, 105. For access to the frame buffer 118 of the endpoint device 105, the host 134 provides for facilitating the presence of the endpoint frame buffer 118 without requiring changes to the fabric interface 166, 174. As a result, when a request issued by the client 112 and used within the endpoint frame buffer 118 is received by the host 134, the host-side logic row converts one of the data requests to a configuration interface 16 6 is in the middle. The structural interface 166 transmits the structural interface 1 74 of the desired point device through the structure 105. The host side 1 72 provides the frame buffer 118 functional inside the remote endpoint device 105. For example, if the 112 request coupled to the endpoint device 103 requests the host-side logical translation from the frame 118 inside the endpoint device 105, the request is in an understandable format and passes through the fabric interface. 166. The structure 104 and the structure interface 174 are such that the request passes from the endpoint device 103 to the device 105 and is processed by the host terminal inside the endpoint device 105. The host side logic 172 provides access to the frame buffer so that the data will be readable and can be written, depending on the requirements within the 105. If the request is a read request, from the connection of the 105, the structure provides access to the client data through the cooperation of the client's data 134 to the terminal. , ready to use through L. Endpoint Installation 172 118, Endpoint Mounting This Frame 12 1328746

The data sent by the buffer 118 is transmitted from the host side logic 172 in the manner that the interface 174' the structure 104 and the structure interface 166 accept, and the data is passed to the endpoint device 103, where The master logic 134 will process the data. In this manner, the endpoint device 103 1 可执行 5 can perform point-to-point data transmission without any modification to the fabric interface 166, 1 or the structure 104. As a result, the endpoints of the present invention are placed in the computer environment 100 to communicate using a standard protocol using standard protocols. In a particular embodiment, the structure 1 与 4 and the structure 166, 174 support PCI or PCI-ExpressTM. As is known in the art, some implementations of the PCI and PCI-ExpressTM protocol do not permit a read request to communicate to facilitate point-to-point read performance. However, such identical structure 104 does permit a write request communication to facilitate the point-to-point write function. Therefore, the standard protocol permits one device to write data to the frame buffer of the other endpoint, but will not allow an endpoint device to read data from the frame buffer of the other endpoint. The present invention overcomes the shortcomings in the standard protocol by enabling host-side logic 134, 172 to provide enhanced functionality to enable the ability to read and write data between endpoint devices. Read Transaction Figure 3 is a flow diagram of a process 300 for reading data in a point-to-point manner in a computer environment in accordance with the present invention. In order to effectively understand the invention, the endpoint device 103, which is required to read the data, will be identified as the "main device" underneath, and when the information is included for reading, the constructor and the 74-faced surface are constructed. Quasi-issue this write from the most to the 13 1328746

The endpoint device 105 will be identified as the "target device." The process 300 begins at step 302 and proceeds to step 304 based on issuing 168 from the client 112 and requesting a trip 3 0 from the target frame buffer 118. The primary device 1 0 3 must determine the data by Having the memory management unit 167 accessing the page data is stored at the local end, and the process 300 proceeds to step 408 of extracting data from the buffer 110. The data is provided to the agent, and the process 300 ends on the other hand. If the resource is at the target device 105 at step 306, the method 300 proceeds to 312, the host side of the main device 103. The read command and the address of the client 112 are loaded to a read request packet (also 105) written to the endpoint. Because the structure 104 does not need to be able to read the loading process, it must be performed. However, the structure 104 will understand the requirements. Therefore, the host side logic 134 encapsulates the read information including an instruction field, a physical address identifying where the data system buffer 1 1 8 is internal, and a data type of the requested data (eg, for a specific purpose) To compile the recognizer of this format). In a specific embodiment, the memory management unit 167 can determine the physical address from the data, the size and type of the data. A person skilled in the art will recognize that step 3 04, the agent of the instruction reads the material. Where the step is located, borrow Form 1 36. If it is slow from the map frame, at step 3 1 0, 3 3 2 ° is judged to be located at > 3 3 2 . In the step series 1 3 4 will take the material type, the same seal is the target device to operate, so the seal and pass the write instruction information 'the size of the data in the endpoint frame, the code to store the data The data of the data of the host side logic 1 34 page table 1 3 6 is transmitted, and the transfer of the entity 14 1328746 address to the target device 105 allows the read command to be processed by the target device 105 without any bit Address conversion.

At step 314, the host side logic 134 addresses the write request (including the read request packet) to a read mail 匣 160 in the target device 105. In a specific embodiment, the read mail address is provided by the resource manager 164. At step 316, the fabric interface 166 passes the request to the target endpoint device 105 via the fabric 104. At step 318, the organization interface 174 receives the write request. In step 320, the payload is fetched from the read request packet, thereby converting the write request containing the read request packet to a read command. The host side logic 172 places the read command in the read mail port 160, a proportional first-in first-out (FIFO) buffer having a depth, which is commensurate with the largest number of changes, and the change is performed by the main device 103 allows for an unprocessed portion. In this connection, the FIF 0 (or queue) holds individual read commands until it is processed by the target device 105. After step 322, the host side logic 172 removes the read command from the read mail frame 160 and reads the data from the frame buffer 118 based on the read command and data type. At step 324, the host side logic 172 encapsulates the retrieved data into a complete packet that is transmitted as if it were the same write request packet and is consistent with the protocol supported by the structure 104. The host side logic 172 addresses the write request to the read completion message 140 within the primary device 103 in step 326. At step 328, the fabric interface 174 transmits the write request to the requestor, i.e., the client 112, via the fabric 104 and via the primary device 103. 15 1328746 At step 330, the fabric interface 166 receives the write request. At step 332, the host side logic 134 within the primary device 103 places the write request to the read completion message 匣 140. At step 334, the host side logic 134 retrieves the data from the read completion message 140 and provides the data to the client 112 via the agent 168 in step 336. The process ends at step 338.

When the write request is placed in the read completion message 匣 140 in step 332, the trace logic located under the read completion message 匣 140 is used to trace the unprocessed read request and the unprocessed request and the The read completion packets returned by the target device 105 match. The tracing logic can explicitly store client information in order to pass back the read data to the appropriate client 112. In some embodiments of the present invention, the read completion message 140 includes a storage resource, such as a scratchpad, a memory, etc., which is reserved for the trace logic for use in the data. Store the captured data before transmitting it to the client 1 1 2 . In a specific embodiment, within the host-side logic 134, a tag is generated when the read command has been issued, and the tag is compared to the read-complete tag, the read-complete tag is written and written. The data entered into the read completion email 140 is received in common. Therefore, many clients 112 can make a read request to the various frame buffers inside the computer ring 100 through the agent 168, which is important for tracking the release and completing the read request to avoid possible errors. . As described above, the present invention is performed by enabling a point-to-point read transaction, even though the interconnect structure 104 may not be supported by a read transaction. In this connection, the read transaction can be performed without modifying the standard communication protocol used by the structure or supported in the specific implementation of the structure 16 1328746. Write Change Figure 4 shows a flow diagram of a write request change in a one-to-one computer environment in accordance with the present invention. In order to most effectively understand the invention, the reader should observe both Figure 4 and Figure 1 when reading the following disclosure.

The process 400 begins at step 402 and proceeds to step 404, which is located at the agent 168, in response to a request from the client 112, and requires the data to be written to the frame buffer 110 or 118. At step 406, the memory management unit 167 determines from the page table 136 whether the location for writing the material is within a map frame buffer 110 or within an endpoint frame buffer 118. If the location is within a map frame buffer 110, the process proceeds to step 408 where the material has been written to the map frame buffer 110, and the step ends at step 410. However, if the data is written to the endpoint frame buffer 1 1 8 , then the method 400 proceeds to step 412. At step 412, the host side logic 134 dispatches a physical page address and a data type assigned to the client 112 write request (which is in the page table), and is stored in the tag 142 (the system is located The physical page address and data type of the primary device 103 are compared. As further described herein, the physical page address and data type listed in the tag 142 will correspond to output the last write request to the target device 1〇5 (from the primary device 103). The physical page address and data type. Therefore, the physical page bit in the tag 142 17 1328746

The address and data type are always matched to the physical page of the target device 105 and stored in the physical address and data type of the write address mail 156. Stored in the write address message 156, the physical page address defines an aperture to the endpoint frame buffer 118. The aperture system is smaller than the area inside the endpoint frame buffer 118. In other words, the aperture may correspond to a fixed memory page within the endpoint frame buffer 118, and the lower bits of the write request address are indexed into the aperture. The aperture can be moved by changing the physical page address within the write address 匣 156, as further described herein in the label 142 of the physical page address and data type and the physical bit of the write. When the address and the data type match, the aperture entering the endpoint framer 118 is correctly aligned with the client Π2 write request. If the client 112 is assigned to the request entity page bit in step 412 If the address and data type do not match the body page address and data type listed in the tag 142, then the process 400 proceeds to step 414. In step 414, in response to a mismatch, the host side logic 134 in the primary device creates a write address request to update the physical page address and data of the column write address mail S1 5 6 Types of. The purpose of the step is to establish an aperture position that matches the physical page address assigned to the client 112 write request, so that the data contained in the write request of the client 112 can be appropriately written to the Target buffer 118. In general, the aperture can be adjusted to the same size as the memory page of the target image 118. Similarly, the write message 154 can be resized to store the target frame buffer 1.172 address. This example is specially provided for an email. Into the buffer K. The fact that the step 103 is at this step, the guest, the guest frame, the frame is slowed down. 8 of 18 1328746

Memory page. At step 416, the node of the primary device 103 transmits the write address request, which includes the address and data type assigned to the client request (through the structure 104 to the target device 105). At step 418, the target device 105 is structured to address the address request, and at step 420, the host side logic includes the write address request (which is tied to the entity in step 414). The page address and the data type are used to update the file 156. When the address stored in the write address message 156 has changed, the aperture is moved, that is, the different memory page located inside the buffer 118. The tag 142 is updated by the logic 134 at step 422 to pair the physical page address and data type of the address in the write address. The aperture entering the punch 118 here is correctly aligned to the client 11: At step 424, the host side logic 134 posts a write to the write data in the target device 105. The payload of the write data request may be all or part of the data included in the client request. Step 426, the node transmits the write data request to the target through the structure 104 to the target device 174 data request of the target device 105 in step 428. In step 430, the host side logic 172 enters the payload required by the data entry. Placement In the step 432, the payload is sent from the write data message to the aperture inside the frame buffer 118 and written by the write interface 1 6 6 1 1 2 to the physical page surface. The 174 receiving set 172 uses the effective negative write address of I:) to send the end point frame of the physical page to be slow, and the end point frame of the host end piece 匣 156 is slow to write the request. Input data requirements 匣 154. End 1 1 2 writes interface 1 6 6 device 105. Receiving the write is included in the write 匣 154. 1 54 Write to Address One of the addresses specified in Address Mail 匣 19 1328746 156. Further, the payload is written in a format specified by the type of material contained in the write address message 156. The method 400 ends at step 434.

In this manner, an additional amount of data, such as a 1 2 8 byte, is typically generated in the block, which can be continuously written to the same memory page, that is, inside the target frame buffer 118. The aperture. Once the aperture has been placed, the host side logic 134 of the primary device 103 can quickly transmit a continuous write data request containing data stored in the target frame buffer 1 18 (eg, the memory page) to Corresponds to the aperture. When a client 112 write request crosses a page boundary, the write address mail 156 has been updated to move the aperture to a different memory page, as described above. Since the write address request is passed to the write address mail included in the physical address of the target frame buffer 118, the target device 1 0 5 does not need to perform an address change operation to use the receive address. The write operation from an endpoint device can be performed very efficiently.

While the foregoing is directed to the specific embodiments of the present invention, further embodiments of the present invention may be practiced without departing from the basic scope thereof, and the scope of the invention is determined by the scope of the claims described below. . BRIEF DESCRIPTION OF THE DRAWINGS In order to provide a more detailed description of the method of the present invention as set forth above, a brief summary of the present invention is described in more detail above.

The specific embodiments are referred to as references, some of which are depicted in this additional figure. However, it is to be understood that the appended drawings are merely illustrative of specific embodiments of the invention and are not intended to Figure 1 shows a computer environment which can be used in a specific example of the present invention; Figure 2 shows a functional area in the computer environment of Figure 1 which is shown in Figure 3 A specific embodiment of the invention, a flow chart executed in a reading process; FIG. 4 is a flow chart executed in a writing process according to an embodiment of the present invention; Description] 100 computer environment 102 computer 104 structure shown in the block everywhere

105 device 1 06 image processing unit (GPU) 1 08 image processing unit (GPU) 1 1 0 frame buffer 1 12 client 1 1 8 frame buffer 124 support circuit 21 1328746 126 central processing unit (CPU) 1 2 8 System Memory 129 Resource Manager 1 3 0 Support Circuit 1 3 6 Page Table 1 6 8 Agent 1 1 6 Support Circuit

167 Memory Management Unit (MMU) 1 6 6 Structure Interface 1 3 6 Page Table 1 34 Host Side Logic 1 4 0 Mail 匣 142 Label 1 5 4 Data Mail 匣 1 5 6 Address Mail 匣 1 6 0 Read Mail 匣

1 6 4 Resource Manager 174 Structure Interface 1 72 Host Side Logic 300 Processing 302~338 Steps 400 Processing 402~434 Step 22

Claims (1)

1328746 Pickup, patent application scope: 1. A system for performing a point-to-point data transmission, comprising at least a first device; a second device; an interconnection structure; wherein the first device comprises at least a first host end Logic, which can be negotiated from the first device to the second device through the interconnect structure to create a read command, and a first structure interface, the read command is from the first through the interconnect structure Transmitting the device to the device; and wherein the second device includes at least a second host-side logic that takes a local memory within the second device to retrieve data identified by the command and a second structural interface And the interconnecting structure for transmitting the data from the second device to the device. 2. The system of claim 1, wherein the interconnecting bridge device supports AGP, PCI bus PCI-ExpressTM bus bar protocol. 3. The system of claim 1, wherein the first device comprises at least an image processing unit and the local memory is at least a frame buffer. Contains: Using a communication for the second storage read reference to use the first structure as or PCI and the second inclusion a 23 1328746 4. A system for performing point-to-point data transmission, comprising at least: a device; a second device; and an interconnect structure; The first device includes at least a first host-side logic for creating a write address request, the write address request includes a page address and a data type; creating a file that can be written a write data request for data into the local memory of the second device; and a structural interface for requesting the write address and the write data request from the first through the interconnect structure Transmitting a device to the second device; The second device includes at least a second host side logic for responding to the address address request to be updated in a write address mail (which has the inclusion in the write address request) A page address and a data type of the page address and the data type are stored in the data message and stored in the local memory. 5. The system of claim 4, wherein the first host-side logic further comprises the address and the data type listed in a tag (which is present in the first device), and the dispatch Comparing an address of a write request (received by the first device) with a data type, wherein the address assigned to the write request and the data type are included in the write address The page address in the request is the same as the data type. The system of claim 5, wherein the first host-side logic further comprises a address and a data type listed on a tag (which is present in the first device) Updated to the page address and the data type written from the write address request to the write address message. 7. The system of claim 4, wherein the interconnect structure is a bridge device that supports AGP, PCI bus or PCI PCI-ExpressTM bus protocol. 8. The system of claim 4, wherein the first and second devices comprise at least an image processing unit, and the local memory comprises at least a frame buffer. 9. The system of claim 4, wherein the second host-side logic writes the data from the write data message to the local memory via an aperture. 25