TWI328271B - Structures for and method of silicide formation on memory array and peripheral logic devices - Google Patents

Description

P940263 I9224twf.doc/006 IX. Description of the Invention: [Technical Field of the Invention] The disclosed technology relates to a high-density integrated circuit. In particular, the disclosed technology relates to the manufacture of a memory cell in an integrated circuit component including a non-volatile memory and its associated peripheral circuit. [Prior Art] Currently existed. The need to increase the operational speed of non-volatile memory components. To achieve this, various techniques have been implemented in component manufacturing and structural design. For example, reducing the feature size of a non-volatile memory component typically increases its operating speed. Another need for this involves reducing the spacing between the control gates of the memory cells by fabricating bit lines that can be used as a source of transistors and poles. The operating speed of the non-volatile memory element has also been increased by minimizing the spacing between the contacts. By causing the gate of the memory array to be tied (siHciding), the _ resistance is reduced, thereby reducing the return (reSP〇nSe dday) and also increasing the operating speed. In some cases, deuterated metallization has been achieved by using a self-aligned process called saliciding in the art. Theization of the bit line due to the self-aligned Shihua chemical metallization process is a problem in some prior art manufacturing processes. For example, U.S. Patent No. 6,566,194, issued on Jun. 2, discloses the doping of the word lines in the grounded array flash memory device and the self-induced metallization without causing a bit line between Short circuit process. According to one of the sadness of this ^ P940263 19224twf.doc/006, before the patterning in the core region (P〇lylaye〇, the substrate between the polylayer lines used for the word line in the upper and lower sub-lines is exempted from being subjected to doping Miscellaneous (1 = ^ this 'poly layer protection word short circuit". According to another method of this method, / / b will bow the bit material between the bit lines to protect the word line between the "time material, dielectric The quality or dielectric prevents the substrate from being self-physicochemically metalized by the possibility of causing the position: (2), (eg, doping). ("Abstract of Inventions No. 6,566,194" I杲@专利第2000年月Announcement on the 24th - ru λ-^ Shows the insults of the 6th, 136, 636 and the formation of self-aligned 闸 = 所 所 所 所 所 所 所 所 所 所 所 所 n n n n n n n n n n n n n n n n n n n n n n n n n The method of resistance in deep sub-micron IMOS transistors. The difficulty involved in non-volatile memory components is increased according to the circuit including ==贞 type. For example, non-volatile memory = piece ^^ Memory early array and various peripheral circuit functions. Memory early array includes control gate (Caf (6)_), such as floating The charge between the interpole (such as the gate gate gate) or the charge trapping ^ldectnc + is trapped in the structure and the memory and the drain of the drain region. The control gate can be connected by the word line. Together, the source and drain regions can be connected in series or in parallel by bit lines. The peripheral circuits can include field power cells (fields) that are suitable for high voltage or low voltage operation using gate dielectrics of different thicknesses. Effect transistor), and may include functions such as a decoder, a charge fruit, and a control circuit to facilitate stylization, reading, and erasing of data in the cells of the memory cell array. 1328271 P940263 I9224twf.doc/006 Non-volatile The memory technology of the memory supports the manufacture of the memory array (including the virtual ground memory array) without the bit line short circuit. SUMMARY OF THE INVENTION The present invention provides a memory element fabricated on a semiconductor substrate. And an improved method of the peripheral circuit together with a novel integrated circuit structure. The method α includes manufacturing a memory component and a peripheral circuit on the substrate, wherein Body

Early W does not have the source and recording area of the Wei metal layer, the surrounding electricity, the transistor in the middle includes the secret of the tree metal layer and the bungee region, and the periphery of the t includes the thickness of the gate dielectric having different gates. High piezoelectric crystal. The method of 彳 彳 迷 迷 包括 包括 包括 包括 包括 包括 包括 迷 迷 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法 方法

5 = load into the layer. And forming a second=four-th gate dielectric layer on the second region of the substrate. The low-voltage transistor will form a second gate dielectric having a third thickness on the three regions of the second plant. Electrical layer, second thickness 'High dust crystals will be built in this area. Depositing and patterning the gate material (in the more coiled disk: polycrystalline (four) other inclusions) on the substrate method φΐ—and the third region to define the transistor in the real three regions of the method in the first region Gate. The method described herein selectively _ in the third region to reduce the first of the source and the gate regions adjacent to the gate region to be close to the second thickness. "close to the second thickness" π 9 1328271 P940263 19224twfd 〇 c / 〇〇 6 = is sufficiently close to the second thickness that the pole is removed; the steps required for the electrical material are at the time of the rhyme An interpolar dielectric material. After subtracting the thickness of the second thickness and the thickness of the third and second dielectric layers, the second and third regions are in the second and third regions: the pole and the bungee region and the The word in the three districts is in the first and second materials. The last name is the dielectric interval; the third interval in the dielectric interval is exposed to the second and - and the first side. The source of the spacer spacer and the spacer in the non-polar region Γ Γ Next, with the sidewalls of the second and third regions, the == generalized source and the non-polar region are extremely dielectrically selective The first and second gate spacers are exposed adjacent to the sidewalls to expose the i!:i exposure, and the substrate contact region is preferably the use of the word lines and gates in the second and second regions. At the top of the exposed metal forming process, the side of the formation of the stone is formed adjacent to the first And the source and the non-polar region of the adjacent two objects in the third region, and are formed on the word lines and the gates in the first, third, and third regions, and remain in the bit line contact region during the sanding metal process. The charge in the charge is formed by the formation of interlayer dielectric on the sub-line of the sub-area and on the gates of the second and second 1328271 P940263 丨 924twfdoc/006. The bit line contact region ^ is formed through the (four) dielectric bit line defect. Since no Shi Xihua full f is formed in this region, the short circuit between the bit line contacts is prevented. Forming a similar contact through the interlayer dielectric f. Such a technique forms an interconnection of Li components for one or more patterned conductor layers on the interlayer dielectric. The bit line contacts and the peripheral regions are connected To == The substrate (four) miscellaneous area is cut by the interlayer dielectric f to protect the cover material 3 (4). The cover is removed before the protection of the word metal. In the deposition of the dielectric spacer material, the word line in the first area The second and third districts of the heart ^; 1 electric liner (dielectric liner) can be caused in the phase, | η _ A. On the dielectric spacers to form a lateral soil spacer to form a memory / seed The body circuit includes a plurality of layers of the plurality of layers in the first region of the substrate, the middle layer, the drain region and the first layer, and the dielectric layer including the dielectric layer Quality $ immersed layer. Inter-layer if; and - or more charge between the top and bottom layers " package ^ and conductor structure over the memory array. Even. 1328271 P940263 19224twf.doc/006 bit line connection Point, via the bit line in the bit line, the package U connects the conductor structure to the plurality. In the case of the electric charge trapping, the thinning metal layer is formed in the material (10) line deposited between the word lines in the word lines in the word line group. A gate a Φ as body having a second thickness that provides shielding during the first set of electrical circuits has a gate dielectric adapted to a lower voltage operation. Substrate

It is adapted to the second of the higher voltage operation; the third thickness of the body is greater than the second thickness. (7) etched "electric scallops, including a gate dielectric having a second thickness, at least the upper portion of the transistor, and a dielectric sidewall spacer having a dielectric sidewall spacer; The material layer of the dielectric material is located at the bottom of the sidewall spacer: between the faceplates:::, which has a thickness close to the second thickness.

The above and other objects, features and advantages of the present invention will be described in the following description. Hey. Ping, .. Tian 5 brother [Embodiment] The following detailed description is made with reference to the examples illustrated in the drawings. The description of the embodiments is used to illustrate the method 'as defined by the definition of category. Those of ordinary skill in the art will recognize a variety of equivalent variations described by the best mode of the Levant. Figure 1 below shows a simplified block diagram of the integrator made by the technique of the root S herein. The integrated circuit 10 includes a memory array 12. =10 5 Remembrance 丄(10)271 p94〇263 i 9224twf.doc/006 Column 12 includes the charge trapped in the memory cell so that the line contact area is covered by the material for the fill line % line_area'. The word line decoder] 4 is charged into the structure of the stone horse device 1 至 connected to the bit line 2 〇 16, and the bit line deficient memory unit reads the operation of the capital and writes the non-volatile Z body unit of 12. For the non-volatile operation of supplying the address to the word 歹i I2 on the address line 22, it can be lightly connected to the bit line decoder 18. & input/output from the bus-feed bus from the integrated circuit W. From the m-input bus 28 and other data sources to supply data to the block 24, f circuit 1 〇 internal or external... integrated circuit Other circuits 30, including input structures, may be included on the 10th. Benefits or dedicated to - or multiple applications of the circuit ^ general micro-processing array 12 storage data function / "including the combination of block 2 by the memory bus 32. Through the data output 匕 甲 甲 感应 感应 感应Circuit U) read ~ transfer material, offer = shake supply to other data destinations of the integrated body. In this silver: two circuit J 〇 internal or external power supply voltage charge mille 36 application to the controller = 34 control The operation of the memory unit, such as reading, ^匕', the recording of the body array 12 and the stylized verification voltage. It is possible to estimate the erasure and erase the verification to apply the control H. The quadrature circuit U) is not included in the land circuit, and may include and is generally referred to as a peripheral field effect transistor thickness of the Kelly and/or low voltage w~ original charge system 36, word line decoder 14, P940263 ^9224twf.d〇c/〇〇e Where:, controller 34 and other peripherals, Figure 2 is not disclosed in this article - side wrapping. Memory array] 2 has a schematic diagram of the allowed pair = The N〇R structure of the selective control is selected as the multiple = and the bit line 20. The unit structure 62^=(2) unit 6] has the same structure, arranged in a matrix, and is shared by a plurality of bits into the structure. The bit line contacts 64 are disposed in the spoon red and the word line 16 bits. In the line contact area 2, the material mask of the charge trapping structure in the body unit of the full == 匕 metal mask is used for memory to the bit line 20 to provide the bit turn ^ 2 = ^ The tool of the contact 64. In the technique discussed herein, the metal mask of the material-recalling unit of the charge-trapping structure of the bit line is prevented from being covered by the cover, and the line contact area 200 Shi Xicheng's ^==^ short circuit between the shapes during the metal forming step of the bit line contact 64. And the sigh mode to prevent the bit line contact < FIG. 3 illustrates a plan view of the portion 60 of the array 12 according to the discussion herein. An array of memory memory cells 62 of a consistent embodiment, wherein the structure is configured with word lines 16 to perform a plurality of memory/ground control bit lines 2 to include the spacing between the memory substrate wells Operation. The line is 2 〇 0 separate separation doping area. Word line 16 broadcast & by can be cut metal Between the words; = 2 () between the word line 16 includes phenotype, amorphous polycrystalline 14 1328271 P940263 19224twf.doc / 006 separated structure. The material used in the charge trapping structure f 仏 位 骇 。 。 。 。 。 。 。 。 The He 64 is placed vertically = the charge trapping material layer 110, and the charge trapping material layer no acts as a junction between the set of word lines 16 (4). The structure of the heart body 7L 6 2 includes - the adjacent bit line The portion of 2 G and the portion of the stacked word line 16 and, moreover, the region of the inserted charge trapping structure 110. Figure 3 shows the dashed lines A_A, B_B, c_c, and _, which define the segmentation of the cross-sectional view in subsequent figures. flat. 4A, 4B, and 4C show cross-sectional views of portions 6 of the memory array 12, Α·Α, B-B, and C-C, lines. Figure 4A additionally shows a cross-sectional view of the high voltage, body 70 and low voltage transistor 80. The memory array 12 includes a charge trapping structure 11 placed on the memory plate 102. The memory substrate well 102 is formed in the substrate 1 by dopant implantation. The word line is placed on the charge trapping structure 11〇. The germanium-containing material, such as one or more layers of doped germanium, amorphous polysilicon or the like, is typically used to form the word line 112, the still piezoelectric crystal gate 丨 24, and the low voltage transistor gate 134. The exemplary high voltage transistor 70 includes a high voltage dielectric 122, a transistor gate 124, and a substrate well 120. The substrate well 120 is implanted in a dopant in the substrate 1 and is formed by P-polar or N-polar doping as may be required for the particular high voltage transistor formed. The low piezoelectric crystal 8A includes a transistor low voltage dielectric 132, a transistor gate 134, and a substrate well 130. The substrate well 13 is a dopant implant formed in the substrate 100 by P-polar or N-polar doping required to form individual low voltage transistors. A plurality of high-voltage 15 1328271 P940263 19224 twf.doc/〇〇6 piezoelectric BB bodies 70 and low-voltage transistors 8 可能 may be required in the fabrication of the integrated circuit voltage charge pump 36 of the integrated circuit 1 and other regions. In order to support higher operations. .

The formed high voltage dielectric 122 is compared to the low voltage dielectric 132, \ voltage, thickness. In the above manufacturing step, the hard mask 114 covers the word Y with a larger high voltage transistor gate 12 4 and a low voltage transistor gate 丨 3 4 & 2 = J12, the word line 112 extends laterally to the bit line 20 and stacked on the electric #, : α structure. Structure 110. The bit line 20 is formed in the memory substrate well 1 〇 2 t = the input structure, and the oxide structure 116 is overlaid on the bit line 2 。. The doped physiograft layer 104, the central charge trapping layer 106, and the top dielectric layer are connected to the word line 112 and the exemplary memory unit 62 of the substrate array 12 including the lateral extension The portion of the word line 16 adjacent to the bit line 20 is memorized, and the memory cell 62k pair includes a region of 110 that is inserted under the word line 16 and between the bit line 2A. ° Q Eight Structure FIGS. 4A-4B illustrate the formation of the charge trapping structure 11 on the integrated circuit board 100. The substrate can be made of (4) or other

Any suitable material is made. The first region of the dielectric material is a charge trapping structure 11〇 of the germanium structure, which includes a bottom dielectric layer and a top dielectric layer 108, and a central charge is inserted between the bottom dielectric layer and the top dielectric layer (10). Layer 1{)6. Typically, the charge trapping structure has a thickness between approximately 140 and 210 angstroms. The dielectric layer 104 is formed by patterning the substrate 1 to deposit a bottom dielectric layer 1 〇 4 charge trap layer 1G6 and a top dielectric layer (10) by using a standard chemical vapor deposition layer; Dioxo cut. The middle charge trapping layer has just been cut by nitrogen deposition of 1328271 P940263 19224twf.doc/006 by standard chemical vapor deposition (4). The top dielectric layer (10) includes the dioxide dioxide deposited by the fresh chemical vapor deposition process. It is known in the art that other materials and combinations of materials can be used, and the layers of the two-electric (four) human structure can be used. Preferably, the top layer of the charge trapping structure comprises "the same material used for the dielectric material in the high voltage and low voltage transistors, or is more tolerant for use in forming the self-aligned metal." , removing the source and the gate dielectric material on the trace region. The brewing lit method also exposes the high voltage of the high voltage dielectric layer 122 and the low dielectric material 132 deposited on the substrate 丨 (8), respectively. The % of the transistor and the low-voltage transistor are made of 〇. By making the time in the integrated circuit 1(), it is possible to provide a partial wipe with a peripheral transistor having a lower and lower operating power. The electrical structure 122 and the low voltage dielectric structure 132 can operate the transistor % at a voltage relatively higher than the cost of the transistor 8G. The rolled dielectric structure 126 can be, for example, approximately 17 angstroms thick yttrium oxide. Dielectric structure 136 may, for example, be an oxide scale of approximately 65 angstroms thick. This method exposes self-aligned metallization words, lines 112 and peripheral transistors 7 and 8 for manufacturing memory array 12. Self-aligned Shi Xihua metal. Control gate and source-no-polar zone The field, as described below, also reduces the oxygen lining #156 (Fig. 7) loss and the improved method of nitriding the spacer 154 (Fig. 8) undercut. ^ Word line 112 and peripheral transistor gate 124 and 134 can be formed, for example, by depositing a polycrystalline layer having a thickness of approximately 2 Å on a substrate on a substrate. The patterned polycrystalline layer is then patterned as a word line 17 1328271 P940263 19224twf.doc/006 112 and peripheral transistor control gates 124 and 134. A two-hard mask 114 is then formed by exposing the patterned polycrystalline stone to plasma enhanced chemical vapor deposition. The resulting hard mask has Approximately 7 angstroms of thick material and protecting the polycrystalline under the patterned hard material during engraving to promote etch, to form word line 112 and gates 124 and 134, between word line 112 and inter-electrode interpole 124 m has a hard mask 114 of the surface. Figure 5 shows a cross-sectional view of the eight-high calendar J crystal 70 and the low-voltage transistor 8〇 of the portion 6() of the memory array 12. Here, the m-body is compacted. Array 12, electro-optical crystal (10), and integrated circuit 1 〇, 彳f 刎 刎 or the like These areas of the resist are protected from the 17G. The protection against _ ΐ ΐ 8 does not reproduce the South piezoelectric crystal 70, and the thickness of the area where the remaining 7 is coated * the thickness of the dielectric 2; 2 ^ 3 ^ 2 The thickness of the electric mass m is such that it is approximately equal to the low voltage electric power. The hard mask 114 protects the high voltage transistor gate 124, the brake i and the engraving agent 170, and thus the 'high voltage dielectric 122 is immediately adjacent to the high 17 〇&quot ; 诘, I, the lower region maintains its original thickness and is not opened by the etchant β and is in this way 'the high voltage gate dielectric 126 in the region below the high voltage transistor. Protecting the anti-buckling agent around the low-voltage electric 曰m70 acts on the low-dust electric crystal 8〇' and thus keeps the ring factory: 2::;, the low-voltage dielectric substance 132 in the area of 134 is in this way, at low pressure The Thunder has a lower thickness and a lower dielectric 136 in the region below the lower 134. Therefore, this method provides 18 1328271 P940263 J9224twf.doc/006 for the south piezoelectric crystal gate dielectric of the low-voltage transistor gate dielectric 136. Each degree is reduced by _7 〇 to reveal the thickness of the electric mass m, so that it is approximately equal to the dielectric ΐ3ζ·^® is ensured by ensuring high dielectric 122 and low dielectric dielectric 132 degree. Approximately equal, this method exposes a wear-and-removal effect to perform subsequent surrogate and pre- or elimination cleaning steps. If the oxide thickness is not = 1 in this way, such defects may occur. effect. f 4 _ step to remove the source (four) and 汲 sub-package 122, thus reducing the thickness of the high-voltage dielectric 122 to approximately 6 = indicative process, the appropriate area of the integrated circuit 1 藉 by the photoresist material (column, positive or negative photoresist) to mask, and to withstand dry, directional, such as reactive ion etch process. Figures 6A-6B show A-A cross-sectional views of portion 60 of memory array 12 and cross-sectional views of high voltage transistor 7A and low voltage transistor (10) during subsequent stages of the fabrication process. Regarding the memory _ 12, the protective anti-money agent is removed and then patterned and an oxide pad U0 is formed to cover the word line out and the top dielectric layer 108. Next, a material of the nitrite 152 is deposited on the oxide liner, and a nitride spacer 152 is formed by an anisotropic meal. To form spacers 152, the insect traps expose the charge trapping material in the bit line contact region 200, and the bit line contacts 64 of the memory array 12 can then be formed there. For example, the button used to form the spacer 152 exposes the top dielectric layer of the charge trapping structure 11 〇8, which is shown in the above table 19 1328271 P940263 19224twf.doc/006. The etching of the tantalum nitride spacer 152 can remove the removal of portions of the oxide liner 15 turns, which results in a small oxide liner loss 156 between the word line 112 and the tantalum nitride spacer 152.

Regarding the high voltage transistor 70 and the low voltage transistor 8A, after the protective resist 118 is removed, the p_ and N_ source and the drain region 140 in the transistors 70 and 8 are patterned and slightly Doped drain (LDD) deposition. A germanide liner 150 is deposited over the high voltage transistor gate 124, the high gate dielectric 126, the low voltage transistor gate 134, and the low voltage gate dielectric 136. Next, a tantalum nitride spacer material is deposited on the oxide liner 15〇, and then a nitride spacer spacer 152 is formed to form a source of the high voltage transistor and a dielectric layer portion on the polar region and the health day. The dielectric f 132 portion of the source and the pole regions facilitates the fabrication of the transistor % and the subsequent implantation of the heavily doped heterodymous region required for the parasitic region. According to the aspect of this method, when it is called a slight change (LDD)

In the implanting process, the same-collecting mask can be used to dope the source of the high-voltage body 70 and the low-voltage transistor (10) and the drain region = body 70 and 8G ', and the mask can be used. The set is implanted with a p_divisional region' and a different subset of masks can be used to implant the Ν·%: °^, · select fresh and implant conditions to make the desired component. Depending on the application. For example, it is possible to deposit a barrier such as a shed (electricity == depositable such as germanium (electron) impurities. The lightly doped/pole region 140 may be in proximity to the transistor gate dielectric during fabrication of the transistors 70 and 80' The regions 126 and 136 are formed. In an exemplary process, after the coffee is deposited, a suitable protective 20 1328271 P940263 19224 twf.d〇c/〇〇6 mask pattern is placed on the integrated circuit 10 and will be conformal An oxide liner 15 is deposited on the word line 16, the transistors 7A and 8G, and on the bit line contact area 2〇〇 exposed by the top dielectric layer 1〇8 between adjacent word lines 16. The oxide liner 150 is deposited using standard chemical vapor deposition techniques to provide a conformal oxide liner 15 having a thickness of approximately 15 angstroms. After forming the oxide liner 150, standard chemical vapor deposition can be used. Techniques for depositing a tantalum nitride layer to form a tantalum nitride (SiN) layer having a thickness of approximately 75 angstroms. After depositing the tantalum nitride layer, it is exposed to a two-stage etch process to form a tantalum nitride spacer 152. The spacer 152 includes a portion f and a portion of the tantalum nitride layer The oxide seam 15G is contacted. The step (4) removes a portion of the nitride layer, exposing the hard mask 114 and the shihua metal, and the position above the thyristor layer (10) between the stront metal mask word lines 112. The line contact region 200. The second step may involve a fluorine-based excess 〇ver_etch, which reduces the thickness of the perimeter 'I-electricity 122 and 132, and removes the bit line disposed between the word lines m The portion of the top dielectric layer 1 〇 8 exposed in the contact area is fined. Therefore, this excessive step reduces the amount of pre-autogenous clean metal etched by the subsequent removal of the dielectric material and the hard material phase. Pre-self-aligned Shi Xihua metal cleaning side, excessive contact will reduce the oxide liner to the shell 156 and the nitride nitride spacer undercut 154 [the degree of the illusion, these will be from the pre-self-fresh Wei metal Figure 7 shows a cross-sectional view of portion A 60 of memory array 12 and a cross-sectional view of south piezoelectric crystal 70 and low voltage transistor 8A, which have been coated with 1321821 P940263 19224twf.d〇c/〇〇6

The money protecting agent 118 shields the integrated circuit 1 while exposing the peripheral transistors 7A and 80 to the dopant flux 172 to implant the heavily doped source in the high voltage substrate well i2 and the low voltage substrate well 130. And bungee area]42. The p+ and N+ dopant concentrations formed in the heavily doped source and drain regions 142 are higher than the p_ and N- dopant concentrations formed earlier in the LDD source and the drain region 14〇. The source and drain regions 14A and 142 in combination with the substrate wells 120 and 130 can be selectively doped to form a transistor having a P-MOS or N-MOS polarity. The CMOS circuit function of the integrated circuit 10 can be manufactured by using the peripheral transistor thus formed. Reducing the thickness of the voltage "electricity 122 to approximately equal to the thickness of the low voltage dielectric 132 can reduce wafer fabrication by reducing the number of processing steps required to fabricate high voltage and low voltage transistors because of approximately equal dielectrics The thickness allows for the sharing of the patterned mask and the implantation conditions for the heavily doped (P+ and N+), source, and drain regions 142.

After the over-etching, the integrated circuit 1 is protected by the memory array 12 and the patterned photoresist on the other regions, in order to perform the exchange of the source and drain regions of the peripheral transistors 7 and 80. Implanted to expose dielectrics 122 and 132. The type and concentration of the impurities are selected to establish the electric poles and the junctions (_ce _ two ainjunetlGn) associated with the peripheral circuits. During implantation of dopant impurities in the substrate well 12Q to form the deep source junction 142, the gates 24 and 134 protected by the hard mask 114 and their associated nitride spacer spacers function. Figure 8 is not using the pre-self-aligned 11 metal cleaning (four) step for 22 P940263 19224twf doc / 006 to remove the word, line 112, high-reflection m and hard mask 114 on the upper surface of the low-pole 134, and also moved In addition to the drain and the dielectric 122 of the source region M2 and the dielectric 132, the AA cross-sectional view of the memory array 12 of ^=60 and the view of the high-voltage transistor 7〇 and the low-voltage transistor. ^ 1 Pre-self-physitized metal necessary for metal deposition is reduced because the etchant 17 图 in Figure 5 reduces the thickness of the high voltage dielectric ^ 122 to approximately the low voltage dielectric f 132. Therefore, the cleaning step is sufficient to remove the liner loss 156 and the tantalum nitride spacer undercut 154 which are undesirable for the pre-self-aligned metal cleaning required for the exposed dielectric 132. Second, the charge trapping structure in the bit line contact area is also prevented: the material is completely removed, so that the charge is trapped in the remaining portion of the structural material to act as a stone mask. The technique discussed herein discloses that the thickness of the dielectric material 122 is reduced to be similar to the thickness of the "electricity 132" as a pre-self-aligned stone for the preparation of the integrated circuit 10 for shortening the metal sinking. Metal Cleaner 2 3 = Pre-self-cleaning metal cleaning step also reduces the conformal dielectric coating minus! 56 and the nitride nitride spacer undercut 154, and the reduction of the undercut loss of the lining loss will help After the higher quality transistor is fabricated and the dopant impurity is implanted in the non-polar region 142, the execution type Lx removes the hard mask 114 and a portion of the peripheral dielectric Γ 328271 P940263 19224 twf.doc/006 122 and 132 ' to expose the polysilicon Word line 112 and the upper surface of gates 124 and 134, and expose the source and drain regions in substrate wells 120 and 130. In an exemplary process, NH40H: H202: H20 mixture is used' followed by HCL: H202: H20 A mixture of H20: HF solution to complete the etching followed by an isopropanol (IpA) cleaning and drying step.

Figure 9 shows a formation of a deuterated metal such as Shi Xihuaming (CoSi2), Tixi 2 (TiSi2) or the like, a cross-section of the portion 60 of the memory array 12 and a high voltage transistor 70 and A cross-sectional view of the low-voltage crystal 80, in the region of the integrated circuit 10 with a reduced resistance, including a deuterated metal contact 144 on the word line 112 of the memory array 12, a high voltage transistor gate 124, and a voltage The dreaming metal contacts 146 on the transistor gate 134, and the source of the high voltage transistor 70 and the low voltage transistor 80 and the slab metal contacts 148 on the drain region 142. The method further discloses that the (4) metal line deposition on the top dielectric layer (10) is prevented by (4) metal deposition.

A short circuit between the bit lines is formed when the deuterated metal contacts 144, 146, and 148 are aligned. Belonging to the "Evening|cleaning step, it is called "self-aligned Shihuahuajin, and the household is produced in the Wei metal deposition process." In the embodiment, it can be π, 3 矽 to the line 112, the transistor gate 124, and the 134 and ί regions. In the exposed area of the pole/no-pole junction 142, the heat is degraded (4), the deposited domain is converted to Shi Xihua and the (4) Lanlai-covered sedimentary layer is provided, and heat is provided during the period of no-treatment. Sexuality often helps the formation of the metal. 24 1328271 P940263 19224twf.doc/006 This method reveals the deposition that begins on the component that needs to form a self-aligned Shihua gold. Therefore, this party Lin Lu Wei Qianzi in the = = body • continued to choose the most in the region of the wrong by the deposition of the reading exposed to the bow and the beginning of the phase _ combined ^ ^ eve to form a rapid (four) process of cobalt telluride (mail idthe face Lp_ss, RTp forms the Shixi chemical metal. This method also reveals the formation of the anti-cutting metal on the town area: although the sedimentary, but the conversion of the metal will be the electrical path.

Thus, this method exposes the deposition of the inscription and then selectively forms a rapid depletion step of the Shihua metal (which is advantageous in its presence). In the first rapid thermal process, the formation of Wei metal reading is formed. This method exposes the cleaning of non-humans, the cleaning of titanium nitride and other impurities, and the step of insect cutting. Then the second formation of Wei metal is completed. Rapid thermal process steps. The technique discussed in this paper is to form a Shihua metal structure on the word line and the peripheral transistor to improve its performance. Meanwhile, this technique prevents the formation of a stone between the bit line contacts of the memory array. Xihua metal short circuit. _

Cobalt can be deposited to form a layer of about Π〇. A titanium nitride (TiN) cap layer having a thickness of approximately 150 angstroms is then deposited. Next, a rapid thermal process (RTP) is performed by heating the self-aligned deuterated metal at a ramp rate to gradually convert the cobalt and helium to convert it to cobalt telluride. In this manner, the cobalt layer reacts with the yttrium-containing region on which the cobalt layer is deposited to form cobalt telluride (c〇Si). It will be appreciated that other deuterated metals may also be formed in this manner by depositing titanium, arsenic, nickel doped or alloys thereof in a manner similar to that described herein using cobalt. 25 1328271 P940263 19224twf.doc/006 This structure is then subjected to a selective cleaning and rhyme process to remove the TiN cap layer from the one piece structure that does not require the formation of the metal

2: and / quality. For example, the bit line contact region 200 is cleaned in this manner. In an exemplary process, (10) cleaning and etching are performed by applying an SCH liquid consisting of NH4〇h.h2Q2.H2Q followed by application of HF name insects.

The second rapid thermal process performed by self-aligning the deuterated metal by heating the n-aligned metal deposition is then followed by a stepwise heating to induce a phase change. In this way, the surrounding structure of cobalt telluride undergoes a phase change by converting (10) into a desired retardation (C〇Si2) having a resistivity. Figure __ shows the formation of extension through the charge trap The portion of the memory array 12 (9) after the connection of the human structure 110, the germanium diffusion oxide 116, and the interlayer dielectric 160 has no 64 continuation of the connection to the bit line 20 of the memory array 12.

, B-B, c_C, and D_D cross-sectional views. The technique disclosed herein discloses that the self-aligned metal layer 144 is formed on the word line 112 of the integrated circuit 10, and the improper metallization of the bit line contact region 2 is prevented. This creates a short circuit between the subsequent formation of the bit line contact 64 line contact 64.彳兀 Figures 11A-11B show a flow chart of a method in accordance with one aspect of the techniques discussed herein. The sequence is started at 18Q, and the action (10) is used to construct the basic components of the array and the components in the surrounding area, including shallow trench isolation structure (shaii〇w_trench is〇iati〇n stmcture STI), periphery The N-well and P-well and the memory array p-well, as well as the initial integrated circuit 26 1328271 P940263 19224twf.doc/006 10, are formed on the substrate 1 () 0. The other basic boards are usually Shi Xi, but It is a t-conductor substrate such as GaAS or Inp. Act 181 involves the charge of the memory array 12 being trapped into a semi-conducting structure such as oxidized oxidized stone, nitrided stone, and oxidized stone °(〇N〇)°=10 or other charge trapping structures. Act 182 involves stacking a high voltage dielectric m and a thin low voltage dielectric 132. The thickness of the implanted dopant to provide the memory substrate well 83 corresponds to the word line 7^2〇 on the charge trapping structure layer in the memory array 12, forming a peripheral rolling Gate 124 and low voltage gate 134. And '==2, and the formation and patterning of the high voltage transistor 7Q and the low germanium transistor. Act 185 involves coating the "" agent m to protect the memory array 12 and the low voltage transistor = _ worm m ίί using _#U70 to reduce part of the high-power dielectric work 187^ to <, It is approximately equal in thickness to the low-voltage dielectric 132, 5乍7々, and used for high-voltage transistor 7〇's doped deposition. Act 188 involves depositing a material such as a cell and a transistor 70 on the substrate, at the periphery, or at the periphery, or at the periphery. The action 丨89 is involved in the spacer spacer array 12, the interval = 152 and the remaining spacer material in the top layer 108 of the structure is exposed to the charge in the line contact region 2 〇 0, and the charge is trapped in the 189 also involves the nitrogen and the middle to the charge trap. Layer.106. Actuating the germanium spacer material to form spacers 152 on the peripheral transistor 70 and 27 1328271 P940263 19224twf.doc/006 80 to remove at least the dielectric structure 122 and a portion of the spacer 150 to expose the source And the bungee area. Act 190 involves the implantation of a dopant in the high voltage transistor 70 and the low voltage transistor 8 and the N: source and drain region 142, where appropriate, between the (four) and the low pressure secret implant. Fine and immersive masking and implantation conditions to reduce the number of manufacturing steps. The action M1 involves a pre-stone forming metal cleaning step, which is performed from the word line 112 and the transistor electrode 124, 1 = the hard mask 114 is removed, and the plasma source of the periphery of the valve and the emitter region 142 are also introduced. The exposed portions of electrical structures 122 and 132. 192 relates to the formation of a self-aligned de-crater metal layer on the word line 112 and the formation of a self-aligned Wei metal transistor gate layer 146 on the south cell transistor gate 124 and the low voltage transistor cell 134. The shape of the self-aligned metallization layer 148 on the pole and drain regions 142 = the original action 193 involves the sinking of the dielectric structure (10) and the placement of the inter-layer dielectric structure 16G and the charge trapping structure 110 The bit in the channel == into. In the bit line contact region 200, there is no Shihua gold (4) to prevent a bit line short circuit between the bit line contacts 64. Potgan's techniques include making arrays of charge trapping memories and changing methods. This method reduces the resistance of the sub-wires by self-aligning deuteration metallization while preventing the improper connection between the bit lines ("the early morningization to the small size of the recording period _^^) Providing a capacitor with a reduced charge trapping the memory array requires a peripheral circuit including a transistor capable of operating at a high voltage and a crystal capable of = voltage = 28 j-JZ0//1 j-JZ0//1 19224 twf.doc/006 P940263. The thickness of the gate oxide is made according to its operation so that the piezoelectric crystal has a thicker, =emulsion relative to the low voltage transistor. This method reduces the overlap between the upper and lower layers of the high voltage transistor. In the secret area, the thickness is near (four) with the thickness of the closed-end pole while maintaining a thicker gate dielectric. This method uncovers the source and the Sir: the thickness of the dielectric adjacent to the source and the pre-self-aligned stone cleaning step. By providing the length of the pre-self-aligned Wei metal cleaning step below the spacer, and the intervening material, the conformal dielectric coating loss that occurs during the fabrication of the wafer is due to & It is necessary to reduce the oxide loss and the amount of undercut. Special: Zone HitT enters the memory array and the small oxide of the peripheral circuit = and the degradation of the transistor performance. Improve memory and wafer performance by subtracting (d) and undercutting. The invention has been disclosed in the preferred embodiments as described above, but it is not intended to be used in the context of the invention, and the present invention is protected and modified without departing from the spirit of the invention. [The diagram simply states that the scope defined by the patent is subject to change. The circuit "" is trapped in the memory array and other circuits, the body array charge is trapped in the virtual ground memory of the memory device. Figure 3 shows the virtual ground memory of the memory chip. 29 1328271 P940263 19224twf.doc/ 006 A partial layout or plan view of the array. Figures 4A-4C show cross-sectional views along lines AA, BB, and CC of Figure 3 after forming memory cell word lines and a cross-sectional view of the peripheral transistor after forming its gates. A cross-sectional view along line aa of FIG. 3 after protecting the memory cell and a cross-sectional view of the peripheral transistor illustrating the gate oxide etching step.

Figures 6A-6B show cross-sectional views along line aa of Figure 3 and cross-sectional views of the peripheral transistor illustrating the dielectric coating and spacer etching steps. Figure 7 is a cross-sectional view along line aa of Figure 3 after protection of the memory cell and a cross-sectional view of the peripheral transistor illustrating the dopant implantation step for forming the source and drain regions. Figure 8 is a cross-sectional view showing the pre-deuterated metal deposition cleaning step, along the cross-sectional view SUX and the peripheral transistor of Figure 3; For example, ^9 is a cross-sectional view showing the self-aligned Wei metal deposition, along the line AA of Fig. 3, and the peripheral transistor.

_^A_1C)D shows a cross-sectional view of the self-aligned Wei metal deposition and the line AA, ― and - of the bit line: the flow _ of the method. 'Read the side of the technique discussed in this article [Main component symbol description] 10 Integrated circuit 12 Memory array 14 Word line decoder 16 Word line 30 1328271 P940263 19224twf.doc/006 18 : Bit line decoding 20: bit line 22: address line 24: data input and data output structure/block 26: data bus 2 8 . tributary input bus 30: other circuits

32: data output bus 34: controller 3 6. power supply voltage electric 50: schematic 60: part 62: memory unit 64: bit line contact 70: high voltage transistor / peripheral transistor 80: low voltage Transistor/peripheral transistor

100: substrate 102: memory substrate well 104: bottom dielectric layer 106: middle charge trapping layer 108: top dielectric layer 110: charge trapping structure/charge trapping material layer 112: word line 114: hard mask 1328271 P940263] 9224twf .doc/006 116. Oxide structure/embedded diffusion oxide 118: protection against residual agent 120: high voltage substrate well 122: high voltage dielectric 124: high voltage transistor gate / peripheral transistor gate / peripheral electricity Crystal Control Gate 126. South ["Electrical Structure/South Piezoelectric Gate Gate Dielectric/Transistor Interpolar Dielectric Region'

130: low-voltage substrate well 132. transistor low-voltage dielectric 134: low-voltage transistor gate / peripheral transistor gate / peripheral electro-crystal gate 136. low-voltage dielectric structure / low-voltage transistor gate dielectric /Transistor dielectric region 140: LDD source and drain region 142. heavily doped source and drain region/source and drain junction

H4: Shi Xihua metal joint / self-aligned Shihua metal joint / self-aligned metal layer is all 1 electric 46 days no / self-material Wei metal joint / self-aligned Shi Xihuan electricity day极极层金属Γ: Money gold secret point / self-aligned Wei metal fine self-aligned Shi Xihua 15 〇: oxide liner 152. tantalum nitride spacer / dielectric spacer material layer 32 1328271 P940263 19224twf.doc /006 154: Tantalum nitride spacer/tantalum nitride spacer undercut 156: oxide liner/oxide liner loss/isoelectric dielectric coating loss 160: interlayer dielectric 17 0: residual agent 172 : dopant flux 180, 18 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193: action 200: bit line contact area

Claims (1)

1328271 P940263 19224twf.doc/006 X. Patent Application Range: 1. A method of fabricating a memory component and a peripheral circuit on a substrate, the method comprising: forming a multilayer charge trapping structure on a first region of the substrate, The multilayer charge trapping structure has a first thickness and includes a top layer of dielectric, a bottom layer of dielectric, and one or more charge trapping layers between the top layer and the bottom layer; forming a second region on the second region of the substrate a first gate dielectric layer having a thickness; a second gate dielectric layer having a third thickness formed on the third region of the substrate, wherein the third thickness is greater than the second thickness; 1. depositing and patterning a gate material on the second and third regions to define word lines in the first region and transistor gates in the second and third regions; Selectively etching to reduce a thickness of the second gate dielectric layer in a region adjacent to the gate to a thickness having approximately the second thickness; via the second and third gate dielectric layers With the second as well The gate in the third region is aligned to implant dopants for forming source and drain regions in the second and third regions; in the first, second, and third regions Depositing a dielectric spacer material on the word line and the gate; etching the dielectric spacer material to form a sidewall spacer on the word line and the gate, and exposing the bit line contact region in the first region The 34 1328271 P940263 19224twf.doc/006 the first and the second dielectric layer in the region of the sidewall spacer; the mysterious (four) is aligned with the spacer and implanted with the dopant for use in the second and Forming a source and a drain region in the second region; 夂": etching the first and the second gate dielectric layer to expose the substrate in the first and third regions adjacent to the side (four) spacer, j exposing the word line and the gate in the first and third regions without exposing the substrate in the contact region of the bit line; and supporting, in: and in the third region On the substrate exposed on the source "domain of the sidewall spacer" and in the first -, second - ir r The word _ and the gate on the county turn metal. The peripheral electrode 1 is fabricated in the memory element and the word line in the gate region and the material in the second and third regions are covered in the dielectric, the word in the third region The material cover is removed before the line is shaped with the gold. The peripheral memory 1 package includes the manufacturing memory component and the material in the idler and the second and the third region: the material is covered in the medium And the word line in the third region: the word line in the region and the 35 1328271 P940263 19224 twf.doc/006 removing the dielectric during the selective etching of the first and the second gate dielectric layers An electrical material cap to expose source and drain regions in the substrate in the second and third regions adjacent to the sidewall spacers. 4. The method of manufacturing a memory device and a peripheral circuit according to claim 1, further comprising: forming on the word line in the first region and the gate in the second and third regions An interlayer dielectric; and a bit line contact through the interlayer dielectric in the bit line contact region of the first region. 5. The method of manufacturing a memory device and a peripheral circuit according to claim 1, wherein the charge is trapped in the top layer of the dielectric in the structure, the gate dielectric in the second region, and the The gate dielectric in the third region includes yttrium oxide. 6. The method of manufacturing a memory device and a peripheral circuit according to claim 1, wherein the charge is trapped in the top layer of the dielectric in the structure, the gate dielectric in the second region, and the The gate dielectric in the third region includes ruthenium oxide, and the method further comprises: forming an oxide oxide in the word line in the first region and the gates in the second and third regions a cover, wherein the cover protects the word line in the first region and the gates in the second and third regions during the etching of the dielectric spacer material; and in the first and the first The cap is removed during the selective etch of the two gate dielectric layers to expose source and drain regions in the substrate in the second and third regions adjacent to the sidewall spacers. The method for manufacturing a memory device and a peripheral circuit according to claim 1, further comprising: before depositing the dielectric spacer material, at the first Forming a dielectric roughness on the word line in the region and the gates in the J1 and the third region and removing at least a portion of the dielectric pad during the etching of the dielectric spacer material to A 'side wall spacer is shaped in the area covered by the sidewall spacer. 8. The device as claimed in claim 3, wherein the gate dielectric and the third region of the first region of the dielectric in the charge trapping structure are The dielectric material includes ruthenium oxide, and the method further comprises: before depositing the dielectric spacer material, forming a cash-cut liner on the first region and the second slanting region At least a portion of the oxygen lining is removed with a chemical field = dielectric spacer material to cover the sidewall spacers without the sidewall spacers. Feng Xi Zhou, hi t _ 4 specializes in her 81 first pin-shaped manufacturing record (four) components and the method of the genus road 'the towel forming scaled metal including self-aligned Wei Jin 10.-the integrated circuit, including: the substrate a memory array in the first region, the memory array comprising: a plurality of word lines of an electrical material, the conductive material comprising a Wei metal layer; L comprising a plurality of layers of the doped substrate region; ^, 1328271 P940263 19224twf .doc/006 The memory unit package (4) the source of the multi-recorded wire towel such as the money pole region and a multi-layer charge trapping structure, the multilayer charge trapping structure has a first thickness, and includes a dielectric top layer, dielectric a bottom layer and one or more charge trapping layers between the top layer and the bottom layer; 层^ an interlayer dielectric layer overlying the memory array and a conductor structure; a plurality of line contact points at the word lines In the middle of the word line group, the layer in the zone, the electrical structure connects the conductor structure to the bit lines = the interlayer dielectric between the material overlying the bit line contacts = and the substrate On the electricity (four), it has a second thickness of the dielectric layer; on the beta substrate Crystal 'which is greater than the third thickness wherein the second thickness. The gate dielectric layer of X, 11· If the first dielectric layer of the first inter-electrode layer includes the dielectric, the third dielectric gate of the transistor J, 5 a gate of the wall spacer, including: one of the dielectric material of the dielectric side of the dielectric side; the dielectric sidewall spacer has a bottom surface, and between the substrates, the evil; 4' position (four) The "bottom of the bottom surface and the layer of sorrow is approximately equal to the second thickness. 38