1324881 九、發明說明： 【發明所屬之技術領域】 本發明提供一種資訊接收器，尤指一種包含有一密碼認證卡 模組和一外部記憶體之數位電視系統，.其中該密碼認證模組之位 址和資料接腳係耦接至該外部記憶體之位址和資料接腳以減少所 使用的接腳數目。 【先前技術】1324881 IX. Description of the Invention: [Technical Field] The present invention provides an information receiver, and more particularly to a digital television system including a password authentication card module and an external memory, wherein the password authentication module is located The address and data pins are coupled to the address and data pins of the external memory to reduce the number of pins used. [Prior Art]
在數位有線電視系統中，視訊/音訊内容被一種條件式存取攪 碼系統（conditional access scrambling system)所保護著。密碼認 證卡模組，例如美國高等數位電視委員會(advanced Tdevisi〇ns Systems Committee，ATSC)所制訂的部署點(point 〇fDepl〇yment， POD)女全模組(現稱為有線卡，亦即CabieCARD)或是數位電視廣 播共同介面(Digital Video Broadcasting Common Interface，DVB-CI)In digital cable television systems, video/audio content is protected by a conditional access scrambling system. Password authentication card module, such as the deployment point (point 〇fDepl〇yment, POD) female full module developed by the Advanced Tdevisi〇ns Systems Committee (ATSC) (now called the cable card, also known as CabieCARD) ) or Digital Video Broadcasting Common Interface (DVB-CI)
CPU 模組’其可以在電視内容經由—個介㈣密碼認證卡模組和該主 機裝置介面傳送· f者之接收機和機上㈣機(亦即主機 裝置)之前’對電視内容進行移除攪碼或重新授碼的動作。該密碼 認證^模組具有—可以和社機較之巾域理單元通訊之中央 處理草位介面_ inteffaee)，此外，^缝置料常和周邊裝 置或外部記憶體（例如唯讀記憶體或快閃記憶體)連結來 、 之指令或進行資料儲存。 ^ 10的示意圖。數位電 明參照第I圖，其為習知數位電視系統 7 視系統10包含有一主機前端積體電路（front-endic) 20、一主機 後端積體（back>end 1C) 30以及一p〇D模組50。主機前端積體 電路20連接到一有線信號源，用來處理該有線信號源所提供的視 訊/音訊内容，主機前端積體電路20包含有一傳送電路24以及一 接收電路26，用來與POD模組50之一帶外埠(out-of-band port)OOB進行通訊。該視訊/音訊内容也傳送到一諧調器電路 (tuner circuit) 22，然後進入一解調變器電路28 ’解調變器電路 28可移除視訊信號中的載波’並把得到的結果經由直接發送到主 機後端積體電路30中一多工器32和POD模組50中一帶内棒 (Inband p〇rt)INB，其中該結果乃經由一第一傳輸流槔TS1發送至 解多工器32。POD模組50可對視訊信號進行解攪碼 (descramble) ’並將解攪碼後的視訊信號流經由一第二傳輸流埠 TS2傳送到解多工器32。 主機後端積體電路30包含有一 p〇D CPU介面34，其可透過 POD模組50中-CPU介面來和咖觀％進行位址和資料訊 息的通訊’主機後端積體電路3〇另具有一外部記憶體介面％，其 賴過-位址和資料匯流排45來和外部記髓以及周邊裝置進行 通訊，其中該外部記憶體可供主機後端積體電路3〇儲存指令或資 料。如第1圖所示’外部記憶體介面36可以和—快閃記憶體如、 一唯讀記憶體42以及周邊裝置44進行通訊。 然而’數位電視系統H)需要大量的接腳來滿足連接這些不同 丄汹881 設備的需求，例如，在數位電視系統10中，儘管p〇D cpu介面 34可能不常和P0D模組5〇進行通訊两外部記憶體介面％亦不時 常存取外部記憶體40、42和周邊裝置44，然而，它們之間的每一 個連結卻都需要一組專屬的位址和資料接腳。此外，解多工器％ 至少使用兩個傳輸流璋TS1、TS2來接收傳輸流㈣，而傳輸流淳 TS1、TS2係各自使用多個接腳，此亦增加主機後端積體電路％ 所使用的接腳總數，而大量接觸使用會提高主機後端積體電路 3〇的製造成本’增加主機後端積體電路3〇的連接點數目，並使得 主機後端積體電路30的設計更加困難。The CPU module 'can remove the TV content before the TV content is transmitted via the (4) password authentication card module and the host device interface to the receiver and the onboard (four) machine (ie, the host device). The action of stirring or re-encoding. The password authentication module has a central processing grass interface (inteffaee) that can communicate with the social media unit, and in addition, the device is often connected to peripheral devices or external memory (such as read-only memory or Flash memory) links instructions, or stores data. ^ 10 schematic. Referring to Figure 1, a conventional digital television system 7 system 10 includes a host front-endic 20, a host backend (back > end 1C) 30, and a p〇 D module 50. The host front end integrated circuit 20 is connected to a wired signal source for processing the video/audio content provided by the wired signal source. The host front end integrated circuit 20 includes a transmitting circuit 24 and a receiving circuit 26 for interacting with the POD module. One of the groups 50 has an out-of-band port OOB for communication. The video/audio content is also transmitted to a tuner circuit 22, and then into a demodulation circuit 28 'demodulation circuit 28 to remove the carrier in the video signal' and pass the result directly And sent to a multiplexer 32 in the host back end integrated circuit 30 and an inband p〇rt INB in the POD module 50, wherein the result is sent to the demultiplexer via a first transport stream TS1 32. The POD module 50 can descramble the video signal and transmit the descrambled video signal stream to the demultiplexer 32 via a second transport stream TS2. The host back end integrated circuit 30 includes a p〇D CPU interface 34, which can communicate with the address and data information through the CPU interface of the POD module 50. The host back end integrated circuit 3 There is an external memory interface %, which relies on the address and data bus 45 to communicate with the external memory and peripheral devices, wherein the external memory can be used by the host back end integrated circuit 3 to store instructions or data. As shown in FIG. 1, the external memory interface 36 can communicate with the flash memory, such as a read only memory 42 and peripheral devices 44. However, the 'digital TV system H' requires a large number of pins to meet the needs of connecting these different 881 devices, for example, in the digital television system 10, although the p〇D cpu interface 34 may not often be performed with the P0D module 5 The external memory interface % of the communication also occasionally accesses the external memory 40, 42 and the peripheral device 44. However, each connection between them requires a unique set of address and data pins. In addition, the demultiplexer % uses at least two transport streams TS1, TS2 to receive the transport stream (4), and the transport streams TS1, TS2 each use a plurality of pins, which also increases the use of the host back end integrated circuit % The total number of pins, and a large number of contact uses will increase the manufacturing cost of the host back-end integrated circuit 3', increase the number of connection points of the host back-end integrated circuit 3, and make the design of the host back-end integrated circuit 30 more difficult. .
【發明内容】 本發明提供—種触電視祕。域本發明之—實施例，一 數位電視系統包含：-前端電路，其具有—解調器電路，用來產 生-未解碼的傳輪流信號；_後端電路，用來解碼傳輸流資料； 一外部記髓，後端電路；—佩隨排；—資料匯流 排’其中該外部記舰猶過位址接腳和㈣接_接至該位址 匯流排和該資龜流排；1戦、證卡模組(¥。_则蝴， 耗接至該前猶路和雜端電路，用來解碼傳輸流簡產生-已 解碼的傳輸流域’以及用來進行條件式存取及安全防護功能， 其中該密碼襲卡模組具有位簡贿龍麟分難接至該外 部記憶，之位址接腳和資料接腳；以及—碰手段，用來切換選 ，將知端電路產生之該未解碼的傳輸流信號歧該密碼認證卡 產生之。紀解碼⑽輸流信號輸人至該後端電路。 9 1324881 依據本發明之另一實施例，一數位電視系統包含：-前端電路’ : 其具有—輸人_雜祕料_見喊料L卜傳輸流信號 - 以及—解調器電路用來產生—帶内傳輸流信號；-後端電路，用 來解碼傳輸流資料；-外部記憶體，輕接於該後端電路；一位址 [机排，> 料匯流排’其中該外部記憶體係透過位址接腳和資 料接腳輕接至触址匯流排和該資贿流排；—密碼認證卡模 組，用來進行餅式雜及安缝護舰，贿碼雛卡模組具 • 有位址接腳與資料接腳分_接至該外·部記憶體之位址接腳和資 料接腳；以及一切換手段’用來切換選擇將該前端電路產生之該 帶外傳輸流信號或是該密碼認證卡模組產生之該帶内傳輸流信號 輸入至該後端電路。 【實施方式】 請參照第2圖，其本發明資訊接收器（例如數位電視系統1〇〇) • 之第一實施例的功能方塊圖。如同第1圖所示之數位電視系統 1〇數位電視糸統1〇〇包含有一第一主機前端積體電路11〇、一主 機後端積體電路120以及一密碼認證卡模組14〇。第一主機前端積 體電路110可為-個和第1圖所示之主機前端積體電路2〇相同或 相似的電路，並至少包含一解調變器電路，用來移除自一有線信 號源所接收之視訊信號十的載波。 密碼認證卡模組140包含一 CPU介面，用來和主機後端積體 id 電路120進行通訊，該CPU介面可發送資料信號、位址信號以及 控制信號’因為主機後端積體電路120僅是偶爾存取密碼認證卡 模組140、外部記憶體40、42以及周邊裝置44，所以在密碼認證 卡模組140、外部記憶體40、42以及周邊裝置44之間共享同一 位址與資料匯流排是可行的。 如第1圖中所示之主機後端積體電路30，主機後端積體電路 120亦包含一解多工器122’用來對視訊/音訊資料進行分工，並將 來自第一主機刖端積體電路110和密碼認證卡模組140之傳輸流 層的資訊（transport stream layer information)進行解碼。然而，不 同於主機後端積體電路30的是：主機後端積體電路12〇包含一密 碼認證卡控制器128、一外部記憶體控制器丨26、一接腳多工器（pin multiplexer) 130以及一裁決器（arbiter) 124。密碼認證卡控制器 128係控制密碼認證卡模組14〇的存取·，而外部記憶體控制器 則控制記舰4G、42錢周邊裝置44畴取。當密碼認證卡控 制器128或外部記憶體控制器126需要對位址及資料匯流排衫進 行存取時，其便對裁決器124發出請求，裁決器】24會決定密碼 過證卡控制器！28和外部記憶體控制器126中那一個可以獲得位 址及資料匯流排45的存轉，並控讎腳多n3()選擇密碼認 證卡控制i 128餅部記顏控繼126來取得位址或資料。 欲碼認證卡控制器14〇可操作於一第一模式(p〇D模式)或一 第模式(PCMCIA模式)之令一間始時，密碼認證卡模组】如 «處於PCMCIA模式’並經由接腳仲裁（pin arbitration)的方式， 透過共享出來的位址及資料接腳來允許主機後端積體電路12〇存 取密碼認證卡模組140、外部記憶40和42以及周邊裝置44。當 主機後端積體電路120把密碼認證卡模組140設為p〇D模式後， 部分PCMCIA模式下的位址接腳，例如A4〜A9和A14〜A25，會 被用來傳送傳輸流資料、條件式存取信息（c〇nditi〇nal access message)或數位電視系統100的網路管理信息。為了使同一位址 接腳可以操作在POD和PCMCIA兩種模式之下，數位電視系統 1〇〇採用三態（tri-state)緩衝器150A〜150D、152A〜152C和一用 來控制三態緩衝器150A〜150D、152A〜152C的控制信號ENP0D， 其中當控制信號ENPOD的邏輯值為‘1’時，高致能式 (active-high)三態緩衝器1S0A〜1S0D處於一致能狀態而低致能 式（active-low)三態緩衝器152A〜152C則處於一高阻抗狀態，反 之亦然。 S在、碼認證卡模組140處於PCMCIA模式，控制信號 ENPOD的邏輯值為‘〇’ ，此時位址及資料匯流排45的位址接腳 A0〜A25和資料接腳D0〜D7可由外部記憶體40、42和周邊裝置 44所共享，而當密碼認證卡模組14〇處於p〇D模式，控制信號 ENP0D的邏輯值則為T，部分的位址接腳(A4〜A9和A14〜A25) 會和該外部記憶體位址匯流排分離。在第2〜4圖中，短直線表示 密碼認證卡模組140處於PCMCIA模式下的信號路徑，如連接位 址及資料匯流排45和密碼認證卡模組14〇令CPU埠的線；點直 1324881 線則表示密碼認證卡模組140處於POD模式下的信號路徑，如連 • 接第一主機前端積體電路110和密碼認證卡模組140中帶内埠 : (Inbandρ_ινβ的線；虛線則表示控制信號ENP0D的路徑。 當密碼認證卡模組140處於PCMCIA模式，解多工器122直 接地接收來自第一主機前端積體電路n〇内解調變器的傳輸流； 而在密碼認證卡模組140.處於P0D模式時，接收來自密碼認證卡 模組140的傳輸流。三態緩衝器15〇A〜15〇D、152A〜152C則用來 鲁 控制傳輸流的傳遞’請注意，三態緩衝器150A〜150D、152A〜152C 也可以用切換開關、多工器或其它相似的可控制裝置來加以取代。 第2圖所示之數位電視系統1〇〇係符合美國高等數位電視系 統委員會(Advanced Televisions Systems Committee, ATSC)規格之 數位電視系統的一種實施例。請注意，數位電視系統1〇〇也可以 修改為適用數位電視廣播系統(Digitai vide〇 Br〇adcasting, DVB)規 φ 格的系統，因此，密碼認證卡模組Η0可以是符合ATSC規格的 POD/CableCARD模組，也可以是符合DVB規格的共同介面 (Common Interface，α)模組’其可用來進行條件式存取和安全防護 的功能，以允許選擇性地存取數位有線服務。 當帶外控制訊號從第一主機前端積體電路11〇經由三態緩衝 斋150傳至保密卡模組丨4〇時，會先被轉換成傳輸流封包㈣叩⑽ stream packet),之後再被送到解多工器】22做處理，該帶外訊號 1324881 可能包含各種不同的MPEG資料區段(MPEG sections)，例如節目 表清單(program guide tab丨e)、系統資訊表(system information table) 以及含有EMM、ECM、PAT以及PMT訊號的保密卡表(crytocard table)。數位電視系統loo並不使用CPU介面來分工處理這些 MPEG資料區段或進行版本控管(versi〇n contr〇l) ’相反地，由於解 多工器122内建有的資料區段過滤硬體.（section filtering hardware) 來處理MPEG資料區段’因此數位電視系統100便將這些MpEG 資料區段送到解多工器122。除此之外，由於該帶外訊號很可能被 轉換成傳輸流封包’因此可與第二主機前端積體電路18〇傳進的 傳輸流進行分工。第二主機前端積體電路18〇與第一主機前端積 體電路110類似’可選擇性地提供另一個傳輸流給後端積體電路 120，例如’第二主機前端積體電路18p可在子母晝面⑼cture出 Picture，PIP)模式或分割晝面(picture outside picture, POP)模式下展 示第二組視訊資料。如果第二主機前端積體電路18〇被使用，一 個以上的多工器190便會提供一種在第—主機前端積體電路11〇 以及第二主機前端積體電路180提供的傳輸流之間進行轉換的機 制。雖然於最佳實施例中使用的是多工器190，但三態緩衝器或其 他形式的轉換器也可被使用。在本實施例中，多工器同樣是SUMMARY OF THE INVENTION The present invention provides a touch television secret. In a preferred embodiment of the present invention, a digital television system includes: a front end circuit having a demodulator circuit for generating an undecoded transport stream signal; a back end circuit for decoding transport stream data; External memory, back-end circuit; - Pei-sui; - data bus - 'The external record ship is still over the address pin and (4) connected to the address bus and the turtle flow row; The card module (¥. _ butterfly, consumed to the front of the road and the miscellaneous circuit, used to decode the transport stream generation - the decoded transport basin) and for conditional access and security protection, The password attack card module has a bit of a bribe and is not connected to the external memory, the address pin and the data pin; and the touch means is used to switch the selection, and the unknown circuit generates the undecoded The transport stream signal is generated by the cryptographic authentication card. The video decoder (10) is input to the back end circuit. 9 1324881 According to another embodiment of the present invention, a digital television system includes: - front end circuit ': - lose people _ miscellaneous materials _ see shouting L Bu transport stream signal - and - the demodulator circuit is used to generate - in-band transport stream signals; - the back-end circuit is used to decode the transport stream data; - the external memory is lightly connected to the back-end circuit; the address is [machine row, > The material bus bar 'where the external memory system is lightly connected to the address bus and the bribe flow row through the address pin and the data pin; the password authentication card module is used for the cake type and the seam protection Ship, bribe code card module • There are address pins and data pins _ connected to the address pins and data pins of the external memory; and a switching means 'used to switch the selection The out-of-band transport stream signal generated by the front-end circuit or the in-band transport stream signal generated by the cryptographic authentication card module is input to the back-end circuit. [Embodiment] Referring to FIG. 2, the information receiver of the present invention ( For example, the digital television system 1)) is a functional block diagram of the first embodiment. As shown in FIG. 1, the digital television system 1 〇 digital television system 1 〇〇 includes a first host front end integrated circuit 11〇, a host back end integrated circuit 120 and a password authentication card module 14. The first host front end integrated circuit 110 may be the same or similar circuit as the host front end integrated circuit 2 shown in FIG. 1 and includes at least one demodulator circuit for removing The carrier of the video signal received by a wired signal source. The password authentication card module 140 includes a CPU interface for communicating with the host back end integrated id circuit 120, and the CPU interface can transmit the data signal, the address signal, and The control signal 'because the host back end integrated circuit 120 only occasionally accesses the password authentication card module 140, the external memory 40, 42 and the peripheral device 44, so in the password authentication card module 140, the external memory 40, 42 and It is feasible to share the same address and data bus between peripheral devices 44. As shown in Fig. 1, the host back end integrated circuit 30, the host back end integrated circuit 120 also includes a demultiplexer 122' The video/audio data is divided, and the transport stream layer information from the first host integrated circuit 110 and the password authentication card module 140 is decoded. However, unlike the host back end integrated circuit 30, the host back end integrated circuit 12 includes a password authentication card controller 128, an external memory controller 26, and a pin multiplexer. 130 and an arbiter 124. The password authentication card controller 128 controls the access of the password authentication card module 14〇, and the external memory controller controls the recorder 4G and 42 peripheral devices 44. When the password authentication card controller 128 or the external memory controller 126 needs to access the address and the data bus, it issues a request to the arbiter 124, and the arbiter 24 determines the password card controller! 28 and the external memory controller 126 can obtain the address and the data bus 45 storage, and control the foot more than n3 () select the password authentication card control i 128 cake department control 126 to obtain the address Or information. If the code authentication card controller 14 is operable in a first mode (p〇D mode) or a first mode (PCMCIA mode), the password authentication card module is in the "PCMCIA mode" and is via In the manner of pin arbitration, the host backend integrated circuit 12 is allowed to access the password authentication card module 140, the external memories 40 and 42 and the peripheral device 44 through the shared address and data pins. When the host backend integrated circuit 120 sets the password authentication card module 140 to the p〇D mode, some of the address pins in the PCMCIA mode, such as A4~A9 and A14~A25, are used to transmit the transport stream data. The conditional access information (c〇nditi〇nal access message) or the network management information of the digital television system 100. In order to enable the same address pin to operate under both POD and PCMCIA modes, the digital television system 1 employs tri-state buffers 150A-150D, 152A-152C and one for controlling tri-state buffering. The control signals ENP0D of the devices 150A to 150D, 152A to 152C, wherein when the logic value of the control signal ENPOD is '1', the active-high tristate buffers 1S0A to 1S0D are in a uniform state and are low The active-low tristate buffers 152A-152C are in a high impedance state and vice versa. S, the code authentication card module 140 is in the PCMCIA mode, and the logic value of the control signal ENPOD is '〇'. At this time, the address pins A0 to A25 and the data pins D0 to D7 of the address and data bus 45 can be externally The memory 40, 42 and the peripheral device 44 are shared, and when the password authentication card module 14 is in the p〇D mode, the logic value of the control signal ENP0D is T, and some of the address pins (A4~A9 and A14~) A25) will be separated from the external memory address bus. In the second to fourth figures, the short straight line indicates the signal path of the password authentication card module 140 in the PCMCIA mode, such as the connection address and the data bus 45 and the password authentication card module 14 to block the CPU line; The line 1324881 indicates that the password authentication card module 140 is in the signal path in the POD mode, such as the line connecting the first host front end integrated circuit 110 and the password authentication card module 140: (Inbandρ_ινβ line; the dotted line indicates The path of the control signal ENP0D. When the password authentication card module 140 is in the PCMCIA mode, the demultiplexer 122 directly receives the transport stream from the demodulator in the first host front end integrated circuit n;; Group 140. When in the P0D mode, the transport stream from the password authentication card module 140 is received. The tristate buffers 15A to 15D, 152A to 152C are used to control the transmission of the transport stream 'Please note that the three states The buffers 150A to 150D, 152A to 152C may also be replaced by switch switches, multiplexers or other similar controllable devices. The digital television system shown in Fig. 2 conforms to the American High Digital Television System Committee ( A An example of a digital television system of the dvanced Televisions Systems Committee, ATSC) specification. Note that the digital television system can also be modified to a system for digital television broadcasting systems (Digitai vide〇Br〇adcasting, DVB). Therefore, the password authentication card module Η0 can be an ATSC-compliant POD/CableCARD module, or a DVB-compliant Common Interface (α) module that can be used for conditional access and security protection. The function is to allow selective access to the digital cable service. When the out-of-band control signal is transmitted from the first host front end integrated circuit 11 via the tri-state buffer 150 to the security card module 丨4〇, it is converted first. The stream packet is sent to the demultiplexer 22, and the out-of-band signal 1324881 may contain various MPEG sections, such as a list of programs. The guide tab丨e), the system information table, and the crytocard table containing EMM, ECM, PAT, and PMT signals. The digital television system loo does not use the CPU interface to divide and process these MPEG data segments or perform version control (versi〇n contr〇l). Conversely, due to the data segment filtering hardware built in the demultiplexer 122 (section filtering hardware) to process the MPEG data section 'so the digital television system 100 sends these MpEG data segments to the demultiplexer 122. In addition, since the out-of-band signal is likely to be converted into a transport stream packet, it can be divided into a transport stream that is transmitted from the second host front-end integrated circuit 18. The second host front end integrated circuit 18 is similar to the first host front end integrated circuit 110. 'Optionally providing another transport stream to the back end integrated circuit 120. For example, the 'second host front end integrated circuit 18p can be in the sub The mother's face (9) is shown in the Picture, PIP mode or the picture outside picture (POP) mode to display the second set of video data. If the second host front end integrated circuit 18 is used, more than one multiplexer 190 provides a flow between the first host front end integrated circuit 11A and the second host front end integrated circuit 180. The mechanism of conversion. Although multiplexer 190 is used in the preferred embodiment, a tristate buffer or other form of converter can be used. In this embodiment, the multiplexer is also
由控制三態緩衝器150A〜150D、152A〜152C的控制訊號ENPOD 所控制。It is controlled by the control signal ENPOD which controls the tristate buffers 150A to 150D, 152A to 152C.
凊參照第3圖’第3圖係為在多個輸入訊號間進行選擇之複 數個多工器】90的示赛圖。多工器】9〇Α可選擇一控制訊號DRX 1324881 或-帶内資料域.data ’其中㈣訊號的傳輸形式可為序列 - (seriaD傳輸或平行(parallel)傳輸；多工器190B可選擇—控制气號 • CRX或一帶内時間訊號CLOCK ;多工器19〇c以及多工工器二d • 可分別傳輸一帶内有效性指令VALID以及一帶内同;訊號 SYNC;多工器190C如果被使用，其便會選擇一預設值，，丨，，或一 ^ 内有效指令VAWD，而多玉器19GD則選擇-預設值，，〇，，或—帶内 同步訊號SYNC。 • 請參照第4圖，第4圖是本發明資訊接收器（如數位電視系統 200)之第二實施例的功能方塊圖。數位電視系統2〇〇是一單一晶 片方案，其主機積體電路210是單一晶片，而非分離的前端、後 端積體電路。為了最佳化所需的接腳數，密碼認證卡控制器128 與外接記憶體40、42以及周邊裝置44共享位址接腳α〇·Α3、 Α10-Α13以及資料接腳D0_D7。密碼認證卡控制器128與複數個 訊號 MDI0〜MDI7、MIVAL、MICLKI、MISTRT 共享位址接腳Referring to Figure 3, Figure 3 is a representation of a plurality of multiplexers 90 selected between a plurality of input signals. Multiplexer] 9〇Α can select a control signal DRX 1324881 or - in-band data field.data 'where (four) signal transmission form can be sequence - (seriaD transmission or parallel transmission; multiplexer 190B selectable - Control air number • CRX or one-band time signal CLOCK; multiplexer 19〇c and multi-engineer two d • can transmit a band internal validity command VALID and a band internal; signal SYNC; multiplexer 190C if used , it will select a preset value, 丨,, or a valid command VAWD, and the multi-jade 19GD selects the preset value, 〇,, or - the in-band sync signal SYNC. • Please refer to the 4th Figure 4 is a functional block diagram of a second embodiment of an information receiver (e.g., digital television system 200) of the present invention. The digital television system 2 is a single wafer scheme, and the host integrated circuit 210 is a single wafer. Instead of separate front-end and back-end integrated circuits, the password authentication card controller 128 shares the address pins α〇·Α3 with the external memory 40, 42 and the peripheral device 44 in order to optimize the number of pins required. Α10-Α13 and data pin D0_D7. Password recognition Card controller 128 and a plurality of signal MDI0~MDI7, MIVAL, MICLKI, MISTRT shared address pins
A15〜A25 ’ 其中訊號 MDI0〜MDI7、MIVAL、MICLKI、MISTRT 係預定將從主機積體電路21〇的解調變器220被傳送到保密卡模 組140的帶内埠。控制訊號ENp〇D控制多工器25〇選擇合適的訊 號組。同樣地’位址接腳A8〜A9由帶外訊號DRX以及CRX共享， 而決定權則落在另一個多工器250上。控制訊號ENPOD也可經由 三態緩衝器152D與152E控制經由接腳A14與A4〜A7所傳送的 位址資訊、帶内訊號MCLK0以及帶外訊號QTX、ETX、ITX、 era ;除此之外，帶外控制訊號CRX以及DRX會被從解調變器 220送至解多工器122，以利用解多工翠122來處裡這些訊號。 不同於習知的數位電視系統，在上述的實施例中，保密卡模組 的位址與資料接腳與外接記憶體的位址與資料接腳耦接，因此可 降低後端電路的接腳使用量，而一旦當後端電路的接腳使用量降 低時’則後端電路的電路面積(footprint)以及製造成本便會隨之下 降。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為習知數位電視系統的功能方塊圖。 第2圖係本發明數位電視系統之第一實施例的功能方塊圖。 第3圖係在多個輸入訊號間進行選擇之複數個多工器的示意圖。 第4圖係本發明數位電視系統之第二實施例的功能方塊圖。 【主要元件符號說明】 20 主機前端積體電路 22 諧調器 24~~ 傳送電路 26~' 接收電路 28 > 220 解調變器 1324881 34 36 外部記憶體ΫΓΪ -— 50 POD 模組 '— 10、100、200 數位電視系氣~~~一'— 110 第一主機刚端積體電路 30 ' 120 1機後端積氣-- 32、122 解多工器~ -— 124 裁fS 126 外部記憶體—— 128 密碼έ忍證卡控制ΙΪ 130 • ' . . 接腳多工器 ' — 140 密碼認證卡 150A、150B、150C、150D、 二態緩衝器 ' 152A、152B、152C、152D、152E 180 第二主機前端積體電路 190、190A、190B、190C、190D DO 〜D7 資料接腳 ~ 40 記憶體'~~— 42 唯讀記憶體 '~ 44 周邊裝置 ~_— 45 位址及資料匯流排 210 主機積體電每:~ 1324881 250 多工器 A0-A25 位址接腳A15 to A25' wherein the signals MDI0 to MDI7, MIVAL, MICLKI, and MISTRT are scheduled to be transmitted from the demodulation transformer 220 of the main body integrated circuit 21 to the in-band port of the security card module 140. The control signal ENp〇D controls the multiplexer 25 to select the appropriate signal group. Similarly, the address pins A8 to A9 are shared by the out-of-band signals DRX and CRX, and the decision weight falls on the other multiplexer 250. The control signal ENPOD can also control the address information transmitted via the pins A14 and A4 to A7, the in-band signal MCLK0, and the out-of-band signals QTX, ETX, ITX, era via the tristate buffers 152D and 152E; The out-of-band control signals CRX and DRX are sent from the demodulator 220 to the demultiplexer 122 to utilize the signals from the multiplexer 122. Different from the conventional digital television system, in the above embodiment, the address of the security card module and the address of the data pin and the external memory are coupled with the data pin, thereby reducing the pin of the back circuit. The amount of use, and once the amount of pin usage of the back-end circuit is reduced, the circuit footprint and manufacturing cost of the back-end circuit will decrease. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should fall within the scope of the present invention. [Simple description of the drawing] Fig. 1 is a functional block diagram of a conventional digital television system. Figure 2 is a functional block diagram of a first embodiment of the digital television system of the present invention. Figure 3 is a schematic diagram of a plurality of multiplexers that select between multiple input signals. Figure 4 is a functional block diagram of a second embodiment of the digital television system of the present invention. [Main component symbol description] 20 Host front end integrated circuit 22 Tuner 24~~ Transmission circuit 26~' Receiver circuit 28 > 220 Demodulation transformer 1324881 34 36 External memory ΫΓΪ - 50 POD module '-10 100, 200 digital TV system gas ~~~一'-110 First host rigid end integrated circuit 30 '120 1 machine back end gas accumulation -- 32,122 solution multiplexer ~ -— 124 cutting fS 126 external memory —— 128 Password έ 证 ΙΪ ΙΪ 130 • ' . . Pin multiplexer ' — 140 Password authentication card 150A, 150B, 150C, 150D, two-state buffer ' 152A, 152B, 152C, 152D, 152E 180 Two host front-end integrated circuit 190, 190A, 190B, 190C, 190D DO ~ D7 data pin ~ 40 memory '~~- 42 read-only memory '~ 44 peripheral device ~_- 45 address and data bus 210 Host integrated power every: ~ 1324881 250 multiplexer A0-A25 address pin