TWI324778B - Memory, bit-line pre-charge circuit and bit-line pre-charge method - Google Patents

Description

1324778 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a memory device, a bit line precharge circuit and a bit line precharge method, and more particularly to a bit line applied to a memory cell (memory ceu) A memory device for a bit line voltage, a bit line precharge circuit, and a bit line precharge method. [Prior Art]

Please refer to Fig. 1, which is a circuit diagram of a detection concept and a precharge circuit in a conventional memory array. Only the control circuit of one of the plurality of memory cells of the memory array is shown. In Fig. 1, the detection concept 1 is mainly composed of the inverter 101 and the memory cell 102. A first end of the clamp transistor MCL is connected to the voltage source VDD via the load 103, and a second end is connected to The input terminal of the inverter 101 and the bit line and the control terminal are connected to the output terminal of the inverter 101. Memory cell 102 is controlled by word line voltage VWL. The capacitor CBL shown in the figure refers to the capacitance effect between the bit line terminals, but its capacitance in the circuit structure. The voltage VBL and the ground do not exist in a real detection concept. The capacitance value of the CBL will become large, and the voltage VBL will be reduced to a predetermined value (for example, the operation of the 1 volt volt 'element bit' concept solution 10 itself. , 亜 / If only according to 3 will increase the bit line voltage Vbi f 艮 long time)

L to the predetermined value, it is difficult to I

7 use the requirements. In order to improve this disadvantage, the conventional technique adds an additional pre-charging path 11 in the detection concept scheme 10, and utilizes an additional pre-charging path 11 to increase the pre-charging speed in the early stage of the pre-charging phase, so that the bit line voltage vBL can be faster. The predetermined value is reached. However, the delay circuit 12 for controlling the additional pre-charging path 11 is subject to many influences of power supply, temperature, and process corners, and thus has great difficulty in precise control; that is, it is intended to be accurately controlled. The startup, operation and shutdown of the additional pre-charging path 11 is highly difficult. For the sake of his position, the applicant has conceived the memory device, the bit line pre-charging circuit and the bit line pre-charging method in the light of the lack of the prior art, after careful testing and research, and a perseverance spirit. The following is a brief description of the case. SUMMARY OF THE INVENTION The purpose of the present invention is to provide a memory device, a bit line pre-charging circuit, and a bit line pre-charging method, thereby increasing the pre-charging speed of the bit line, and being able to turn off an additional pre-charging path early to generate Sufficient voltage margin to prevent overcharge. In this aspect, a memory device is provided, including: a memory cell; a clamp transistor having a first end, a second end, and a control end The second end is lightly coupled to the memory cell; a first inverter having an input end and an output end electrically connected to the second end of the clamp transistor 1324778, the output end Electrically connected to the control end of the clamp transistor; a bit line electrically connected to the second end of the clamp transistor and the input end of the first inverter, the bit line having a first line voltage; a pre-charging path electrically connected to the first end of the clamp transistor, having a detection voltage at the connection node; and a detection controller electrically connected to the clamp current Crystal The first end and the pre-charging path, the detecting controller is configured to detect the detecting voltage, and when the detecting voltage is at a first low level, turn on the pre-charging path to increase the bit line voltage, and when The pre-charging path is turned off when the detection voltage is at a first high level. Another aspect of the present invention provides a bit line precharge circuit, comprising: a clamp transistor having a first end, a second end, and a control end; a bit line electrically connected to the clamp transistor The second end of the bit line has a bit line voltage; a current source circuit is connected to the first end of the clamp transistor, has a detection voltage at the connection node; and a detection controller Electrically connected to the first end of the clamp transistor and the current source circuit, the detection controller is configured to detect the detection voltage, and enable the current when the detection voltage is at a first low level The source circuit boosts the bit line voltage and disables the current source circuit when the sense voltage is at a first high level. In another aspect, the present invention provides a bit line pre-charging method, which is applied to a plurality of bit lines of a memory array, wherein each bit line is coupled to a clamp transistor, and the clamp transistor has a first a second end and a control end, each of the first ends has a detection voltage, each of the second ends is electrically connected to the bit line, and the bit \ S ) 9 1324778 has a line a bit line voltage, the bit line pre-charging method comprising the steps of: detecting the detection voltage; pre-charging the clamping transistor to increase the bit line voltage when the detection voltage is at a low level; When the detection voltage is at a high level, the pre-charging of the clamp transistor is stopped. In this case, we can get a deeper understanding by the following diagrams and detailed explanations: [Embodiment] Please refer to the memory device in order to improve the above problem. The figure includes the clamp transistor MCL and the reverse in the first figure. In addition to the phase detector 101 and the bit line detection concept 10, a pre-charging path and a detection controller are additionally provided. Please refer to Fig. 2, which is a circuit diagram of a preferred embodiment of the memory device proposed in the present invention. In Fig. 2, the circuit configuration of the detection concept 10 is identical to that of Fig. 1, and the memory device 2 includes a precharge path 21 and a detection controller 22 in addition to the concept solution 10. The following describes the operation between the detection concept scheme 10, the precharge path 21, and the detection controller 22, and the operation is based on a detection voltage Vsa and a bit on the drain of the NMOS transistor constituting the clamp transistor MCL. One element line voltage VBL on the meta line. In other words, the detection controller 22 can be used to detect the detection voltage Vsa by electrically connecting the pre-charging path 21 and the detection controller 22 to the anode of the NMOS transistor constituting the clamp transistor MCL. (S) 10 1324778 When the detection voltage Vsa is at the low level, the detection controller 22 turns on the pre-charging path 21 to raise the bit line voltage VBL, and when the detection voltage Vsa is at the high level, the detection controller 22 turns off the pre- Charging path 21 藉• By pre-charging path 21 and detecting controller 22, the pre-charging speed of the bit line can be increased, and the pre-charging voltage Vsa can be accurately turned off when the pre-charging voltage Vsa is approximated to the bit line voltage Vbl. The charging path 21 has the advantage of preventing overcharging but is not affected by the power source, temperature, and process boundaries. In the preferred embodiment of Fig. 2, a current source circuit is used as the precharge path 21. As shown in FIG. 2, the current source circuit is composed of three PMOS transistors P1 to P3 and a reference current source Ir^, and the sources of the PMOS transistor P1 and the pM0S transistor p2 are electrically connected to the high voltage source. The VDD and the gate are electrically connected to each other. The drain of the PMOS transistor P2 is electrically connected to its own gate and the input terminal of the reference current source iREF, and the output of the reference current source Iref is electrically connected to the low voltage source. . The source of the PMOS transistor P3 is electrically connected to the drain of the PMOS transistor P1, and the gate receives a control voltage vct from the detection controller 22, and is electrically connected to the NMOS electrode constituting the clamp transistor MCL. The bungee of the crystal. Note that the aspect ratio of the PMOS transistor P1 (aspect

The ratio is y [times] of the aspect ratio of the PMOS transistor P2, and the PMOS transistor PI, the PMOS transistor P2, and the reference current source IREF together constitute a current mirror; therefore, as the current source of the precharge path 21. The circuit can supply a Μ times reference current iREF to the clamped electrical 11 1324778 crystal MCL.

On the other hand, the detection controller 22 is composed of a pM 〇s transistor P4, an NMOS transistor N2, a buffer dET, and two inverters 〇4 and 105. The source of the PMOS transistor p4 is electrically connected to the high voltage source, the gate is controlled by the uniform energy signal pRE_EN, and the drain of the NM〇s transistor N2 is electrically connected to the drain and gate of the pM〇s transistor p4. The output terminal and the source of the buffer DET are electrically connected to the low voltage source. The inverters 104 and 105 are electrically connected to each other in reverse, and the input terminal of the DET is electrically connected to the > and the NMOS transistors constituting the clamp transistor mcl. Please refer to Fig. 3, which is a wave sequence diagram of the control voltage Vctl, the precharge voltage Vsa and the bit line voltage of the memory device of Fig. 2 under different memory currents. The following only uses the memory cell current Icell for ΙΟιιΑ and also refers to Figure 2 for illustration. When the memory cell current Icell is 15UA and 20uA, respectively, the situation is similar. 1. 1. 0ns~20ns

When the bit line voltage VBL is high by the low level, the detection voltage V sa is lowered from the high level, and the control voltage Vctl is also lowered to the low level by the detection of the detection controller 2 2, and the precharge path is PMOS. Crystal ^ pass 'precharge path 21 provides "parameters

The current Iref is applied to the clamp transistor MCL to increase its precharge yield. 2. When 20 ns is near 'X and when the rise of the bit line voltage VBL is slowed down', due to the amplification of the home transistor MCL, the detection voltage Vsa will rise to a higher level with a faster rate, via the detection controller 22, , 2 conversions, control voltage < S ) 12 1324778

Vctl also rises to a high level. At this time, the PMOS transistor P3 of the precharge path 21 is turned off, and the precharge path 21 stops supplying the reference current Iref to the clamp transistor MCL. ' 3. 20ns~50ns Although the reference current Iref is greater than the memory cell current' but the bit line voltage VBL does not rise enough to detect the level at which the precharge path 21 is turned off, the bit line voltage VBL requires a segment. It will take a long time to stabilize. The reason for this long period of formation is illustrated by Figure 4 below. Please refer to FIG. 4, which is a schematic diagram of the reference current Iref load line and the memory cell current Icell of the clamp cell under the variation of the gate voltage VCl and the source voltage VBL of the clamp transistor of FIG. . As can be seen from Fig. 4, in order to charge the bit line, the 参考 times reference current Iref provided by the precharge path 21 must be greater than the memory cell current Icell. Further, since the gate-source voltage Vgs of the clamp transistor MCL is fixed, when the bit line voltage Vbl rises, the gate voltage VCL falls. Obviously, the bit line voltage VBL in the detection phase is the point a in the figure, and the bit line voltage VBL when the precharge path is off is the point b in the figure, between the two points a and b. The voltage difference is the reason why the bit line voltage VBL after the aforementioned pre-charging path 21 is turned off requires a long period of time to stabilize. In order to minimize this period of time, the case proposes two methods and circuit structure to solve. The first method is to increase the memory current Icell; that is, try to

13 1324778 The memory cell current load line in Figure 4 is raised to a point closer to the reference current Iref load line of 'Μ, so that paying a and b two points as close as possible' can shorten this period of time. In order to achieve this goal, the method used in this case is to increase the channel width of the clamp transistor MCL. Please refer to FIG. 5, which is a circuit diagram of the memory device with the first compensation circuit proposed in the present invention. The memory device 5 of the figure differs from the memory device 2 of FIG. 2 only in that a first compensation circuit 51 is provided between the three ends of the NMOS transistor constituting the clamp transistor MCL to increase the clamp transistor MCL. The channel width, thereby increasing the memory current Icell. The first compensation circuit 51 includes an NMOS transistor N3 and a PMOS transistor P5. The drain of the NMOS transistor N3 is electrically connected to the drain of the clamp transistor MCL, and the gate is electrically connected to the gate of the clamped transistor MCL. The source of the PMOS transistor P5 is electrically connected to the source of the NMOS transistor N3, and the gate is controlled by the control voltage Vet. The gate is electrically connected to the source of the clamp transistor MCL. Further, the aspect ratio of the NMOS transistor N3 is M-1 times the aspect ratio of the clamp transistor MCL. Please refer to FIG. 6 , which is the reference current IrEf load line and the memory cell current Icell load line which are twice the compensation after the change of the gate voltage VCL and the bit line voltage VBL of the memory cell in FIG. 5 . intention. As can be seen from the figure, the memory cell current Icell can be increased by the configuration of the first compensation circuit 51, and the memory cell current load line and the 参考 times reference current IREF load in FIG. 4 can be obtained under optimal conditions. 14 1324778 Lines coincide with each other' so that the two points a and b also coincide with each other to eliminate the time. The second method is to change the relationship between the bit line voltage VBL and the gate voltage ^Vcl; that is, 'try to make the gate of the fourth figure electrically waste - V 〇 L and the bit line voltage Vbl change line The slope is increased so that the two points a and b are as close as possible, and this period of time can be shortened. In order to achieve this, the method used in this case is to enhance the driving ability of the first inverter 1〇1 to change its transfer function ° _ See Figure 7 A circuit diagram of a memory device having a second compensation circuit, the memory device 7 of FIG. 7 differs from the memory device 2 of FIG. 2 only in that a first portion is provided between the input terminal and the output terminal of the inverter 1〇1. The second compensation circuit 71 is operative to enhance the driving ability of the first inverter 1〇1 to change its conversion function. The second compensation circuit 71 includes a PMOS transistor? 6 and 1>]\408 Transistor P7. The drain of the PM0S transistor P6 is electrically connected to the high voltage source VDD, and the gate is controlled to control the electroacoustic Vctl. The source of the PM0S transistor is electrically connected to the drain of the PMOS transistor P6, the gate is electrically connected to the input end of the first inverter 101, and the gate of the gate is electrically connected to the output of the first inverter. end. Please refer to FIG. 8 'which is the change of the gate voltage vcl and the bit line voltage vBl of the clamp transistor MCL in FIG. 7 and the compensated IV [times of the reference current Iref load line and the memory cell current Icell Schematic diagram of the load line. As can be seen from the figure, by the configuration of the second compensation circuit 71, the driving capability of the first inverter 1〇1 can be enhanced and the conversion function can be changed 15 in the best case. The slope of the change line of the gate voltage yCL and the bit line voltage Vbl is increased (as changed from the change line S to the change line R in the figure), so that the two points a and b are as close as possible to shorten the time. Please refer to FIG. 9 , which is the control voltage of the memory device of FIG. 2 under different memory currents after the compensation circuit is configured.

Waveform timing diagram of Vet Bu detection voltage Vsa and bit line voltage diaphragm. Compared with the 9th and 3rd figures, it can be seen that with the compensation method and circuit proposed in the present case, it is indeed possible to improve the bit line voltage VBL after the pre-charging path 21 is turned off, which requires a long period of time to stabilize. . In summary, the present case mainly utilizes a pre-charging path 侦测-detection control H in the pre-charging stage before riding the memory pre-charging speed, can quickly and stably pre-charge the bit line, or stop at the appropriate time Prevent overcharging. In addition, 'this # also proposes a compensation circuit and method, which can improve the problem that the bit line voltage after the pre-charging path is turned off requires a long period of time to stabilize. This case can be modified by people who are familiar with the art, and they are all modified as if they were protected by the scope of the patent application. ^ Call 4778 [Simple description of the diagram] • Figure 1. Circuit diagram of the detection concept in the memory call list / 茱 and precharge circuit. - Figure 2: Circuit diagram of a preferred embodiment of the memory device proposed in the present invention. Fig. 3 is a control voltage Vct of the memory device under different memory cell currents, and a detection voltage Vsa and a bit line voltage I. Waveform timing diagram. • Fig. 4: Schematic diagram of the reference current Iref load line and the memory cell current Icell load line at the gate voltage VcL of the clamp transistor MCL and the change of the source voltage Vbl in Fig. 2. Fig. 5 is a circuit diagram of a memory device having a first compensation circuit as proposed in the present invention. "Fig. 6: The change of the reference current iref load line and the memory cell current Icell load line of M times after the compensation of the gate voltage VCL of the clamp transistor MCL in FIG. 5 = the bit line voltage Vbl Figure 7. Circuit diagram of the memory device with the second compensation circuit proposed in this case. Fig. 8 · The gate voltage VCL and the source voltage VBL of the clamp transistor in Fig. 7 Schematic diagram of the reference current Iref load line and the memory cell current IceU load line after the compensation, M times after compensation. Fig. 9: The memory device of Fig. 2 after the compensation circuit is configured, under different memory currents Waveform timing diagram of control voltage Vetl, detection voltage Vsa, and bit line voltage vBL. 17 1324778

VBE bit line voltage Vex gate voltage v WL word line electric dust Vctl control voltage Vsa detection voltage 19

Claims (1)

1324778 X. Patent application scope: 1. A memory device comprising: a memory cell; a clamp transistor having a first end, a second end and a control end, the second end being coupled to the memory cell; a first inverter having an input end and an output end electrically connected to the second end of the clamp transistor, the turn output being electrically connected to the control of the clamp transistor a first line electrically connected to the second end of the clamp transistor and the input end of the first inverter, the bit line having a bit line voltage; a precharge path, Connected to the first end of the clamp transistor, having a detection voltage at the connection node; and a detection controller electrically connected to the first end of the clamp transistor and the precharge path, The detection controller is configured to detect the detection voltage, and turn on the pre-charging path to increase the bit line voltage when the detection voltage is at a first low level, and turn off when the detection voltage is at a first high level. The pre-charge path. 2. The memory device of claim 1, wherein the first end of the clamp transistor is electrically connected to a high voltage source via a load, and the second end of the clamp transistor is further It is electrically connected to a low voltage source via the memory cell. 3. The memory device of claim 1, wherein the clamping transistor is a first NMOS transistor, the first end of the clamping transistor is a > and a pole of the powder transistor The control terminal is a gate, and the second end of the s 20 1324778 box transistor is a source. 4. The memory device of claim 1, wherein the pre-charging path is a current source circuit. 5. The memory device of claim 4, wherein the current source circuit comprises: a first PMOS transistor having a source, a gate and a drain, the source being electrically connected to a high voltage a first PMOS transistor having a first aspect ratio; a second PMOS transistor having a source, a gate and a drain, the source being electrically connected to the high voltage a source, the gate is electrically connected to the drain of the first PMOS transistor and the gate of the first PMOS transistor, the second PMOS transistor has a second aspect ratio, and the first aspect ratio is the first a third PMOS transistor having a source, a gate and a drain, the source being electrically connected to the drain of the first PMOS transistor, the gate being electrically Connected to the detection controller, the gate has a control voltage, the drain is electrically connected to the first end of the clamp transistor; and a reference current source has an input end and an output end. The input end is electrically connected to the drain of the second PMOS transistor, and the output end is electrically connected to a low voltage source, the reference current source is configured to provide a reference current; wherein, when the control voltage is at a second low level, the third PMOS transistor is turned off to turn off the precharge path, and when the control voltage is at a The second high level is on time, the third PMOS transistor leads 21 1324778 turns on the precharge path to provide a multiple of this reference current to the 13⁄4 bit transistor. 6. The memory device of claim 5, wherein the detection controller comprises: a fourth PMOS transistor having a source, a gate and a drain, the source being electrically connected to a high a voltage source, the gate is controlled by a uniform energy signal; a second NMOS transistor having a drain, a gate and a source electrically connected to the drain of the fourth PMOS transistor The source is electrically connected to a low voltage source; a buffer has an input end and an output end, the input end is electrically connected to the first end of the clamp transistor, and the output end is electrically connected The second inverter has an input end and an output end electrically connected to the drain of the fourth PMOS transistor and the second a drain of the NMOS transistor, the output terminal is electrically connected to the current source circuit; and a third inverter having an input end and an output end, the input end is electrically connected to the current source circuit and the The output end of the second inverter, the output end is electrically connected to the second inverting The input terminal of the device, the drain of the fourth PMOS transistor, and the > pole of the second NMOS transistor. 7. The memory device of claim 6, wherein the control terminal of the clamp transistor is electrically connected to a first compensation circuit for increasing a channel width of the clamp transistor. The clamp CS) 22 1324778 A voltage between the control terminal and the second terminal of the transistor is the same when the pre-charge path is turned on and off. 8. The memory device of claim 7, wherein the first compensation circuit comprises: a third NMOS transistor having a drain, a gate, and a source, the gate being electrically connected to the clamp The first end of the bit transistor is electrically connected to the control end of the clamp transistor, the third NMOS transistor has a third width to length ratio; and a fifth PMOS transistor has a a source, a gate and a drain, the source being electrically connected to the source of the third NMOS transistor. The gate is controlled by the control voltage, and the gate is electrically connected to the bit line Wherein the second aspect ratio is M-1 times the aspect ratio of the wheel transistor. 9. The memory device of claim 6, wherein the control terminal of the clamp transistor is electrically connected to a second compensation circuit for enhancing a driving ability of the first inverter. And changing a transfer function of the first inverter such that the bit line voltage is the same when the pre-charge path is turned on and off. 10. The memory device of claim 9, wherein the second compensation circuit comprises: a sixth PMOS transistor having a source, a gate and a drain, the source being electrically connected to a high a voltage source, the gate is controlled by the control voltage; and a seventh PMOS transistor has a source, a gate and a 23 1324778 drain, the source is electrically connected to the sixth PMOS transistor The gate is electrically connected to the input end of the first inverter, and the drain is electrically connected to the output end of the first inverter and the control end of the clamp transistor. 11. A bit line precharge circuit, comprising: a clamp transistor having a first end, a second end, and a control end; a bit line electrically connected to the first portion of the clamp transistor a two-terminal, the bit line has a bit line voltage; a current source circuit connected to the first end of the clamp transistor, having a detection voltage at the connection node; and a detection controller, electrical Connected to the first end of the clamp transistor and the current source circuit, the detection controller is configured to detect the detection voltage, and enable the current source circuit when the detection voltage is at a first low level The bit line voltage is boosted, and the current source circuit is disabled when the sense voltage is at a first high level. 12. The annual line pre-charging circuit of claim 11, wherein the clamping transistor is a first NMOS transistor, and the first end of the clamping transistor is a terminal. 13. The bit line pre-charging circuit of claim 11, wherein the current source circuit comprises: a first PMOS transistor having a source, a gate and a drain, the source being electrically connected The first PMOS transistor has a first aspect ratio; the second PMOS transistor has a source, a gate and a 24 1324778 drain, the source is electrically connected to the a high voltage source, the gate is connected to the drain of the first PMOS transistor and the gate of the first PMOS transistor, the second PMOS transistor has a second aspect ratio, and the first aspect ratio is the first a third PMOS transistor having a source, a gate and a drain, the source being electrically connected to the drain of the first PMOS transistor, the gate being electrically Connected to the detection controller, the gate has a control voltage, the drain is electrically connected to the first end of the clamp transistor; and a reference current source has an input end and an output end. The input end is electrically connected to the drain of the second PMOS transistor, and the output is electrically connected Connected to a low voltage source, the reference current source is used to provide a reference current; wherein, when the control voltage is at a second low level, the third PMOS transistor is turned off to disable the current source circuit, and when When the control voltage is at a second high level, the third PMOS transistor is turned on to enable the current source circuit to provide a multiple of the reference current to the clamp transistor. 14. The bit line precharge circuit of claim 13, wherein the detection controller comprises: a fourth PMOS transistor having a source, a gate and a drain, the source being electrically Connected to a high voltage source, the gate is controlled by a uniform energy signal; a second NMOS transistor having a drain, a gate and a source, and the pole is electrically connected to the fourth PMOS The source is electrically connected to a low voltage source; the buffer has an input end and an output end electrically connected to the first end of the clamp transistor The output end is electrically connected to the gate of the second NMOS transistor; the second inverter ' has an input end and an output end electrically connected to the fourth PMOS transistor The drain and the drain of the second NMOS transistor, the output terminal is electrically connected to the current source circuit; and a third inverter has an input end and an output end, the input end is electrically connected At the current source circuit and the output of the second inverter, the output The input terminal is electrically connected to the second inverter, the fourth PMOS transistor and the drain> and the second electrode of the NMOS transistor. 15. A bit line pre-charging method applied to a plurality of bit lines of a memory array, wherein each bit line is coupled to a clamp transistor, the clamp transistor having a first end, a second end and a control end, each of the first ends has a detection voltage, each of the second ends is electrically connected to the bit line, and the bit line has a bit line voltage, the bit The method for pre-charging the power line includes the following steps: detecting the detection voltage; pre-charging the clamp transistor to raise the bit line voltage when the detection voltage is at a low level; and when the detection voltage is at a high level, Stop precharging the clamp transistor. 16. For the method of pre-charging the bit line of claim 15 of the patent scope, 26 1324778 includes a first compensation step of increasing a channel width of the clamp transistor such that a voltage between the control terminal and the second terminal of the clamp transistor is precharged to the clamp transistor The same is true when the pre-charging of the clamp transistor is stopped. 17. The method of pre-charging a garment line according to claim 15 further comprising a second compensation step of: connecting an inverter between the control end and the second end of the clamp transistor, and enhancing The driving capability of the inverter changes a conversion function of the inverter such that the bit line voltage is the same when pre-charging the clamping transistor and stopping pre-charging the clamping transistor.