1323516 九、發明說明： 【發明所屬之技術領域】 本發明與製備奈米尺度之單電子電晶體有關，特別 是利用現行半導體製程中的微影技術、蝕刻技術等來製 備完成’而具有突破既有製備奈米結構設備的物理極 限’以及同時滿足室溫操作的條件要求下，精準地達成 控制源極#閘、✓及極及閘極的大小與彼此之間的相對 位置，進而達到大量生產的目的。 【先前技術】 奈米電子學技術被視為未來新一代微電子技術的 核主要是因為具有量子效應的奈米電子元件的工作 電流為數個到數十個電子，因此其因運算工作所帶來的 能耗極小，其與目前積體電路中的微電子元件相比，可 大幅降低其能耗，且工作時間頻率（即運算速度）也可 以隨之大幅度提高；其中，單電子電晶體（singie EleCtr〇n Transistor，SET)被視為極有潛力成為下一代 微處理器的主要核心，其主要工作是基於庫倫堵塞效應 (Coulomb Blockade Effect )和單電子隧道效應（Single -Electron Tunnel Effect )的物理效應，所產生的—種新 型奈米電子元件。 早在20世紀中期，物理理論便預期了庫倫堵塞效 7 應和單電子隧道效應，且庫偷堵塞效應是1980年代固 體物理所觀測到的重要物理現象之一；當一個物理體系 的尺寸達到奈米量級時，這個體系的充電和放電過程是 不連續的，也就是說，其是量子化的，充入一個電子所 需的成量 為 e2/2C (Charging Energy)，其中 e 為一 個電子的電荷，C為該物理體系的電容，體系越小， 電容C越小’能量越大，所以把這個能量稱為庫 倫堵塞能；在一個奈米體系的充放電過程中，電子無法 進行連續的集體傳輸，而是一個一個單電子的傳輸，這 種在奈米體系中電子的單個輸送特性，就稱之為庫偷堵 塞效應。又，如果兩個量子點通過一個隧道結（Tunnel Junction)連接起來，單個電子從一個量子點穿過勢壘 (Tunnel Barrier)到另一個量子點的過程，稱為量子穿隧 效應8為了使單個電子從一個量子點隧穿到另一個量子 點，這個電子的能量必需克服電子的庫偷堵塞能 五c，亦即e/2C ’此處c為兩個量子點之間隧道結的 電容。但直到20世紀80年代後期，人們才成功地在極 低溫的環境下實現了利用這些效應的電子元件線路。實 踐晚於理論的長達幾十年的主要原因是在此之前，人們 的技術還無法成熟到成長出非常微小的電極以及對這 些電極進行精確定位β庫倫堵塞效應和單電子隧道效應 8 1323516 的直接應用就是設計和製造單電子電晶體元件。單電子 電晶體元件具有能耗低，高熱敏度和易於集成等突出優 點’因此被認為是傳統的微電子MOS元件之後，最有 發展前途的新型奈米元件之一。 請參閲第一圖所示，係己被發表之單電子電晶體 (Single Electron Transistor，簡稱 SET)的基本電路圖， 是為具有源極（source)S、汲極（drain)D及閘極（gate)G 的二極體，其基本電路除包括源極s，汲極D及閘極G 外尚有一可儲存電荷的浮閘（island)I，係介於源極s 與汲極D之間，且此儲存電荷的浮閘丨之電容極小，相 對而言其顆粒大小為奈米級尺度，進而形成小尺寸量子 點（quantum dot’ QD)所特有的庫侖障壁（c〇lU〇mb Blockade )之效應，而在量子點兩端則為極微小之穿透 性接合（tunnel juncti〇ns);此結構的特點是在量子點內 形成不連續能階（discrete energy level)，只有當源極s ' 汲極D内的費米能階（Fermi level)和量子點內的能階排 成一線對準時，電子才能經由量子點從源極S流至汲極 D，如此便可控制每次流過的電子數目，甚至在理想狀 態下可達到每次只有一個電子通過，因此該源極S與浮 閘I之間的距離di、或汲極D與浮閘j之間的距離、 或閘極G與浮閘I之間的距離d3及其自身的大小尺 9 13235161323516 IX. Description of the invention: [Technical field of the invention] The present invention relates to the preparation of nano-scale single-electron transistors, in particular to the use of lithography techniques, etching techniques, etc. in current semiconductor processes to prepare for completion. With the physical limit of preparing nanostructured devices and the conditions for operating at room temperature, the relative position of the source gates, ✓ and poles and gates can be accurately controlled to achieve mass production. the goal of. [Prior Art] Nanoelectronics technology is regarded as the core of the next generation of microelectronics technology mainly because the nanometer electronic components with quantum effects have several to dozens of electrons, so they are brought about by the operation. The energy consumption is extremely small, which can greatly reduce the energy consumption compared with the microelectronic components in the current integrated circuit, and the working time frequency (ie, the operation speed) can also be greatly improved; among them, the single electron transistor ( Singie EleCtr〇n Transistor (SET) is considered to have the potential to become the main core of the next generation of microprocessors. Its main work is based on the Coulomb Blockade Effect and the Single-Electron Tunnel Effect. Physical effects, produced by a new type of nanoelectronic components. As early as the middle of the 20th century, physics theory predicted the Coulomb blockage effect and single electron tunneling effect, and the library stealing effect was one of the important physical phenomena observed in solid physics in the 1980s; when the size of a physical system reached In the case of meters, the charging and discharging process of this system is discontinuous, that is, it is quantized, and the amount of electrons required to charge an electron is e2/2C (Charging Energy), where e is an electron. The charge, C is the capacitance of the physical system, the smaller the system, the smaller the capacitance C, the larger the energy, so this energy is called the Coulomb plugging energy; in the charging and discharging process of a nano system, the electrons cannot be continuous. Collective transmission, but a single electron transmission, this single transport characteristic of electrons in the nano system is called the library stealing effect. Also, if two quantum dots are connected by a tunnel junction, the process of a single electron passing from one quantum point through a barrier to another quantum dot is called quantum tunneling effect 8 in order to make a single Electrons tunnel from one quantum point to another, and the energy of this electron must overcome the electron bank's stealing energy, c, ie, e/2C 'where c is the capacitance of the tunnel junction between the two quantum dots. However, it was not until the late 1980s that people succeeded in implementing electronic component lines that utilized these effects in extremely low temperatures. The main reason why practice is decades later than theory is that before this, people's technology could not mature enough to grow very tiny electrodes and accurately locate these electrodes. β Coulomb plugging effect and single electron tunneling effect 8 1323516 Direct application is the design and manufacture of single-electron transistor components. Single-electron transistor components have outstanding advantages such as low power consumption, high thermal sensitivity and ease of integration. Therefore, they are considered to be one of the most promising new nano-components after traditional microelectronic MOS components. Please refer to the first figure, which is the basic circuit diagram of the Single Electron Transistor (SET), which has a source S, a drain D and a gate. The gate of G)G, in addition to the source s, the drain D and the gate G, has a charge I, which is between the source s and the drain D. And the capacitance of the floating gate of the stored charge is extremely small, and the particle size is relatively on the nanometer scale, thereby forming a Coulomb barrier (c〇lU〇mb Blockade) unique to a small quantum dot (QD). The effect is a very small penetrating junction (tunnel juncti〇ns) at both ends of the quantum dot; this structure is characterized by the formation of a discrete energy level within the quantum dot, only when the source s When the Fermi level in the bungee D is aligned with the energy level in the quantum dot, electrons can flow from the source S to the drain D through the quantum dot, so that each flow can be controlled. The number of electrons, even under ideal conditions, can reach only one electron at a time, This distance di between the source and the floating gate electrode S I, the distance d3 between the distance between the drain D or the floating gate j, G or gate and the floating gate and its own I roll sizes 91323516
寸，將會影響整個單電子電晶體的性能（perf〇rmance) 和良率，以現行之技術要達到前述的要求，相當困難且 製備之成本極為高昂’亦是至今仍尚朱被大量生產使用 於半導體或電子產業的主要原因。 再如第二圖至第四圖所示，係習知以奈米微影 製程(nan〇-mh〇graphy)所得之奈米結構，其施作之步 驟為：（a).先將預期的奈米圖形Q設計於光罩 (ask)M上’再將該光罩馗置放於表面塗佈有阻劑(St)2的基材1上方(如第二圖所示）；(B).以光束 e穿過光罩Μ上的各奈米圖形Q後形成曝光，再經 過顯影之後，即會在基材 與原設計於光覃Μ上相同 (如第三圖所示）；（C)·以鍍 表面的阻劑2上生長出Inch, will affect the performance (perf〇rmance) and yield of the entire single-electron transistor. It is quite difficult to achieve the above requirements with the current technology, and the cost of preparation is extremely high. The main reason for the semiconductor or electronics industry. Further, as shown in the second to fourth figures, the nanostructure obtained by the nano lithography process (nan〇-mh〇graphy) is conventionally applied as follows: (a). The nano-pattern Q is designed on the mask M. The photomask is placed on the substrate 1 coated with the resist (St) 2 (as shown in the second figure); (B) After the light beam e passes through each nano-pattern Q on the mask, the exposure is formed, and after development, the substrate is the same as the original design on the pupil (as shown in the third figure); ) · grows on the resist 2 of the plating surface
子型態的鍍源材料Β直接 與底部位置上（如第四圖中 圖形Q的奈米孔3之結構 源裝置30將氣體分子或原 鑛著在該奈米孔3的周圍 之Χ及Υ兩視圖所示）； (D).最後再以溶劑將阻劑 面上得到所需奈米尺度結 2消除後’即可在基材丨表 構的奈米點4(如第四圖中 之Ζ視圖所示）„其中 前述之習知製程因受限於既 有光刻技術的精度極 尺寸只能連到60〜65 光罩Μ的奈米孔3， 限下’使得目前最精密的奈米 奈米（nm)，因此轉印曝光來自 其奈米尺寸均在60奈米（nm)以 1323516 上，相對地其製備所得到的奈米點4之奈米尺寸也 是在60奈米（nm)以上，故如何突破該奈米孔3的奈 米尺度，使其Bb更小至單電子電晶體所需的丨〇奈米 (ΓΗΠ)以下，乃是至今各個領域產業專家們所急欲解 • 決的技術難題，同時在解決過程中又得遵守成本花 費不可太高的原則，致使選擇技術突破的方式相當 困難，瞭解奈米科技的科學家或奈米技術的製備專 •家們，都知道要做出小於10奈米或小至卜2奈米之 元件的好處，但至今仍見不到有任何好的特別方法 被提出或發表或應用。 【發明内容】 本發明首創一種使用半導體微影技術製備單電子 電晶體的方法，其主要目的在利用既有生產半導體製程 • 的設備下’不必改變或重新設計其原有設備的精準度， .即可精準地製備出奈米結構之單電子電晶體，且同時達 成㈣單電子電晶體中源極、浮閘、㈣及閘極的大小 與彼此之間的相對位置，以及滿足室溫操作的條件要 求’進而達到大量生產的目的。 本發明之另-目的係在提供—種使用半導體微影 技術製備單電子1：晶體的方纟，其步驟在既 定成長（型）於基材（Substrate)上之奈米結構筒狀細孔 1323516 (P〇re)的頂部開口上，以原子或分子態的材料堆積黏著 於該奈米結構筒狀細孔的頂部開口，使其頂部開口的口 徑逐渐縮小而形成一較原有頂部開口口徑為小的奈来 縮小D (reduced nano-aperture) ;(b)將基材固定在水平 方向，再以氣體分子或原子型態的鍍源材料垂直正對於 該奈米縮小口，㈣氣體分子或原子型態的鍛源材料穿 透該奈米縮小口後，即會直接在奈米結構筒狀細孔的底 部基材表面上，鍍著形成一個與該奈米縮小口之口徑尺 度相同的利奈米量子點;(c)《令基才才以奈米緒小口 為中心向右傾斜一傾斜角度，且氣體分子或原子型態的 鍍源材料輸出方向不變，再次將該氣體分子或原子型態 的鍍源材料穿透該奈米縮小口，即會在該浮閘奈米量子 點之右側位置的基材表面上，鍍著出一汲極奈米量子 點’（d )再令基材以奈米縮小口為中心向左倾斜一傾斜 角度，且氣體分子或原子型態的鍍源材料輸出方向不 變，再次將該氣體分子或原子型態的鍍源材料穿透該奈 米縮小D，即會在該浮閘奈米量子點之左側位置的基材 表面上’鍍著出一源極奈米量子點；（e)以奈米縮小口 的中心線作為軸心，並配合一傾斜的傾斜角度與一旋轉 的旋轉角度’且氣體分子或原子型態的鍍源材料輸出方 向不變’再經由氣體分子或原子型態的鍍源材料穿透該 12 1323516 奈米縮小口後，即會在該浮閘奈米量子點之前侧位置的 基材之表面上，鍍著出一閘極奈米量子點；（f)最後以 汾劑洗滌（即溼式蝕刻wet eiching)或氣體腐蝕（即乾式 蝕刻dry etching)等方式將基材上的阻劑及阻劑上的奈 * 米結構筒狀細孔消除，即可在基材上製備出具有奈米尺 . 度的浮閘奈米量子點、汲極奈米量子點、源極奈米量子 點及閘極奈米量子點結構之單電子電晶體。 • 【實施方式】 如第五圖所示’係習知半導體微影製程利用 binld-up或build-down等方法製程中所得出的既有奈米 結構筒狀細孔10，該習知奈米結構筒狀細孔1〇的最小 尺寸只能達到60奈米^叫或6〇奈米（nm)以上，其製備 方式可選擇包括光刻微影技術、奈米轉印技術（職〇 φ impnnting)、分子束磊晶技術（mbe)、化學氣相沉積技 術（MOVCD)等之任一種方式來達成，惟，該等習知之技 術方式均非本發明所訴求之技術特徵與標的，故在此不 予贅述，合先敘明。 續請參閱第五圖至第十三圖所示，本發明「使用半 導體微影技術製備單電子電晶體的方法」，其步驟包含： (a)在既定成長（型）於基材（substrate)l的阻劑 (resist)2上之奈米結構筒狀細孔（p〇re) 1〇的頂部開口 13 11上（如第五圖中之Β·Β楣 β視圖所不）’先以原子或分子態 的封口材料Α堆積黏芸##六 唯償黏著於該奈米結構筒狀細孔〗〇之頂 部開口 11，使該頂却两h^ 、部開口 11的口徑逐渐縮小而形成一 較原頂部開口 U纟口徑為小的奈米縮小口 (reduced 職〇-aperture)2()(如第六圖之g視圖及第七圖所示）； (b)將基材1时在水平方向，再以氣體分子或 原子型態的鍍源材料B垂直正對於該奈米縮小口 2〇， 使該氣體分子或原子型態的鍍源材料B穿透該奈米縮 小口 20後’即會直接在奈米結構筒狀細孔10的底部基 材1表面上，鍍著形成一個與該奈米縮小口 2〇之口徑 尺度相同的浮閘奈米量子點4〇(如第九圖所示）； (C)先令基材1以奈米縮小口 20為中心向右傾斜 一傾斜角度θ 1，·且氣體分子或原子型態的鍍源材料b 輸出方向不變，再次將該氣體分子或原子型態的鍍源材 料B穿透該奈米縮小口 20 ’即會在該浮閘奈米量子點 40之右側位置的基材1表面上，鍍著出—汲極奈米量 子點50 (如第十圖及第十圖中2_2剖視圖所示）； (d )再令基材1以奈米緒小口 2 0為中心向左傾斜 一傾斜角度Θ2’且氣體分子或原子型態的鍍源材料b 輸出方向不變’再次將該氣體分子或原子型態的鍍源材 料B穿透該奈米縮小口 20’即會在該浮閘奈米量子點 40又左側位置的基材i表面上’鍍著出—源極奈米量 子點60 (如第十-圖及第十-圖中3-3剖視圖所示）； (e) 以奈米縮小口 20的中心線作為軸心，並配合 傾斜的傾斜角度θ與一旋轉的旋轉角度①，且氣體分 子或原子型態的鍍源材料Β輸出方向不變，再經由氣體 分子或原子型態的鍍源材料Β穿透該奈米縮小口 後’即會在該浮閘奈米量子點4G之前側位置的基材工 I表面上，鍍著出一閘極奈米量子點70 (如第十二圖 及第十二圖中4_4剖視圖所示）；及 (f) 最後以溶劑洗滌（即溼式蝕刻wet etcMng)或氣 體腐姓（即乾式姓刻dry etehing)等方式將基材^上的阻 j及阻劑2上的奈米結構筒狀細孔1 〇消除，即可在 基材1上製備出具有奈米尺度的浮閘奈米量子點40、 汲極奈米量子點50、源極奈米量子點6。及閘極奈来量 子點7〇結構之單電子電晶體(如第十三圖及其相對應上 視圖所示）。 其中’當步騾(c)中的傾斜角度與步驟⑷中的 傾斜角度Θ2為相等時，則反應在鍍著於基材！表面上 該浮閑奈米量子點40與汲極奈米量子點5。之間的距離 ，就會等於該浮閘奈来量子點4()與源極奈米量子點 6〇之間的…(如第十三圖所示)；另該浮閑奈米量 子點40與閘極奈米量子點70之間的距離d3則是透過 '轉角度Φ的大小來控制(如第十二圖中之4-4剖視圖 所不）’因此，經由傾斜角度與旋轉角度①之容 易且可調控定位下’即可使該源極奈米量子點60、汲 極奈米量子點5。、浮間奈米量子點40及閘極奈米量子 .、之間的距離大小，或是單位面積上所需要的密产 等要求均能非常精準地達成，甚至各個量子點如被要求 各自有不同材質成份之要求時（例如：半導體、金屬等 材料)’亦僅需透過選用不同的鍍源材料Β來搭配即可 滿足其要求’使得本發明的適用範圍與應用擴充性極 廣’且其均又都是在室溫下可操作，故整體之效益相當 高但卻又價廉。 又’前述步驟“)、(〇、⑷及（e)之施作顺序 並非固定不變’當選擇步驟⑴做為首先完成之汲極 奈米量子點5°時’其他的浮閘奈来量子點40、源極奈 米量子點60及閘極奈米量子點7〇,仍可依傾斜角度及 旋轉角度的_來接續完成’且其最終之結果均相同。 另’前述步騾⑷中在奈米結構筒狀細孔ι〇的頂部 開口 η所形成奈米縮小口 2G的施作方式乃如第六圖所 示’其步騾包含： ⑴先將基材！置放固定於具有三維空間傾斜角度 1323516 及旋轉功能的旋轉傾斜檯RJl，並調整該旋轉傾斜檯r 成-傾斜角度如第六圖中纟a視圖所示，即該奈米 結構筒狀細孔10的頂部開口 u中心軸線與鍍源裝置 3〇的輸出方向之夾角度值為9〇。- Θ)’使得原子或分子 態的封口材料A能在奈米結構筒狀細孔10的頂部開口 U之最底端〇緣位置(如第六圖中之a視圖所對應側視 圖之圖號A所標示之處)上’產生局部堆積封口的結果 (如第/、圖a視圖及其所對應之側視目所示）；及 、⑺令該旋轉傾斜檯R固定在該傾斜角度0之傾斜 位置上’再經逐渐旋轉該旋轉傾斜檯R -圈後(如第六 圖中^、66、£等視圖及其各自所對應之各側視圖 =，則該原子或分子剛口材料A即可在奈米結The sub-type plating source material is directly and at the bottom position (as in the structure source device 30 of the nanohole 3 of the pattern Q in the fourth figure, the gas molecules or the ore are placed around the nanopore 3). (D). Finally, the solvent is used to obtain the desired nano-scale junction 2 on the resist surface, and then the nano-point 4 of the substrate can be formed (as shown in the fourth figure). ΖThe view shows that „the above-mentioned conventional process is limited by the precision of the existing lithography technology. The size can only be connected to the nano-hole 3 of the 60~65 mask ,, which limits the current most sophisticated Millet (nm), so the transfer exposure is from its nanometer size at 60 nm (nm) to 1323516, and the nanometer size of the nano-point 4 obtained by its preparation is also at 60 nm (nm). Above, so how to break through the nanometer scale of the nanopore 3, so that Bb is smaller than the nanometer (ΓΗΠ) required for a single electron transistor, is an industry expert in various fields • The technical difficulties of the decision, while at the same time complying with the principle that the cost should not be too high in the process of solving, so that the choice of technology breakthrough It is quite difficult to understand the advantages of the scientists of nanotechnology or the preparation of nanotechnology. They all know the benefits of making components smaller than 10 nm or as small as 2 nanometers, but still have no good results. A special method is proposed or published or applied. SUMMARY OF THE INVENTION The present invention is directed to a method for fabricating a single electron transistor using semiconductor lithography, the main purpose of which is to use a device that does not have to be changed or re-used under the existing semiconductor manufacturing process. By designing the accuracy of the original equipment, the single-electron transistor of the nanostructure can be accurately prepared, and at the same time, the size of the source, the floating gate, the (four) and the gate in the (IV) single-electron transistor can be achieved. The relative position, as well as the requirements for room temperature operation, to achieve mass production. Another object of the present invention is to provide a method for preparing a single electron 1: crystal using a semiconductor lithography technique, the steps of which are predetermined. Growing (type) on the top opening of the cylindrical structure pore 1323516 (P〇re) on the substrate (Substrate), deposited in an atomic or molecular state Opening the top of the cylindrical pore of the nanostructure, the diameter of the top opening is gradually reduced to form a reduced nano-aperture having a smaller diameter than the original top opening; (b) the substrate is Fixed in the horizontal direction, and then the gas source or atomic type of the plating source material is perpendicular to the nanometer shrinking port, and (4) the gas molecule or atomic type of forging material penetrates the nanometer shrinking port, and then directly The surface of the bottom substrate of the nano-structured cylindrical pores is plated to form a Linay quantum dot having the same diameter as the diameter of the nano-reduced port; (c) "The base is centered on the nano-small mouth. The right angle is inclined at an oblique angle, and the output direction of the gas source or atomic plated source material is unchanged, and the gas source or atomic plated source material is again penetrated through the nanometer narrowing port, that is, in the floating gate On the surface of the substrate on the right side of the quantum dot, a nano-nano quantum dot '(d) is plated, and then the substrate is tilted to the left by an inclination angle centered on the nanometer narrowing port, and the gas molecule or atomic type The output direction of the plated source material is unchanged. Passing the gas molecule or atomic plated source material through the nano-reduced D, which will 'plate a source nano-quantum dot on the surface of the substrate to the left of the floating-gate nano-quantum dot. (e) taking the center line of the nanometer narrowing opening as the axis, and matching a tilting angle with a rotating angle of rotation 'and the output direction of the gas source or atomic plated material is unchanged' and then passing through the gas molecule After the atomic type plating source penetrates the 12 1323516 nm shrinkage port, a gate nano quantum dot is plated on the surface of the substrate at the front side of the floating gate nano quantum dot; (f) finally removing the nano-meter structure cylindrical pores on the resist and the resist on the substrate by means of tanning agent washing (ie wet etching) or gas etching (ie dry etching). A single electron transistor having a nanometer quantum dot, a nanowire quantum dot, a source nano quantum dot, and a gate nano quantum dot structure can be prepared on the substrate. • [Embodiment] As shown in the fifth figure, the conventional semiconductor lithography process uses the binned-up or build-down method to obtain the existing nano-structured cylindrical pores 10, which is known as nanometer. The minimum size of the cylindrical pores of the structure can only reach 60 nanometers or 6 nanometers (nm) or more, and the preparation method can be selected to include lithography lithography technology, nano transfer technology (professional φ impnnting) ), molecular beam epitaxy (mbe), chemical vapor deposition (MOVCD), etc., but these technical methods are not the technical features and targets of the present invention, so here I will not repeat them. Continuing to refer to the fifth to thirteenth drawings, the present invention "method for preparing a single electron transistor using semiconductor lithography", the steps of which include: (a) in a predetermined growth (type) on a substrate (substrate) l Resist 2 on the nano-structured cylindrical pores (p〇re) 1〇 on the top opening 13 11 (as in the fifth figure, Β楣·Β楣β view does not) 'first with atoms Or the molecular sealing material Α 芸 芸 # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # Compared with the original top opening U纟, the diameter of the nano-reduced port (reduced job-aperture) 2 () (as shown in Figure 6 g and Figure 7); (b) the substrate 1 at the level In the direction, the source material B of the gas molecule or atomic form is perpendicular to the nanometer narrowing port 2, so that the gas source or atomic plated material B penetrates the nanometer narrowing port 20' Will be directly on the surface of the bottom substrate 1 of the cylindrical pores 10 of the nanostructure, and plated to form a diameter scale with the nanometer narrowing port 2 The same floating gate nano quantum dot 4〇 (as shown in the ninth figure); (C) the sling substrate 1 is tilted to the right by the tilting angle θ 1, centered on the nanometer narrowing opening 20, and the gas molecule or atom The output direction of the plating source material b of the type is unchanged, and the gas source or atomic plated material B is again penetrated through the nano-reduced port 20', which is located at the right side of the floating nano-quantum dot 40. On the surface of the substrate 1, a bismuth nano-quantum dot 50 is plated (as shown in the cross-sectional view of 2_2 in the tenth and tenth drawings); (d) the substrate 1 is further centered on the nano-port 2 0 Tilting an oblique angle Θ2' to the left and the source direction of the plating source material b of the gas molecule or atomic form is unchanged. 'The gas source or atomic plated source material B is again penetrated through the nano-reduced port 20'. A source-nano quantum dot 60 is plated on the surface of the substrate i at the left side of the floating nano quantum dot 40 (as shown in the cross-sectional views of the tenth-figure and the tenth-figure 3-3); (e) taking the center line of the nanometer narrowing port 20 as the axis, and matching the tilting angle θ with a rotation angle of rotation 1, and the gas molecule or the original The sub-type plating source material has the same output direction, and then passes through the gas source or the atomic type of the plating source material to penetrate the nano-reduced port, which is located at the front side of the floating nano-quantum dot 4G. On the surface of the substrate I, a gate nano-quantum dot 70 is plated (as shown in the cross-sectional view of FIG. 4 and FIG. 4 in FIG. 4); and (f) is finally washed with a solvent (ie, wet etching wet) EtchMng) or gas rot (ie dry etehing), etc., the resistance on the substrate ^ and the nano-structured cylindrical pores 1 on the resist 2 are eliminated, and can be prepared on the substrate 1. The floating nanometer quantum dot 40, the nanowire quantum dot 50, and the source nano quantum dot 6 have a nanometer scale. And a single-electron transistor with a gate of 7 〇 structure (as shown in the thirteenth figure and its corresponding upper view). Where the angle of inclination in step (c) is equal to the angle of inclination Θ2 in step (4), the reaction is plated on the substrate! The floating nanometer quantum dot 40 and the bungee nanometer quantum dot 5 are on the surface. The distance between the floating gate Nyle quantum dots 4 () and the source nano quantum dots 6 ... (as shown in Fig. 13); the floating nanometer quantum dots 40 The distance d3 from the gate nano quantum dot 70 is controlled by the magnitude of the 'turn angle Φ (as shown in the 4-4 cross-sectional view in Fig. 12). Therefore, via the tilt angle and the rotation angle 1 The source nanometer quantum dot 60 and the bungee nano quantum dot 5 can be easily and tunably positioned. The requirements for the distance between the floating nanometer quantum dots 40 and the gate nanometer quantum, or the density required per unit area can be achieved very accurately, even if the quantum dots are required to be different. When the material composition requirements (for example, semiconductors, metals, etc.), it is only necessary to match the requirements by selecting different plating materials, which makes the scope and application of the invention extremely expandable. They are all operable at room temperature, so the overall benefits are quite high but inexpensive. The 'previous steps'), (〇, (4) and (e) are not fixed in the order of 'When the selection step (1) is used as the first completed buckwheat nanometer quantum point 5°' other floats Nyle Quantum Point 40, source nano quantum dot 60 and gate nano quantum dot 7 〇 can still be completed according to the tilt angle and the rotation angle _ and the final result is the same. Another step in the above step (4) The nano-scale narrowing port 2G formed by the top opening η of the nano-structured cylindrical pores is formed as shown in the sixth figure. [The steps include: (1) The substrate is first placed and fixed in a three-dimensional space. The tilting angle 1323516 and the rotating tilting table RJ1 of the rotating function are adjusted, and the tilting angle of the rotating tilting table is adjusted as shown in the 纟a view in the sixth figure, that is, the central axis of the top opening u of the nanostructure cylindrical pore 10 The angle of the output direction with the output direction of the plating source device 3 is 9 〇. - Θ)' so that the sealing material A of the atomic or molecular state can be at the bottom end of the top opening U of the cylindrical pores 10 of the nanostructure. Position (as indicated by the figure A of the side view corresponding to the view in the sixth figure) 'The result of the partial accumulation of the seal (as shown in the /, view a and its corresponding side view); and, (7) the rotation of the tilting table R is fixed at the inclined position of the tilt angle 0 'and then gradually After rotating the rotating tilting table R-ring (as in the figure of ^, 66, £, etc. in Figure 6 and their respective side views =, then the atomic or molecular rigid material A can be in the nano knot
、'、細孔10的頂部開口 u上堆積出較頂部開口 U :口::為小的奈米縮小口 2。(如第六圖中g視圖及其對 應乙侧視圖所示）。 在前述步揉⑺中，另可對該旋轉傾斜, ', the top opening u of the fine hole 10 is stacked on the top opening U: mouth:: is a small nano-reduced port 2 . (As shown in the figure in Figure 6 and its corresponding side view). In the aforementioned step (7), the rotation can be tilted
:的圈數，以獲得更小口徑的奈米料口 2。,且J 米縮小口 20的丑这奈 的口#大小可利用市售之膜厚計來做即時 …溯，以作為控制旋轉傾斜檀Μ轉速度快慢的 ㈣入因而能達成所預期口徑大小的奈米縮小口 20， 、口單電子電晶體中各浮閘奈米量子點40、设極奈 17 米量子點50、源極奈米量子點6〇及閘極奈米量子點7〇 所需奈米尺寸規格的結構β 再者，在前述步騾（a)中的氣體分子或原子型態锻 源材料B係由鍍源裝置30所提供輸出，為使得氣體分 子或原子型態的鍍源材料B能以直線路徑方式穿透過 奈米縮小D 20 ’可於該鍍源裝置3〇與奈米縮小口 2〇 之間加裝—準直器Y(如第八圖所示），其能有助於導引 該氣體分子或原子型態鍍源材料Β的行進方向更為一 致性，進而增加基材1之表面上所形成各浮閘奈米量子 點40、汲極奈米量子點5〇、源極奈米量子點⑼及閘極 奈米量子點70的可靠度。 續如第十四圖至第十七圖所示，為使汲極奈米量子 點5〇 '源極奈米量子點60及閘極奈米量子點70能與 其他電子元件或導線行相容導接，必須加大或加寬其尺 寸，則在前述步驟（c)中，更可將該向右傾斜之傾斜 角度04逐渐加大’使該氣體分子或原子型態的鍍源材 料Β不斷地經由奈米縮小口 2〇 ,而逐渐堆積鍍著形成 條狀的汲極奈米線50a (如第十四圖及第十四圖中5_5 剖視圖所示）；同樣地，該步騍（d)中，更可將該向左 傾斜之傾斜角度Θ5逐渐加大，使該氣體分子或原子型 態的鍍源材料B不斷地經由奈米縮小口 2〇，而逐渐堆 1323516 積鍍著形成條狀的源極奈米線60 (如 、卻第十五圖及第十 五圖中6-6剖視圖所示）；而該步驟（ ;甲，更可將該 倾斜角度逐渐加大，並配合旋轉角度φ，使該氣體分 或原子型態的鍍源材料Β不斯地經由奈来縮小口 2。子 而逐渐堆積鍍著形成條狀的間極奈米線7〇a (如第十六 圖及第十六圖"-7剖視圖所示);經由前述步驟之施、 作，即可獲得具有與其他電子元件或導線行相容導接功 能之單電子電晶體。 再如第十八圖至第二十二圖所示，為使得前述中該 汲極奈錢50a、源極奈米線6〇a、閑極奈米線？〇a三 者的末端部加1 ’更可在步騾（c)、步騾（d)及步驟 (e)中，分別調控加大旋轉角度φ1、φ2、φ3、φ4， 即可獲得具有更寬末端部汲極奈米線5〇b、源極奈米線 60b、閘極奈米線70b之單電子電晶體。 综上所陳，採用本發明製備單電子電晶體的方式， 可透過調控適當的傾斜角與旋轉角以及奈米縮小孔孔 徑等參數，即能精確地控制其源極、汲極、浮閘及閘極 等量子點間的位置、大小、成份以及密度等條件，且其 均是在室溫下來操作，並與現今的半導體微影製程相 容’故變得極為簡易且製備成本低廉又達到大量生產， 確實是製備單電子電晶體技術上的一大突破，符合產業 19 =:r_、f用性及進步性之要件 第一圖：係單電子電晶體的基本電路圖。 第圖係習用奈米轉印技術微影製程中光罩與基材的 立體示意圖。 第二圖：係第二圖中A_A線的剖面視圖。: The number of turns to get a smaller diameter of the nanometer port 2 . , and the size of the mouth of the ugly mouth of the J-meter is 20, and the size of the smear can be made by using a commercially available film thickness meter as a control for the speed of the rotation of the slanting slanting shovel. The nanometer shrinking port 20, the floating nanometer quantum dot 40 in the single-electron transistor, the nanometer quantum dot 50, the source nano quantum dot 6 〇, and the gate nano quantum dot 7 〇 Structure of the nanometer size specification Further, the gas molecule or the atomic type forging material B in the aforementioned step (a) is supplied from the plating source device 30, and is a plating source for gas molecules or atomic states. Material B can penetrate through the nanometer in a straight path to reduce D 20 ' can be installed between the plating device 3 〇 and the nanometer narrowing port 2 — collimator Y (as shown in the eighth figure), which can The direction of travel of the gas molecule or the atomic material source material is more uniform, thereby increasing the floating gate nano quantum dots 40 and the bucking nanometer quantum dots 5 formed on the surface of the substrate 1. The reliability of 〇, source nano quantum dots (9) and gate nano quantum dots 70. Continued as shown in Figures 14 through 17, in order to make the bungee nanometer quantum dot 5 〇 'source nano quantum dot 60 and gate nano quantum dot 70 compatible with other electronic components or wires In the above step (c), the inclination angle 04 of the rightward inclination may be gradually increased to make the gas source or the atomic type of the plating source material continuously. The ground is narrowed by the nanometer 2, and gradually stacked to form a strip-shaped bungee nanowire 50a (as shown in the cross-sectional view of Fig. 4 and Fig. 5-5); similarly, the step (d) In the middle, the tilt angle Θ5 tilted to the left may be gradually increased, so that the gas source or atomic material of the plating source B is continuously narrowed through the nanometer 2, and gradually stacked 1323516 to form a strip. a source of nanowires 60 (as shown in the fifteenth and fifteenth views of the fifteenth and fifteenth views); and that step (; A, the angle of inclination can be gradually increased, and with rotation The angle φ causes the gas source material of the gas or atomic type to shrink through the port 2 and gradually accumulate Forming a strip of inter-phase nanowires 7〇a (as shown in the sixteenth and sixteenth <-7 cross-sectional views); through the foregoing steps, it can be obtained with other electronic components or The single-electron transistor with the wire line compatible with the guiding function. As shown in the eighteenth to twenty-secondth figures, in order to make the above-mentioned bungee money 50a, the source nanowire 6〇a, the idle pole In the step (c), step (d), and step (e), the rotation angles φ1, φ2, φ3, and φ4 are respectively adjusted in the step (c), step (d), and step (e) of the nanowires? A single-electron transistor having a wider end portion of the ruthenium nanowire 5〇b, the source nanowire 60b, and the gate nanowire 70b can be obtained. In summary, the method for preparing a single electron transistor by the present invention is obtained. The position, size, composition and density of quantum dots such as source, drain, floating gate and gate can be precisely controlled by adjusting the appropriate tilt angle and rotation angle, and the parameters such as the hole diameter of the nanometer. Conditions, and they all operate at room temperature and are compatible with today's semiconductor lithography processes. Low cost and mass production, it is indeed a breakthrough in the preparation of single-electron transistor technology, in line with the industry 19 =: r_, f usefulness and progressiveness of the first figure: the basic circuit diagram of a single electronic transistor. The figure is a three-dimensional diagram of the mask and the substrate in the lithography process of the nano transfer technology. The second figure is a cross-sectional view of the A_A line in the second figure.
第四圖:係習知半導體微影製程製備奈米點結構之流程 不意圖。 第五圖：係習知利用半導體微影製程所得出奈米結構圓 筒狀細孔的立體示意圖。 第/圖/係本發明在奈米結構圓筒狀細孔的頂部施作奈 米縮小D之流程示意圖。Figure 4: Flow of the preparation of nano-dots by the conventional semiconductor lithography process. Fig. 5 is a perspective view showing the cylindrical pores of the nanostructure obtained by the semiconductor lithography process. Fig. / Fig. / is a schematic view showing the flow of the nanometer reduction D on the top of the cylindrical pores of the nanostructure.
第七圖：係本發明在奈米結構圓筒狀細孔的頂部完成奈 米縮小D之剖面示意圖。 第八圖：係本發明在基材表面上長成單電子電晶體所需 奈米量子點之作動示意圖。 第九圖：係本㈣在基材表面上製#單電子電晶體之源 極奈米量子點的流程示意圖。 ' 第十圖：係本發明在基材表面上製備單電子電晶體之汲 極奈米量子點的流程示意圖。 第十一圖：係本發明在基材表面上製備單電子電晶體之 20 1323516 .浮閘奈米量子點的流程示意圖。 圖係本發明在基材表面上 觖拉去 衣厢早黾子電晶體之 _ 奈米量子點的流程示意圖。 第十二圖：係本發明在基 灯录面上兀成阜電子電晶 奈米量子點的示意圖。 各 第十四圖：係本發明欢 發月在基材表面上製備單電子電晶體之 第十五圖 汲極奈米線的示意圖。 :係本發时基材表面上㈣單t子電晶體之 源極奈米線的示意圖。 第十六圖 係本發明在基材表面上製備單電子電晶體之 閘極奈米線的示意圖。 第十七圖 係本發明在基材#面上完成具有浮閘奈米量 子點、汲極奈米線、源極奈米線及閘極奈米 線之單電子電晶體的示意圖。 第十八圖：係、本發曰月中製備汲極奈米線末端部加寬的作 動不意圖之一。 第十九圖·係本發明中製備汲極奈米線末端部加寬的作 動不意圖之二。 第二十圖：係本發明中製備源極奈米線末端部加寬的作 動示意圖之一。 的 第二十一圖：係本發明中製備源極奈米線末端部加寬 21 作動示意圖之二。 圖：係本發明在基材表面上完成具有末端部加 寬之汲極奈米線、源極奈米線及閘極奈米 線的單電子電晶體示意圖。 【主要元件符號說明】 u基材 2·阻劑 3-奈米孔 4-奈米點 10-奈米結構筒狀細孔 頂部開0 2〇-奈米縮小D 3〇-鍍源裝置 4〇-浮閘奈米量子點 5〇-汲極奈米量子點 5〇a ' 50b-汲極奈米線 6〇-源極奈米量子點 60a ' 60b-源極奈米線 70·閘極奈米量子點 70a ' 70b-閘極奈米線 A-封口材料 B-氣體分子或原子型態的鍍源材料 C-電容 D-汲極 G-閘極 I-浮閘 M-光罩 Q-奈米圖形 R-旋轉傾斜檯 s-源極 Y-準直器 θ、Θ1、Θ2、Θ4、Θ5·傾斜角度 φ、Φ1、Φ2 ' Φ3、Φ4-旋轉角度Fig. 7 is a schematic view showing the cross section of the nano-reduced D on the top of the cylindrical pores of the nanostructure. Figure 8 is a schematic view showing the operation of the nano quantum dots required for the invention to grow into a single electron transistor on the surface of the substrate. The ninth picture: the system (4) on the surface of the substrate made # single electron transistor source of the nanometer quantum dot flow diagram. Fig. 10 is a schematic view showing the flow of a nanometer quantum dot of a single electron transistor on the surface of a substrate of the present invention. Eleventh drawing is a schematic flow chart of the preparation of a single electron transistor 20 1323516. Floating gate nanometer quantum dot on the surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS The flow chart of the present invention is carried out on the surface of a substrate to remove the nano quantum dots of the chamber. Twelfth Figure: A schematic view of the present invention in the formation of a germanium quantum dot on an electron-electric crystal on a base lamp recording surface. Each of the fourteenth drawings is a schematic view of a fifteenth diagram of a single-electron transistor prepared on the surface of a substrate in the present invention. : A schematic diagram of the source nanowire of a (iv) single-t transistor on the surface of the substrate. Fig. 16 is a schematic view showing the preparation of a gate nanowire of a single electron transistor on the surface of a substrate. Fig. 17 is a schematic view showing a single electron transistor having a floating gate nanometer quantum dot, a silicon germanium nanowire, a source nanowire, and a gate nanowire on the substrate # surface. Figure 18: One of the actions of the system to prepare for the widening of the end portion of the bakelite nanowire. Fig. 19 is a second intent of the action of preparing the end portion of the bakelite nanowire in the present invention. Fig. 20 is a view showing one of the operation diagrams for preparing the end portion of the source nanowire in the present invention. The twenty-first figure is the second schematic diagram of the operation of preparing the end portion of the source nanowire in the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig.: A schematic diagram of a single electron transistor having a terminal nanowire, a source nanowire and a gate nanowire on the surface of a substrate. [Main component symbol description] u substrate 2·resistance 3-nano hole 4-nano point 10-n structure cylindrical hole top open 0 2〇-nano reduction D 3〇-plating source device 4〇 -Floating nanometer quantum dot 5〇-汲 pole nanometer quantum dot 5〇a ' 50b-汲 pole nanowire 6〇-source nanometer quantum dot 60a ' 60b-source nanowire 70·gate Meter quantum dot 70a ' 70b-gate nanowire A-sealing material B-gas molecule or atomic type plating source material C-capacitor D-drain G-gate I-floating gate M-mask Q-nai Meter graph R-rotation tilt table s-source Y-collimator θ, Θ1, Θ2, Θ4, Θ5· tilt angle φ, Φ1, Φ2 ' Φ3, Φ4-rotation angle