TWI321840B - Low-capacitance bonding pad for semiconductor device - Google Patents

Description

1321840

V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) 1. Field of the Invention The present invention relates to a semiconductor element having a structure in which a semiconductor device has a low capacitance pad.植 植 I, [Prior Art] Electronic products are increasingly inclined to light, thin, car, ^ ^ sister small trend. In the case of a ship, in the wafer process technology and packaging technology, people tend to hate this trend. However, under the limitation of the welding machine, the size of the bonding pad is not reduced by the reduction of the 70-line width, because the size of the soldering iron is not 00 „ ^ ^ ^ J eight Not small' and is heavily weighted by the pad

The area of the stacked substrate is large. 0, the solder fillet still has a high parasitic capacitance. In addition, the 'pee Bu ff effect' usually occurs in the process steps of soldering the wire, resulting in a significant reduction in the degree. Because of the large input capacitance generated by the pad to input the electrostatic discharge (ESD) protection component, the tea usually limits the input/output (I/O) signal in the south speed integrated circuit. The circuit is, for example, a DRDRAM (Direct Rambus DRAM) or a radio frequency (RF) integrated circuit. Although the deep metal micron complementary metal oxide semiconductor (CM0S) technology can greatly reduce the size of the integrated circuit, the size of the pad is still limited.

1^21840

Yu Feng picks up the machinery, and the thief will count the wall,],. Forces such as su hold an A* inch in the entire wafer area, the area of the substrate to be covered with a large area has a considerable area, thereby causing high parasitic capacitance and reducing the execution speed of the integrated circuit, or need to be more Large wafer area to form a stronger and more powerful drive circuit. In addition, the input pad is captured by an ESD protection component located on the wafer to protect the internal circuitry from damage caused by electrostatic discharge. ^ Withstanding high electrostatic discharge, ESD protection components typically have a large π-piece size. Therefore, the ESD protection component can provide a large parasitic capacitance of the input pad. As shown in the first figure, it is a semiconductor element having a pad structure on a substrate. The semiconductor component includes a dielectric layer 110 overlying the substrate. A glow pad structure 200 is positioned over the dielectric layer 110. The pad structure 2 is composed of a plurality of metal layers 210, 220, 230 and a top metal layer 240. Further, the 'multilayer metal layers 210, 220, and 230 are located within the plurality of dielectric layers 212, 222, and 232. Furthermore, each of the plurality of metal layers and the adjacent metal layers are disposed within the plurality of dielectric layers 212, 222, and 2 32, and the plurality of via plugs 214, 224, and 234 are coupled to each other. In order to avoid the peeling effect occurring on the pad structure 200 composed of a flat multi-layer metal layer, it is generally used to increase the adhesion between the dielectric layer and the metal layer during wire bonding using some structures and materials. When more metal layers are used, the peeling effect on the pad structure 2 会 will be easy to

Page 7 1321840 V. INSTRUCTION DESCRIPTION (3) The higher parasitic capacitance is generated on the pad structure 200 because the distance between the metal layer and the substrate 100 is too close. Referring to the second figure, another semiconductor component having a low parasitic capacitance solder bump structure is shown. The semiconductor device includes a dielectric layer 31 上方 above the p_type substrate 300, wherein the P-type substrate 300 has a well region 304 having a second conductivity such as an N_ type, and has The first conductivity is like? The doped region 302 of the _ type is located in the N-type well region 304, and the P-type doped region 3 〇 2 can be regarded as a diffusion region. Additionally, a pad structure 400 is provided over the dielectric layer. The θ solder bump structure 400 comprises a stacked metal layer stacked and positioned over the p-type substrate 3〇〇 and aligned? A top metal layer 440 of the doped region 312. The stacked metal layer in this embodiment is a 4-layer' comprising a plurality of metal layers 410, 420, 430, 440, and a plurality of dielectric layers 412, 422, and 432. In addition, the metal layers 41, 420, 430, and 440 and the plurality of dielectric layers 412, 422, and 432 are alternately stacked above the 卩-type substrate 300. "And each of the multiple metal layers is located adjacent to the adjacent metal layer. Within the multilayer dielectric layers 412, 422, and 432, a plurality of via plugs 414, 424, and 434 are coupled to each other. Since the doping region 302 is located under the pad structure 400, the pad structure 400 has a lower parasitic capacitance because the bonding capacitor is connected in series in the P-type substrate 3〇〇. form.

1321840 V. DESCRIPTION OF THE INVENTION (4) According to the semiconductor element structure described above, there is a junction capacitance Cp between the well region 304 and the P-type replacement region 3〇2; and the N-type well region 304 There is a junction capacitance CN between the P-type substrate 300 and the P-type substrate 300. Therefore, a total equivalent capacitance CMeq (total equivalent capacitance) is provided by the metal layers 4i, 420, 430, and 440. Therefore, all the capacitors Cp, q, and tq in the semiconductor element are spliced in series, so that the parasitic capacitance of the entire pad structure 4 〇 可以 can be effectively reduced. III. [Invention] The can according to the present invention 'provides a structure having a low capacitance pad on a substrate' and combined with a double well complementary CMOS technology, thereby reducing the top metal and substrate Parasitic capacitance between. It is an object of the present invention to provide a low capacitance pad structure for reducing the total pad capacitance between the substrate and the top metal layer. The purpose of the present invention is to integrate triple well technology to form a triple well.

Structured in a substrate having a first conductivity to reduce the total pad capacitance D between the substrate and the top metal layer

1321840 V. INSTRUCTIONS (5) Bonding capacitors are provided and coupled in series so that the parasitic capacitance of the pads can be effectively reduced. In view of the above, for a semiconductor device, the present invention provides a structure in which a low capacitance pad is combined with a triple well. The semiconductor component includes a substrate, a dielectric layer over the substrate, a pad structure over the dielectric layer, and a passive layer over the pad structure. The first well region having a first conductivity such as an N-type is present in the substrate. A second well region having a second conductivity, such as a P-type, is located within the first well region, wherein the first conductivity and the second conductivity are opposite conductivities. A doped region having a second conductivity, such as a diffusion region, is located in the second well region having the second conductivity. The pad structure comprises a plurality of metal layers and a top metal layer. The multilayer metal layer is composed of a plurality of metal layers and a plurality of dielectric layers, wherein a plurality of metal layers are buried in the dielectric layer, and the respective metal layers are separated by a dielectric layer. _ having a first junction capacitance between the doped region having the second conductivity and the first well region having the first conductivity, the first well region of the first conductivity and the second well of the second conductivity The region has a second junction capacitance, and a third junction capacitance between the second well region of the second conductivity and the substrate, and the junction capacitors are coupled in series, thus, on the substrate and the top layer ^ The total pad capacitance between the metal layers can be effectively reduced, and the noise of the substrate can be improved. Fourth, [Implementation]

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丄 JZ_L04U

Some embodiments of the invention will be described in detail, and the invention will be further described. However, the scope of the present invention is not to be construed as being limited to the scope of the present invention, and the scope of the month is not limited, which is based on the scope of the following patent. In the conventional semiconductor device, the structure is affected, and the reliability of the solder pad of the zinc pad capacitor is affected. Therefore, the present invention provides a pad capacitance. To reduce the weld between the substrate and the top metal layer

The invention mainly provides a semiconductor material having a low capacitance, a substrate of a 4, '----------------------------------------------------------------------------------------------------------------------------------------------------------------- The substrate having the triple well structure has a second conductive diffusion region, a first female region having a first conductivity, and a second well region having a second conductivity. There is a first junction capacitance between the first well region and the diffusion, a second junction electric valley between the first well region and the second well region, and a third junction between the second well region and the substrate capacitance. Its first, second and third junction capacitances are removed by the pad structure

Total #:!: The capacitors are drained in series, so that the parasitic capacitance between the substrate and the top metal layer can be effectively reduced. In addition, according to a preferred embodiment of the present invention, a semiconductor component having a pad structure combined with a triple well complementary metal oxide semiconductor technology can be used.

Page 11 1321840 V. INSTRUCTIONS (7) Effectively reduce the total parasitic capacitance and improve the noise of the substrate. Referring to the third figure, the semiconductor device comprises a substrate 10 having a first conductivity such as p-type, a dielectric layer 20 over the P-type substrate 10, and a solder bump structure on the dielectric layer 20 ( The b〇nding pad structure 30 and a passivation layer 70 having a 〇pening 72 are located above the pad structure 3〇. Using the triple well complementary MOS technology 'the first doped region 12 having a second conductivity in the P-type substrate 1 、, the first well region 14 having the first conductivity is located at the second conductivity Below the first doped region 12, and a second conductive second well region 16 are located below the first well region 14, and the second well region 16 can be considered a deep well region. Wherein, the first conductivity is opposite to the electrical conductivity of the second conductivity. The triple well structure in the above P-type substrate 1 is formed by the well-known triple well technique, and its steps are briefly described as follows: using conventional diffusion or ion implantation (ion implantati〇) n), implanting an N-type dopant in the P-type substrate 1〇 to form a first doped region 12 having a second conductivity; implanting p_ type by ion implantation An ion such as arsenic (As) or phosphorus (P) 'forms a first well region having a first conductivity' 14 in the P-type substrate 10, which is located below the first doped region 12; A dopant, such as boron (B), forms a second well region 26 having a second nature, which is located below the first well region 14. Therefore, the dopant concentration of the second conductivity second well region 16 (d〇pant, $

Page 12 1321840 V. Inventive Note (8) " - concentration), higher than the dopant concentration of the first well region u having the first conductivity, and the doping of the first well region 14 having the first conductivity The impurity concentration is higher than the dopant concentration of the first doping region 具有2 having the second conductivity. Thereby, a triple well structure is formed in the P-type substrate 1 〇. Next, a dielectric layer 2 is placed over the P-type substrate. A pad structure 3 is located above the dielectric layer 2A. Pad structure 30 includes a multilayer metal layer structure overlying the dielectric layer and a top metal layer. The multilayer metal layer structure 'in this embodiment is four layers, which includes a plurality of metal layers 32, 42, 52, 62, and a plurality of dielectric layers 34, 44, and 54. Further, a plurality of metal layers 32, 42, 52, 62 and a plurality of dielectric layers 34, 44, and 54 are alternately stacked over the dielectric layer 2A and the P-type substrate 1A. 5. Between the first of a conductivity as described above, having a first capacitance); and the second of the second conductivity having a second conductive triple junction capacitance C3. Capacitance (total a parasitic capacitance of the to a a equ body element, a third junction electrical first junction capacitance, a P-type substrate 10 having a triple well structure, having a well region 14 and a first doping having a second conductivity The impurity region 12 has a junction capacitance C! (junction has a second junction capacitance between the first well region 14 having the first conductivity and the well region 16; and the second well region 16 and P- The type of substrate 1 has a first and a capacitance is provided by the pad structure 30 for a total equivalent lvalent capac i tance )CHeq. Therefore, the semiconducting capacitance can be made up of the first junction capacitance, the second junction capacitance, and the total equivalent amount. Capacitance is obtained, and the total equivalent capacitance, the second junction capacitance, and the third junction capacitance are connected in series

1321840 V. INSTRUCTION DESCRIPTION (9) The coupling of the type enables the parasitic capacitance of the semiconductor element to be effectively reduced. Further, in the present invention, each of the metal layers 32, 42 and 52 is exposed to the adjacent metal layers by via plugs 36, 46 and 56. In the present invention, the locations of the via plugs 36, 46 and 56 are not limited to being aligned with adjacent via plugs. Alternatively, misalignment may be utilized to achieve coupling with adjacent metal layers. Further, for the subsequent soldering wire step, a passive layer 7〇 having a pad opening 72 is formed over the top metal layer 62 so that subsequent pad wires can be formed in this opening 72. According to the above, the advantages of the present invention are as follows: First, the transfer region having the second conductivity is located in the p-type substrate such that the contact capacitance of the doped region and the capacitance of the pad structure are in series Way to consume. Therefore, the parasitic capacitance of the pad structure can be reduced. Second, the present invention is a triplet complementary MOS technology. The junction capacitance between the pad structure and the P-type substrate is coupled in series so that the total pad capacitance can be effectively reduced, and at the same time the noise of the ρ_ φ group substrate can be changed. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the claims of the present invention;

Page 14 1321840 V. INSTRUCTIONS (ίο) Equivalent changes or modifications made under the spirit shall be included in the scope of the following patent application.

IHHI Page 15 1321840 BRIEF DESCRIPTION OF THE DRAWINGS The first figure is a structural side view of a semiconductor component having a conventional RF pad structure using conventional techniques; the second figure is a conventional pad structure using conventional techniques. A side view of a semiconductor component; and a third side view of a semiconductor component having a pad structure in combination with triple well technology in accordance with the teachings of the present invention. Representative symbols for the main part: 10 P-type substrate 12 N+ doped region 14 P-type first well region 16 N-type second well region 20 dielectric layer 30 pad structure 32, 42, 52, 62 metal Layers 34, 44, 54 Dielectric layers 36, 46, 56 Dielectric plugs 70 Passive layers 72 Pad openings 100 Substrate 110 Dielectric layer 200 Pad structure

1321840 Schematic description 210, 220, 230, 240 metal layer 212, 222, 232 dielectric layer 214, 224, 234 via plug 3 00 substrate 302 P + doped region 3 04 N_ well 400 soldering Pad structure 410, 420, 430, 440 metal layer 412, 422, 432 dielectric layer

414, 424, 434 interfacial embolism

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Claims (1)

1321840 6. Patent application scope 1. A semiconductor component combining a triple well structure and a pad structure, the semiconductor component combining the triple well structure and the pad structure comprises: a substrate having a triple well structure, the triple well structure Having a doped region having a conductivity in the substrate, having a first conductivity, a first well region is located within the substrate and below the doped region, and has a second conductivity The second well region is located within the substrate and below the first well region; and a pad structure is positioned above the substrate. 2. The semiconductor component of the triple well structure and the pad structure according to claim 1, wherein a dopant concentration of the second well region having the second conductivity is higher than the first component Conductivity of one of the first well regions. 3. The semiconductor device according to the first aspect of the invention, wherein the conductivity of the first conductivity is opposite to the conductivity of the second conductivity. 4. The semiconductor component of the triple well structure and the pad structure according to claim 1, wherein the dopant concentration of the first well region is higher than a dopant concentration of the dopant region. 5. The semiconductor component of the triple well structure and the pad structure according to claim 1, wherein the pad structure comprises: The invention relates to a semiconductor component having a low capacitance pad structure according to claim 8, wherein the conductivity of the first conductivity is opposite to the conductivity of the second conductivity. The semiconductor component having a low capacitance pad structure according to claim 8, wherein a dopant concentration of the second well region having a second conductivity is higher than the first conductivity The dopant concentration of one of the first well regions. 1 1. The semiconductor component having a low capacitance pad structure according to claim 8, wherein the dopant concentration of the first well region having the first conductivity is higher than the conductivity. One of the doping regions has a dopant concentration. 12. The semiconductor device having a low capacitance pad structure according to claim 8, wherein each of the plurality of metal layers utilizes a plurality of via plugs in each of the plurality of dielectric layers and adjacent thereto Each of the plurality of metal layers is coupled.