TWI321308B - Data receiver - Google Patents

Description

[Technical Field] The present invention relates to a data receiving unit, and a data receiving unit having a digital starting circuit.

[Prior Art] With the advancement of optical technology and semiconductor technology, liquid crystal display device (Crystal Disp丨ay; LCD) has been widely used in devices. The liquid crystal display has the advantages of high image quality, small size, light weight and low power: it has the advantages of inactivity, low power consumption and wide application range, so it has been widely used in portable TVs, mobile phones, video recorders, It is the mainstream of displays in consumer electronics or computer products such as notebook computers, desktop monitors, and projection TVs. · . In the liquid crystal display, the source driver (source Dr) converts the digital signal into an analog voltage value for transmitting image signals to the display, so it is also called a data driver. The liquid crystal display has a panel. Multiple source drivers, including multiple data receiving units (Data • Receiver), can be used for data transmission. To save power consumption, the data receiving unit in the source driver will be turned off when not in operation (Power Down) 'Wake Up when you want to operate, so the LCD panel has multiple data receiving units, but there will only be one data receiving unit. The rest of the data receiving units are turned off. In other words, the liquid crystal = display medium receiving unit is activated in turn, and then turns off in turn. 凊 Referring to Figure 1, the i-th diagram shows a schematic diagram of the conventional data receiving unit without moving 1321308. It is shown that when the data receiving unit does not operate, the control signal input by the control signal input terminal 102 is high, and the inverting control signal input terminal 104 is The input inverting control signal is low, so that the transistor 106 is turned off, the transistor 108 is turned on, and the power supply voltage (Vdd) charges the point a, so that the voltage at point A rises, and therefore, the transistor is turned off. In this way, no current flows through the differential pair U2'. At this time, the data receiving unit does not operate. Although the -before receiving unit is activated, the input inverting control signal is high, and the control is performed. The signal is low, so the transistor 丨〇8 is turned off, the transistor 〇6 is turned on, and the voltage at point A is lowered. Therefore, the transistor i 1 〇 is turned on, and the current flows through the differential circuit 112, and the data receiving unit operates. However, in this way,

Heart, heart, and f丨*'s thorns use frequency of the receiving unit. In the current prior art, for passing A to Φ廒, kk m丨k1

The capacitive start-up circuit has the disadvantage of being unstable, the power smash (Vgs). However, in this way, the speed of winning is still not fast enough. In addition, the instantaneous discharge amount of the voltage at point A is different from the voltage at point a when the voltage at point a is returned to the operating power supply voltage, and they are also changed. The influence of the source electric grinder

I f Ming content J Therefore, the object of the present invention is to have a digital start circuit for β. Providing a kind of data receiving unit, another object of the present invention is to provide... quickly return to a normal state at startup. The material can be received earlier than the different electricity == the purpose is to provide - the data receipt can be in the area. The same digital start circuit is used under the power supply, which can greatly reduce the above-mentioned object of the present invention, and proposes a data receiving unit. The above-mentioned Becko receiving unit includes at least a current mirror and a starting circuit. The start circuit is coupled to the common gate of the current mirror, and the start circuit includes at least a pulse generating circuit and a first electric circuit. The pulse generating circuit generates a pulse, and the first switching circuit is based on the pulse. Selectively turning on the common gate of the current mirror and a first voltage. According to a preferred embodiment of the present invention, at least a current source is coupled to the current mirror and the first voltage. The current mirror includes at least a first transistor and a second transistor, the source of the first transistor is coupled to the second voltage, the closed end of the first transistor is coupled to the drain of the first transistor, and the source of the second transistor is coupled to the second voltage. Further, at least a second switching circuit is disposed on the common gate path of the current mirror for selectively conducting the common gate terminal of the current mirror. Further, at least one differential circuit is connected to the current mirror. Including a third switch 2: the common gate of the current mirror and the common terminal of the first current mirror and the second voltage, the timing, the Thunder', the second switch circuit is turned on, the gate terminal Disconnected, and When the IM is # iT, s cloth-switching circuit is disconnected, the current ', the gate terminal is turned on. The second voltage is greater than the first voltage. According to another object of the present invention, a starting circuit in the data receiving unit is suitable for - -Electric, 'shovel unit contains at least one current source, one: electro-crystal 胄' current mirror - the input end is coupled to the input end of the current source. One of the current mirrors is coupled to a first voltage, the first voltage, the first One of the transistors is lightly connected to the first voltage, the first __ transistor and the current mirror-to-gate terminal, and the starting circuit is coupled to the common gate of the current mirror. The above starting circuit includes at least a pulse generating circuit and a second transistor. The pulse generating circuit is configured to generate a pulse. The second transistor is connected to the pulse generating circuit, and one of the second transistors is coupled to the common gate of the current mirror. One source of the second transistor is coupled to a second voltage, wherein the pulse generating circuit generates a pulse and turns on the second transistor to reduce the common gate extreme voltage of the current mirror, thereby starting the current mirror. According to the invention In a preferred embodiment, the first transistor is a P-type transistor, and the second transistor is an n-type transistor, and the first voltage is greater than the second voltage. The pulse generating circuit includes at least a first inverter. a second inverter and a reverse gate. The first inverter has an input for inputting a first signal, and one of the input terminals of the second inverter is coupled to one of the outputs of the first inverter. The first input end of the reverse gate is coupled to one of the output ends of the second inverter, and the second input end of the reverse gate is used for inputting a second signal, wherein the phase of the first signal and the second signal Conversely, when the first signal and the second signal are rotated, the 1321308 gate first receives the second signal, and then receives the first signal to generate the pulse β. According to another object of the present invention, a pulse generating circuit is provided, at least The first inverter includes a first inverter, a second inverter and a reverse gate. The first inverter has an input terminal for inputting a first signal. One of the input terminals of the second inverter is coupled to one of the outputs of the first inverter. The first input end of the reverse gate consumes one of the output ends of the second inverter, and the second input end of the reverse gate is used to input a second signal, wherein the phase of the first signal and the second signal in contrast. When the first signal and the second signal are rotated, the reverse gate first receives the second signal and then receives the first signal to generate a pulse. According to another object of the present invention, a source driver is proposed, comprising at least the above-described data receiving unit. According to another object of the present invention, a display system is provided, comprising at least the source driver described above. According to another object of the present invention, a control method for a data receiving unit is proposed for use in a source driver. This control method includes at least the following steps. First, according to a first control signal, a data receiving unit is closed. Then, 'the first control signal and the second control signal are generated according to the first control signal. Then, according to the pulse signal, the data receiving unit is activated. The first control signal is opposite to the second control signal. [Embodiment] In order to make the present invention more detailed and complete, reference is made to the following description in conjunction with the drawings of Figs. 3 to 5. Please refer to FIG. 3, which is a schematic diagram of a 1320308 beacon receiving unit according to a preferred embodiment of the present invention. The present invention is a data receiving unit having a digital starting circuit. The data receiving unit of the preferred embodiment of the present invention includes a transistor 3G2, a transistor 3G4, a transistor alone, a transistor ground, an electric 'origin 310 differential circuit 312, a transistor 314, and a pulse generating circuit* The transistor 302, the transistor 304, the transistor 3〇6, and the electromorphic body: 08 is a p-type transistor, and the transistor 3 14 is a patterned transistor. In addition, the transistor 314 and the pulse generating circuit 4A constitute a starting circuit, and the transistor_______ The wheel end of the current mirror is coupled to the input of the current source 31 (), and the output of the current mirror is coupled to the differential circuit 312. As shown in FIG. 3, the source of the transistor 3〇6 and the transistor 3〇8 is electrically connected to the gate of the power supply M (Vdd)', and the gate of the crystal 306 is electrically connected to the gate and the transistor of the transistor 302. The 314 is infinite, the gate of the transistor 3〇8 is electrically connected to the source of the transistor 302, and the gate of the transistor 3〇8 is electrically connected to the gate of the transistor and the input terminal of the current source 31〇, The negative electrical connection of the crystal 3〇6 is _the circuit 312, and the transistor 3〇4 is connected between the power supply dust and the transistor 极. The pulse generating circuit is electrically connected to the transistor 314. The source of the transistor 314 is electrically connected to the ground voltage (Vss), the gate of the transistor is electrically connected to the control signal 424, and the closed electrode of the transistor 3〇4 is electrically connected to the inverted control signal 422. Please refer to FIG. 4 and FIG. 5 again. FIG. 4 is a schematic diagram showing a pulse generating circuit according to a preferred embodiment of the present invention. The fifth circle shows the timing of the pulse generating circuit according to the preferred embodiment of the present invention. Figure. As shown in Fig. 4, the pulse generating circuit 400 includes at least a plurality of inverters connected to the -reverse 410 coupling 10 1321308. As shown in Fig. 4 and Fig. 5, when the start signal (CLK_SUS) changes from 1 to 0, the 'start signal will also change from 1 to 0. After the inverter 402, the inverted control signal 422 will be changed. After 1, after the inverter 404, the control signal 424 will change from 1 to 〇 ^. After the control signal 424 is passed through the inverter 406 and the inverter 408, the inverse gate input signal 426 will still be 1 The state becomes 0, wherein the inverse gate input signal 426 is the result of the control signal 424 passing through the two inverters. The inverted control signal 422 of the other input end of the gate 410 is changed from 〇 to 1, however, since the inverse gate input signal 426 passes through three inverters more than the inverted control signal 422, , and the gate input signal 426 is input to the opposite

The time of the gate 410 is delayed compared to the inverted control signal 422, that is, the inverted control signal 422 is first input to the inverse gate 410. In addition, it can be seen from the truth table of the reverse gate that only when the input is 1 , the output of the reverse gate will be 〇, and the rest will be 1. Therefore, when the inverted control signal 422 (the state changed from 0 to 1) is first input to the inverse gate 410, and then the gate input signal 426 (the state changed from 1 to 〇) is input to the inverse gate 410, The output of the gate 410 will generate a pulse signal triggered by a negative edge, and the output signal of the gate 410 will pass through the inverter 412, and then become a short pulse signal 428, as shown in FIG. Show. Next, please refer to Figure 3. When the startup circuit activates the data receiving unit, the pulse generating circuit 400 of the startup circuit generates the short pulse signal, and then inputs the short pulse signal into the transistor 314 to temporarily activate the transistor 314. As a result, the 'point A will rapidly discharge through the transistor 3 14 at the moment the transistor 3 14 is activated' to rapidly lower the voltage at point A to the desired size 1321308 (Vgs). Next, the transistor 306 is turned on, and current flows through the differential circuit 3 12 to cause the data receiving unit to start operating. Therefore, a feature of the present invention is that the data receiving unit of the preferred embodiment of the present invention uses a digital start circuit. When the start circuit activates the data receiving unit, the data receiving unit of the preferred embodiment of the present invention can quickly return to normal status. In addition, in the preferred embodiment of the present invention, since the pulse time is extremely short, the voltage at point A is not affected by the power supply voltage, and therefore, the digital starting circuit of the preferred embodiment of the present invention can improve the conventional The disadvantage of the unstable capacitive start circuit. On the other hand, since the voltage drop at point A is not affected by the power supply voltage, the same digital start circuit can be used at different power supply voltages, and the area can be greatly reduced. As apparent from the above-described preferred embodiments of the present invention, an advantage of the present invention is that the data receiving unit of the present invention can use a digital start circuit to quickly return to the normal state upon startup.

According to the preferred embodiment of the present invention, another advantage of the present invention is that the data receiving unit of the present invention can share the same set of digital starter circuits under different power supply voltages, thereby greatly reducing the area. --- «(4) W kinds of foreign workers, heat is not limited to the invention, any skilled person can do all kinds of changes and retouching without departing from the spirit of the invention, so the protection of the invention This is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent and <RTIgt; </ RTI> <RTIgt; The figure shows a schematic diagram when the conventional data receiving unit does not operate. Figure 2 is a schematic diagram showing another conventional data receiving unit. Figure 3 is a schematic diagram of a data receiving unit in accordance with a preferred embodiment of the present invention. 4 is a schematic diagram showing a pulse generating circuit not according to a preferred embodiment of the present invention. FIG. 5 is a timing diagram showing a pulse generating circuit in accordance with a preferred embodiment of the present invention. Main component symbol description] 102: control signal input terminal 106. transistor 110. transistor 202: control signal input terminal 206. transistor 210: transistor 214: capacitor 304: transistor 308: transistor 312: differential circuit 400 : pulse generation circuit 104: inverting control signal input terminal 108: transistor 112: differential circuit 204: inverting control signal input terminal 208: transistor 212: differential circuit 302: transistor 306: transistor 3 10: current Source 3 14 : transistor 402 : inverter 13 1321308 404 : inverter 406 : inverter 408 : inverter 410 : inverse gate 412 : inverter 422 : reverse control signal 424 : control signal 426 : Reverse gate input signal 428: short pulse signal

14

Claims (1)

The patent receiving range is as follows: a data receiving unit includes at least: a current mirror; and a starting circuit coupled to a common gate terminal of the current mirror, the starting circuit comprising at least: a pulse generating circuit for generating a pulse; and a first switching circuit for selectively turning on the common gate terminal of the electric lens and a first voltage according to the pulse. 2. If the data receiving unit described in item 1 of the patent application scope includes more current sources, the current mirror and the first voltage are lightly connected. 3. The data receiving unit of claim 2, wherein the current mirror comprises at least: a first transistor, a source of the first transistor coupled to the first voltage, the first One gate of the crystal is coupled to the first transistor 棰; and/or a second transistor, one source of the second transistor is coupled to the first &gt; 4. The data receiving unit according to claim 1 of the patent application, further comprising a second switching circuit, located on the common gate of the current mirror for selectively conducting the current mirror Common gate extreme. &lt; 15 1321308 5. The data receiving unit of claim 1, further comprising at least one differential circuit coupled to the current mirror. 6. The data receiving unit of claim 1, further comprising a third switching circuit coupled to the common gate terminal of the current mirror and a second voltage for selectively turning on the current mirror The common gate is extreme with the second voltage. 7. The data receiving unit of claim 6, wherein when the third switching circuit is turned on, the common gate of the current mirror is disconnected. κ 8. The data receiving unit according to claim 6, wherein when the third switching circuit is turned off, the common gate of the current mirror is turned on. 9. The data receiving unit of claim 6, wherein the second voltage is greater than the first voltage. — a first inverter, the first inversion. The first signal has an input terminal for inputting a second inverter, and the second inverter is coupled to the C ^ ^ input terminal An output of one of the first inverters; and a reverse gate, one of the opposite gates - a person #*, the music input k is coupled to an output of the second inverter, the gate a second round of her persuasion input for inputting a second signal 16 1321308, wherein the first signal is opposite to the second signal; wherein 'when the first signal and the second signal are input, the The anti-gate will first receive the second signal and then receive the first signal to generate the pulse. 11_ A start-up circuit, suitable for use in a data receiving unit, the data receiving early 7G includes at least one current source, a current mirror and a first transistor, and one input end of the current mirror is coupled to one input end of the current source One of the current mirrors is coupled to a first voltage, and one source of the first transistor is coupled to the second voltage, and one of the first transistors is coupled to a common gate of the current mirror. The startup circuit is coupled to the common gate terminal of the current mirror, the startup circuit includes at least: a pulse generating circuit for generating a pulse; and a second transistor, wherein a gate of the second transistor is coupled to the a pulse generating circuit, a drain of the second transistor is coupled to the common gate terminal of the current mirror, and a source of the second transistor is coupled to the second voltage; wherein the pulse generating circuit generates the pulse And turning on the second transistor 'to lower the common gate voltage of the current mirror, and starting the current mirror. 12. The start-up circuit of claim U, wherein the second transistor is an n-type transistor. 13. The start-up circuit of claim 5, wherein the first transistor is a p-type transistor. 17 1321308. The starter circuit of claim 11, wherein the first voltage is greater than the second voltage. 15. The starter circuit of claim 11, wherein the pulse generating circuit comprises: at least: a first inverter having an input for inputting a first signal; a second inverter, an input end of the second inverter is coupled to an output end of the first inverter; and a reverse gate is connected to the second input An output terminal of the phase switch, the second input end of the reverse gate is configured to input a second signal 'where the first signal is opposite to the phase of the second signal; wherein, when the first signal is input and the In the second signal, the reverse gate first receives the second signal and then receives the first signal to generate the pulse. 16. A source driver comprising at least a data receiving unit as described in claim i. The 17' type display system' includes at least the source driver as described in claim 16 of the patent application. The control method of the data receiving material is applicable to the source driving 1 δ. The control method at least includes: according to a first control signal, for closing the data receiving unit; 18 1321308 according to the first control signal and the first The second control signal generates a pulse signal, wherein the first control signal is opposite to the phase of the second control signal; and the data receiving unit is activated according to the pulse signal. 19