TWI316787B - Method for optimizing critical path timing in a logic synthesis flow and data processing system - Google Patents
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1316787 * 九、發明說明: 【發明所屬之技術領域】 本發明關於電子電路設計之邏輯電路合成(logic synthesis),尤其是—種用於邏輯電路合成流程中最佳化 關鍵路徑時序之系統與方法。 【先前技術】1316787 * IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to logic synthesis of electronic circuit design, and more particularly to a system and method for optimizing critical path timing in a logic circuit synthesis process . [Prior Art]
邏輯電路合成係由基本邏輯電路功能方塊設計出一複 雜的邏輯電路功能,此基本邏輯電路功能方塊係衍生自基 本邏輯電路功能的目標函式庫。合成流程通常開始於以高 階描述語言定義欲達成之複雜功能。合成流程並建立一個 基本邏輯電路方塊的互連集合來達成上述被定義的複雜邏 輯電路功能’每個基本邏輯電路方塊或單元(eell)係包含 一個或多個電路元件之群組,這些it件可歧電晶體、電 谷與其他肖以執行—簡單基本功能之基本電路元件群組。 乂樣的邏輯電路單元至少包含兩類:組合單元 —toriai cells)與序向單元(琴⑼咖⑽小 組合單7L執行最基本之布林邏輯功能,The logic circuit synthesis is designed by the basic logic circuit function block to design a complex logic circuit function, which is derived from the target function library of the basic logic circuit function. The compositing process usually begins with defining the complex functions to be achieved in a high-order description language. Synthesizing the process and establishing an interconnected set of basic logic circuit blocks to achieve the above-described defined complex logic circuit functions. 'Each basic logic circuit block or unit (eell) contains a group of one or more circuit elements, these are pieces Discrete transistors, electric valleys, and other groups of basic circuit components that perform simple-simple basic functions. There are at least two types of logic circuit units: the combination unit—toriai cells) and the sequence unit (the piano (9) coffee (10) small combination single 7L performs the most basic Boolean logic function.
如 NAND、M0R ,邏輯反轉,其#由組合(_bining)電子訊號輸入成為簡 單邏輯輸出’來實現這些簡單的功能。 所有可實現的電子電路需要—有限時間以傳遞一邏輯 電路功能’此時間被稱為傳遞延遲。由於需由基本電晶體 5 1316787 * 元件組合成不同的組態’不同的邏輯電路功能通常有不同 的傳遞延遲。當組合方塊所合成之邏輯電路功能越複雜, 則形成之邏輯電路路徑數量越可觀,這些路徑係電子訊號 自組合單元的互連集合之輸入傳遞至輸出所通行的路線。 實現愈複雜之邏輯電路功能則協調邏輯路徑之傳遞時序愈 趨困難。如果邏輯電路的時序未良好協調,邏輯電路功能 可能會顯現不能重製(transient)之失常行為或完全失效。 序向單元係為特殊邏輯電路,其配合所謂時脈之同步 訊號以調節邏輯電路路徑之時序。遍及於整個設計之同步 事件(synchronization events)發生時,這些單元停止或 許可邏輯訊號通過一複雜邏輯電路功能,如同交通訊號協 調交通流量。序向單元以將資料儲存於一記憶體功能之方 式來停止邏輯資料,直到時脈通過時序(clock passing time)發生為止。一序向單元時脈傳遞所儲存之邏輯資料所 需時間稱為時脈傳遞延遲(cl〇ck pr〇pagati〇]1 delay)。於 一邏輯停止時脈事件(logic—haiting ci〇ck event)完善儲 存資料前’必須呈現此資料之所需時間稱為設定時間 (setup tlme) °序向單元之範例如正反器(flip-flops)與 閂(latches)。 以一正反器或閂之資料通過時脈事件開始,且以一正 反器或問之資料停止時脈事件結束之邏輯電路路徑被稱為 1316787 一時序路徑。依此推論,具有兩個序向單元的時序路徑, 需由組合單元連結上述兩個序向單元。一時序路徑包含第 一序向單元的時脈傳遞延遲、組合單元的傳遞延遲與第二 序向單元所需的設定時間。一邏輯電路設計中最長的時序 路徑通常限制了整體設計的效能,因此被稱為關鍵時序路 徑。 在合成過程中為改進一邏輯電路設計,最佳化此關鍵 • 時序路徑極為重要。圖1係一合成設計流程中一個具有兩 個標準正反器之關鍵時序路徑之示意圖。此路徑邏輯電路 包含能執行任一邏輯電路功能之專門組合單元邏輯電路, 如圖1所示,關鍵時序路徑由正反器1與11之時脈至 Q(Clock-to-Q)的傳遞延遲(tc〇i)、路徑邏輯電路13之傳遞 延遲(tpathiogic)、與正反器2與12之D至時脈(D-to-Clock) 之設定時間tl)C2所構成。 ® —標準正反器包含兩個相似的閂,一主要閂決定D至 時脈的設定時間,而另一從屬閂提供時脈至Q的傳遞延 遲。若最佳化D至時脈之設定時間,則會對時脈至Q之傳 遞延遲不利,反之亦然。因此,對一標準正反器而言,必 需在主要閂與從屬閂間做一個妥協。 除了正反器之外,常見之設計技術可利用兩個個別的 閂來實現時序功能,並在這兩個閂間提供路徑邏輯電路, 7 1316787 但是這些技術需要更複雜的時序分析,並且更難以由一邏 輯合成工具自動完成。 因此需要一種方法或系統在一邏輯電路合程流程中最 佳化關鍵路徑時序,使其能以邏輯電路合成的現有技術來 施行。 【發明内容】 鑒於上述之發明背景,為了符合產業上利益之需求, • 本發明之一實施例提供一種在邏輯電路合成流程中最佳化 關鍵路徑時序之方法與系統,可用以解決上述傳統技術未 能達成之標的。在一具體實施例中,揭示了邏輯電路合成 流程中最佳化關鍵路徑時序之一系統,該系統包含一個傳 遞延遲最佳化之第一時脈邏輯電路單元、一個設定時間最 佳化之第二時脈邏輯電路單元與一路徑邏輯電路。第一時 脈邏輯電路單元之輸出係耦接於路徑邏輯電路,並且被傳 • 送至路徑邏輯電路作處理。第二時脈邏輯電路單元具有與 第一時脈邏輯電路單元相同之邏輯電路功能,其輸入耦接 於路徑邏輯電路之輸出。路徑邏輯電路之輸出則傳送至第 二時脈邏輯電路單元作處理。關鍵路徑時序由第一時脈邏 輯電路單元之傳遞延遲、路徑邏輯電路之傳遞延遲與第二 時脈邏輯電路單元之設定時間所決定。在邏輯電路合成流 程中,設計速度與耗電量可藉由較佳的關鍵路徑之時脈最 8 1316787 佳化得到改善。 本發明之另一實施例提供邏輯電路合成流程中最佳化 關鍵路徑時序之一系統,該系統具有一路徑邏輯電路與一 傳遞延遲最佳化之時脈邏輯電路單元。時脈邏輯電路單元 的輸出係耦接於路徑邏輯電路的輸入且被傳送至路徑邏輯 電路作處理。 本發明之又一實施例提供一邏輯合成流程中最佳化關 • 鍵路徑時脈之系統。此系統包含一路徑邏輯電路與一設定 時間最佳化之時脈邏輯電路單元。該時脈邏輯電路單元乃 耦接於路徑邏輯電路以接收與處理路徑邏輯電路之輸出。 本發明在一實施例提供一邏輯合成流程中最佳化關鍵 路徑時脈之方法。此方法包含設計一個具一最佳化傳遞延 遲之第一時脈邏輯電路單元,與一個具一最佳化設定時間 之第二時脈邏輯電路單元。此方法之步驟包括將第一時脈 ® 邏輯電路單元耦接於路徑邏輯單元,將第一時脈邏輯電路 單元之輸出傳送至路徑邏輯單元作處理。此方法更包括將 第二時脈邏輯電路單元耦接於路徑邏輯電路以接收與處理 路徑邏輯電路之輸出,該第二時脈邏輯電路單元與第一時 脈邏輯電路單元之邏輯功能相同。 【實施方式】 本發明在此所探討的方向為一種邏輯電路合成流程中 9 1316787 最佳化_路徑時序之_與方法。為了能徹底地瞭解本 發明’將在下列的描述中提屮 出詳盡的步驟及其組成。顯然 地,本發明的施行並未限定於邏輯電路合成流程中最佳化 關鍵路料序之系統與方法之技藝者所熟習的特殊細節。 另〆方面1所周知㈣成或步驟並未描述於細節中,以 避兔造成本發科必要之限制^本發日㈣較佳實施例會詳 ,細揭述如下1而除了這些詳細描述之外,本發明還可以Such as NAND, M0R, logic inversion, its # by _bining electronic signal input into a simple logic output 'to achieve these simple functions. All achievable electronic circuits require finite time to pass a logic circuit function. This time is called the transfer delay. Due to the need to be combined by the basic transistor 5 1316787 * components into different configurations 'different logic circuit functions usually have different transfer delays. The more complex the logic circuit functions synthesized by the combination block, the more substantial the number of logic circuit paths formed, which are the input of the electronic signal from the input set of the combination unit to the output path. The more complex logic circuits are implemented, the more difficult it is to coordinate the timing of the transfer of logic paths. If the timing of the logic circuit is not well coordinated, the logic circuit function may exhibit an abnormal behavior that cannot be reproduced or a complete failure. The sequence unit is a special logic circuit that cooperates with a so-called clock synchronization signal to adjust the timing of the logic circuit path. These units stop or permit logic signals to pass through a complex logic function, such as traffic signals to coordinate traffic flow, as the entire design synchronization event occurs. The sequence unit stops the logic data by storing the data in a memory function until the clock passing time occurs. The time required to pass the stored logical data to the unit clock is called the clock transmission delay (cl〇ck pr〇pagati〇]1 delay). Before the logic-haiting ci〇ck event perfects the storage of data, the time required to present this data is called the set time (setup tlme). The order of the sequence unit, such as the flip-flop (flip- Flops) and latches. A logic circuit path that begins with a clock event with a flip-flop or latch data and stops the clock event with a flip-flop or a data message is called a 1316787-timing path. It follows from this that a timing path with two sequential units needs to be connected by the combining unit to the two sequential units. A timing path includes the clock transfer delay of the first sequence unit, the transfer delay of the combining unit, and the set time required by the second sequence unit. The longest timing path in a logic circuit design often limits the overall design performance and is therefore referred to as a critical timing path. Optimizing this logic to improve a logic circuit design during synthesis • Timing paths are extremely important. Figure 1 is a schematic diagram of a critical timing path with two standard flip-flops in a synthetic design flow. This path logic circuit contains a special combination of unit logic circuits capable of performing any of the logic circuit functions. As shown in FIG. 1, the critical timing path is delayed by the clock of the flip-flops 1 and 11 to Q (Clock-to-Q). (tc〇i), the transfer delay of the path logic circuit 13 (tpathiogic), and the set time t1) C2 of the D to the clock of the flip-flops 2 and 12 (D-to-Clock). ® —The standard flip-flop contains two similar latches, one primary latch determines the settling time from D to the clock, and the other slave latch provides the clock-to-Q transfer delay. If the D to the set time of the clock is optimized, the delay to the clock to Q will be adverse, and vice versa. Therefore, for a standard flip-flop, a compromise must be made between the primary and secondary latches. In addition to the flip-flops, common design techniques can utilize two separate latches to implement timing functions and provide path logic between the two latches, 7 1316787 but these techniques require more complex timing analysis and are more difficult It is done automatically by a logic synthesis tool. There is therefore a need for a method or system to optimize critical path timing in a logic circuit assembly process that can be implemented in the prior art of logic circuit synthesis. SUMMARY OF THE INVENTION In view of the above described background, in order to meet the needs of industrial interests, an embodiment of the present invention provides a method and system for optimizing critical path timing in a logic circuit synthesis process, which can be used to solve the above conventional techniques. Failure to achieve the target. In one embodiment, a system for optimizing critical path timing in a logic circuit synthesis flow is disclosed, the system including a first clock logic circuit unit for optimizing the transfer delay, and a set time optimization A two-way logic circuit unit and a path logic circuit. The output of the first clock logic circuit unit is coupled to the path logic circuit and transmitted to the path logic circuit for processing. The second clock logic circuit unit has the same logic circuit function as the first clock logic circuit unit, the input of which is coupled to the output of the path logic circuit. The output of the path logic circuit is passed to the second clock logic circuit unit for processing. The critical path timing is determined by the transfer delay of the first clock logic circuit unit, the transfer delay of the path logic circuit, and the set time of the second clock logic circuit unit. In the logic synthesis process, the design speed and power consumption can be improved by the better critical path of the clock. Another embodiment of the present invention provides a system for optimizing critical path timing in a logic circuit synthesis flow, the system having a path logic circuit and a transfer delay optimized clock logic circuit unit. The output of the clock logic circuit unit is coupled to the input of the path logic circuit and passed to the path logic circuit for processing. Yet another embodiment of the present invention provides a system for optimizing the key path clock in a logic synthesis process. The system includes a path logic circuit and a set time optimized clock circuit unit. The clock logic circuit unit is coupled to the path logic circuit for receiving and processing the output of the path logic circuit. In one embodiment, the present invention provides a method of optimizing a critical path clock in a logic synthesis process. The method includes designing a first clock logic circuit unit having an optimized transfer delay and a second clock logic circuit unit having an optimized settling time. The method includes the steps of coupling the first clock logic circuit unit to the path logic unit and transmitting the output of the first clock logic circuit unit to the path logic unit for processing. The method further includes coupling the second clock logic circuit unit to the path logic circuit to receive and output the processing circuit logic circuit, the second clock logic circuit unit having the same logic function as the first clock logic circuit unit. [Embodiment] The direction of the present invention discussed herein is a method and method for optimizing the _path timing in a logic circuit synthesis flow. In order to fully understand the present invention, detailed steps and compositions thereof will be presented in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the art of methods and methods for optimizing the routing of logic circuits. The other aspects are well-known (four) into steps or steps are not described in the details, in order to avoid the necessary restrictions on the hair of the rabbit. The present invention (four) preferred embodiment will be detailed, as detailed below 1 and except for these detailed descriptions The invention can also
廣泛地施行在其他的實施例t,且本發明的範圍不受限 定,以所列的專利範圍為準。 由圖1可知正反器η、12與路徑邏輯單元13建構出 舍成之最關鍵時序電路,以組織系統之信號時序與流程。 用於建構一正反器的主要元件為一個閂。圖2(a)中為一典 麥問20的代表符號;參照圖(2b),舉例一以電晶體施行之 典逛閂20的示意圖。閂20包含一緩衝反向器21、一傳送 閘22與一訊號擷取機制23。當當受到互補時脈訊號彡與g致 能’傳运閘22連結缓衝反向n 21之輸出至訊號擷取機制 23。該結構能讓輪人訊號D驅動緩衝反向器21斑傳送閘 22,控制訊號擷取機制 '、 嚆",妳傳诚 的狀L、且在Q之輪出端顯現。輪 八·虎請、4麵成為-輸 #傳遞時間W閃的… 以蛉間為如圖3所 ,- 1的另一個特性延遲為tCQ,該延遲係當 罐™而開啟傳時,穩定輸入訊二;; 1316787 輸出Q所需之時間。為實現一快速電路,傳遞延遲tDQ與tcQ 需減低至其最小值。 另外一個主要時序關係乃設定時間tDC,發生在互補時 脈訊號關閉傳送閘22與隔絕訊號擷取機制23之前,如圖 3所示。為使訊號擷取機制23可反映訊號D之正確狀態, 訊號D必須在訊號擷取機制23被傳送閘22隔絕一段特定 時間之前達到一穩定邏輯狀態。對一快速電路而言,最小 鲁化設定時間tDC亦為所需。 由於緩衝反向器21、傳送閘22與訊號擷取機制23係 交互連結,一閂的時序參數tDC、tDQ與1^並非各自獨立。 例如,增加傳送閘22的驅動強度會降低傳遞時間tCQ,但 額外的寄生負載導致設定時間增加。由此設計相關之結 構與裝置熟知相關技藝者可輕易推知參數tcQ與tDC之反向 關係。 ® 參照圖4,其中例舉了一典型反向器單元,其包含兩 串聯之閂41、42與一時脈網路43(clock network)。時脈 網路43在時脈反相時讓資料通過閂41、42間來調節資料 流。圖5示意從正反器的外部埠(ports)來看時脈CLK、資 料輸入D與正反器輸出Q的時序關係。如果通過時脈網路 的傳遞延遲為可忽略,可得知正反器tDC的設定時間為正反 器電路中閂1(41)的設定時間。同樣地,如果時脈網路的 11 1316787 延遲可以被忽略的話,正 僂谈 正反态的傳遞延遲tcQ為閂2(42)的 tDC。 丄 9有限延遲加長tcQ的延遲,並且降低 ‘函式庫-般包含標準正反器邏輯電路功能,其時 、“ Μ遞延遲^與D至時脈設定時間之間妥協, 〜兩個參數間具有反比的關係。如第-圖所示, 、一具有兩個標準正反器之合成設計流程中,時脈至Q傳 遞L遲tci、D至時脈設定時間^的妥協會導致一非最佳 之關鍵時序路&,這是因為每—個正反器與該關鍵路徑 時序:f限於非關鍵的路徑時序。圖6示意了本發明之一 口 U讀’其關鍵路徑時序具有—個傳遞延遲最佳化 之傳遞正,S 61與-個設定時間最佳化之接收正反器 62正^器61、62具有相同的邏輯電路功㉟,卻是以不同 ㈣序取佳化來設計。傳遞正反器61對較小傳遞延遲tcQi 作最佳化而接收正反器62對較小設定時間tDC2作最佳 化。本發明提φ具有兩個獨立且最佳化序向單元之一目標 函式庫以供合成流程使用。傳遞正反器61與一路徑邏輯電 路63間的傳遞路徑為P1,而路徑邏輯電路⑽與接收正反 器62間的傳遞路徑為p2。 參照圖7,其示意了在圖6之關鍵路徑時序的時序關 係。給定一時脈週期時間teyeie,傳遞延遲t⑽最佳化之傳 12 1316787It is widely practiced in other embodiments, and the scope of the invention is not limited, and the scope of the listed patents will control. It can be seen from Fig. 1 that the flip-flops η, 12 and the path logic unit 13 construct the most critical sequential circuits to organize the signal timing and flow of the system. The main component used to construct a flip-flop is a latch. In Fig. 2(a), a representative symbol of a code 20 is used; and with reference to Fig. 2b, a schematic diagram of a tag 20 for performing a transistor is exemplified. The latch 20 includes a buffer inverter 21, a transfer gate 22 and a signal extraction mechanism 23. When the complementary clock signal 彡 and g enable the transmission gate 22, the output of the buffer reverse n 21 is output to the signal acquisition mechanism 23. The structure enables the wheelman signal D to drive the buffer reverser 21 spot transmission gate 22, and controls the signal acquisition mechanism ', 嚆", 妳传诚's shape L, and appears at the end of the Q wheel. Round eight · Tiger please, 4 sides become - lose # pass time W flash ... With the day as shown in Figure 3, -1 another characteristic delay is tCQ, the delay is when the tank TM is turned on, stable input News 2;; 1316787 Time required to output Q. To achieve a fast circuit, the transfer delays tDQ and tcQ need to be reduced to their minimum values. Another primary timing relationship is the set time tDC, which occurs before the complementary clock signal turns off the transmit gate 22 and the isolated signal capture mechanism 23, as shown in FIG. In order for the signal acquisition mechanism 23 to reflect the correct state of the signal D, the signal D must reach a stable logic state before the signal acquisition mechanism 23 is blocked by the transmission gate 22 for a certain period of time. For a fast circuit, the minimum lubricated set time tDC is also required. Since the buffer reverser 21, the transfer gate 22 and the signal capture mechanism 23 are interconnected, the timing parameters tDC, tDQ and 1^ of a latch are not independent of each other. For example, increasing the drive strength of the transfer gate 22 reduces the transfer time tCQ, but the additional parasitic load causes the set time to increase. Thus, those skilled in the art will be able to easily infer the inverse relationship between the parameters tcQ and tDC. Referring to Figure 4, a typical inverter unit is illustrated which includes two series of latches 41, 42 and a clock network 43. The clock network 43 allows data to pass through the latches 41, 42 to adjust the data stream when the clock is inverted. Figure 5 illustrates the timing relationship of the clock CLK, the data input D, and the flip-flop output Q from the external ports of the flip-flop. If the transmission delay through the clock network is negligible, it can be known that the set time of the flip-flop tDC is the set time of the latch 1 (41) in the flip-flop circuit. Similarly, if the 11 1316787 delay of the clock network can be ignored, the forward-transfer delay tcQ is the tDC of the latch 2 (42).丄9 finite delay lengthens the delay of tcQ, and reduces the 'function library' to include the function of the standard flip-flop logic circuit. At the same time, "the delay between the delay delay ^ and the D to the clock setting time, ~ between the two parameters It has an inverse relationship. As shown in the figure--, in a synthetic design flow with two standard flip-flops, the clock-to-Q transfer L is delayed by tci, and D is set to the time of the clock. The key timing circuit & this is because each flip-flop and the critical path timing: f is limited to non-critical path timing. Figure 6 illustrates one of the aspects of the present invention U read 'its critical path timing has a pass The transmission of the delay optimization is positive, and the S 61 and the set-up time-optimized receiving flip-flops 62 have the same logic circuit function 35, but are designed with different (four) ordering. The pass flip-flop 61 optimizes the small transfer delay tcQi and the receive flip-flop 62 optimizes the smaller set time tDC2. The present invention provides for two independent and optimized ordering units. The library is used for the synthesis process. Passing the flip-flop 61 and all the way The transfer path between the path logic circuits 63 is P1, and the transfer path between the path logic circuit (10) and the receive flip-flop 62 is p2. Referring to Fig. 7, the timing relationship of the critical path timings in Fig. 6 is illustrated. Pulse cycle time teyeie, pass-through delay t(10) optimization pass 12 1316787
遞正反器61反映在傳遞路徑ρι上,而設定時間七 化之接收正反器62反映在傳遞路徑p2上。#由最佳化— 正反器(如傳遞正反器61)的傳遞延遲仏與最佳化另一正 反器(如接收正反H 62)的設定時^,肢㈣/遞送延 遲之折衷問題可獨立於—般組合路徑邏輯電路的傳遞延遲 tPathlogic而獲得解決。由於傳遞正反器之七即與接收正反器 之tDC2係個別最佳化來降低關鍵路徑時序,這種創新的人 成方法相較於運用折衷設定/傳遞延遲正反器的合成二 法,可以達到一較快的設計。 最佳化正反器的設定與傳遞延遲可以兩個習知的方法 來達成,包含在正反器層加入/移除時脈網路延遲與控制閂 元件的大小。有關最佳化正反器之設定與傳遞延遲的細部 时論可參照 Skew Tolerant Circuit Design —書(SkewThe flip-flop 61 is reflected on the transfer path ρι, and the receive flip-flop 62 of the set time is reflected on the transfer path p2. #化化—— The transfer delay of the flip-flop (such as the transfer flip-flop 61) and the optimization of another flip-flop (such as receiving the positive and negative H 62) ^, limb (four) / delivery delay The problem can be solved independently of the transfer delay tPathlogic of the general combination path logic circuit. Since the transfer of the flip-flop 7 and the tDC2 of the receive flip-flop are individually optimized to reduce the critical path timing, this innovative method of man-made is compared to the synthetic two method of using the trade-off/transfer delay flip-flop. A faster design can be achieved. Optimizing the flip-flop settings and transfer delays can be accomplished in two conventional ways, including adding/removing the clock network delay and controlling the size of the latch elements in the flip-flop layer. For details on the settings and transfer delays for optimizing the flip-flops, see Skew Tolerant Circuit Design - Book (Skew)
Tolerant Circuit Design by David Harris, Morgan Kaufmann Publishers, 2001,pp. 52-54)。若以第一種方 法調整時脈網路來最佳化傳遞延遲,請再一次參照圖4, 可知時脈至Q傳遞延遲時序開始於CLK埠,遞送過圖示中 兩個時脈網路43的反向器,並且啟動閂2 (42)至一穿透 (transparent)狀態,使其可遞送資料輸出至Q埠。從CLK 埠至閃2 (42)的最短路控為一個單一時脈網路反向器茂叉 至3埠,此最短路徑決定閃2(42)與正反器整體開始遞送儲 13 1316787 存於閂2(42)的資料之曰且 沾吐, 枓之取早時間。圖8示意-個相同功能 的夸脈網路,該網路直 .7 直接連結CLK埠至閂2(82)的$埠,建 立—個能從閂2(82)值、关次』丨建 使㈣… 資料的較快路徑。此較快路徑致 ,, 之正反益具有較短之傳遞延遲。因Tolerant Circuit Design by David Harris, Morgan Kaufmann Publishers, 2001, pp. 52-54). If the first method is used to adjust the clock network to optimize the transfer delay, please refer to FIG. 4 again. It can be seen that the clock-to-Q transfer delay timing starts at CLK埠, and the two clock networks 43 in the figure are delivered. The inverter is activated and the latch 2 (42) is activated to a transparent state such that it can deliver the data to Q埠. The shortest path from CLK 埠 to 闪 2 (42) is a single clock network reverser to 3 埠, this shortest path determines flash 2 (42) and the flip flops start to deliver the whole 13 1316787 The data of the latch 2 (42) is sputum and sputum, and the sputum takes the early time. Figure 8 shows a similar function of the bogey network, the network directly. 7 directly link CLK埠 to the latch 2 (82) $埠, establish a can be from the latch 2 (82) value, close the state Make (four)... a faster path to the data. This faster path leads to a shorter delivery delay. because
此’圖8的正反器比圄1 τ U τ 之正反器更為最佳化,且圖8的 正反器是圖6中關+ 的 擇。 徑時序之起始正反器61更好的選 回顧設定時間,表昭 m铲I)^ 〜、、、圖2(b)1埠與3埠控制允許資料 巩唬D通過反向器21盥 ^ 9q . 0a 〇 ^傳迗閘22,並影響資料擷取機制 23。在閂20的擷取階庐调1則 .. 奴,傳送閘22關閉並且阻止資料埠 D與訊號擷取機制23問 7寸埤 間進一步的資料流。設定時間乃資料 D與〆#間轉變的延遲,使欠 _ 更传貝料D上一個可能的轉變能夠 在分與?的轉換關閉傳送 2之則,正確地遞送並儲存於却 號擷取機制23。圖3絡干+ 、訊 口 α、、,日不—tDc的量測波型圖。 圖8的正反裔比圖4的正反器較快關閉閃1(81),係 因圖8的正反器使用—個具有較少緩衝反向器階段的時脈 網路83。假設兩個正反器的問1(⑴設計為相同,就圖8 ^正反器而言,資料D 1會較早到達,因為圖8之正反 器的4與》訊號較早到達 丁 j運亦即,圖8的正反器顯示一個輪 大的設定時間。因此,袜气〜+ χ 心Λ 定時間而言,®4的正反器相 a 、态更為最佳化,並且對圖6的關鍵路徑時 1316787 序整體而言,圖4的正反器會是正反器62的較佳選擇。 由此可知傳遞延遲或設定時間任一者之最佳化可由調 整一給定之正反器其時脈網路之延遲來達成。第二種縮簡 閂元件規模來最佳化設定時間與傳遞延遲的方法為熟悉相 關技術者所熟知,相關細節可參考Logical Effort (Logical Effort by I. Sutherland, et al, Morgan Kaufmann Publishers, 1999,pp. 45-61)。某些程度的傳 鲁 遞延遲或設定時間最佳化可以透過電晶體縮簡規模與緩衝 區配置來施行於正反器元件自身的閂中。 一數位電路中的電晶體可以想像成一個電子開關,如 圖9所示。一閂元件,如圖9(a)所示的CMOS反向器90 (亦 可參照圖2(b)的21)具有一 N通道裝置92與一 P通道裝置 93,如圖9(b)所示,其寬/長比分別為Wn/Ln與Wp/Lp。該電 路可以被模組化成為兩個開關94、95的網路如圖9(c)所 ® 示。開關之傳導電阻Rnl係與N通道裝置92的寬/長比成反 比,同樣地,開關之傳導電阻RPl的係與P通道裝置93的 寬/長比成反比。電阻Rnl與RPl限制了 一給定之供應電壓下 能強行通過電晶體開關9 4、9 5的電流。 所有實體結構本身具有一個容量來儲存某些量的電 荷,這個性質被稱為電容。在最佳化設定與傳遞延遲的應 用上,其為限制一電晶體啟閉速度的一種寄生現象。這是 15 1316787 因為一電性接點的電壓改變率與該接點的電流充電成正 比’並與該接點的電容特性成反比。例如,圖9(c)的qjos 反向器90中存在兩電容Cil與Cpl。電容Cii影響輸入接點A, 並且與電晶體的閘區域WpLp + WnLn成正比。電容Q係一輸 出電谷,其與源極與汲極的結構有關,與電晶體wp + wn 的寬度總和成正比。 圖10(a-c)係一基本閂(請參照圖2(b)示出的元件22) ®的一傳送閘100之一相似模組分析。參照圖1〇(c)的詳細 模組,開關電阻R„2與RP2係分別與Wn/Ln& ^/^成反比。 不同於反向器90在一給定狀態中只啟動n通道92與p通 道93兩者之一,傳送閘開關104、1〇5係同時開啟或同時 關閉。訊號#必需驅動一輸入電容CiZn,其與n通道電晶體 W„Ln的區域成正比。同樣地,訊號》必需驅動一輸入電容 C%,其與P通道電晶體WpLp的區域成正比。電容U2a與匕^ 係大小相似,並且與^ + WP電晶體寬度的總和成正比。 為了降低一電晶體電路之延遲,必須最小化開關電阻 與由開關電阻所充電之負載電容,開關電阻與負載電容的 乘積與傳遞延遲成直接正比。在先前技術中,如果對一裝 置維持一常數的長度(maintain a constant length),可 增加該裝置之寬度以降低電晶體的開關電阻,進而降低驅 動一給定負載電容之開關的傳遞延遲。當裝置加入網路中 16 1316787 時便需要最佳化,這是由於增加一電晶體之寬度便會對驅 動該電晶體的前一狀態呈現出一個較大的負載電容。 如果以基本電晶體模組理論套用於圖2的閂20,便可 列出閂2 0之設定與傳遞延遲最佳化的可能性與限制,如圖 11所示,為說明之便,簡單分析描述該開關於D埠之單一 個低至高的轉換。 在單元設計(ce 11 design)中的一個共通規格為限制 • 輸入與負載的最大電容量。參照圖11(a),這些電容分別 為Cin與Cl。設定閂輸入電容可建立輸入反向器111的輸入 電容,由此限制了最大寬度,也限制了最小開關電阻Rin 與寄生電容CPin。圖11(b)中訊號擷取機制回饋反向器114 只需要對程序溢漏(process 1 eakage)補償,並且增加閂對 雜訊的排阻,因此大寬度的電晶體便非必需。此外,大寬 度電晶體也會增加Cfin,因而增加輸出驅動器113除了 ClI 16 • 外所需開關之負載電容。基於這些理由,擷取機制回饋反 向器114通常縮減至製程所容許之最小電晶體寬度。 由上述之限制,大致僅存傳輸閘112與輸出驅動器113 可作為最佳化之基本元件,雖然精確的最佳化需要複雜的 模組化與電腦模擬,仍可針對一最佳化傳遞延遲或設定時 間之裝置獲得某些基本概念。 例如,在圖11(b)中,可藉由增加包含輸出驅動器113 17 1316787 在内之電晶體的寬度來降低閂的傳遞延遲,直到寄生電容 CPd達到電容Cfin與Cl所呈現的有效負载電容量。增加電晶 體寬度會降低驅動電阻Rd與最小化輸出驅動器113的傳遞 延遲。進-步增加電晶體寬度在實質上並不會降低延遲, 因為驅動電阻的降低是由比例增加電晶體本身寄生電容Cpd 來達成。 最小化通過傳送閘U2之傳遞延遲較複雜些,因為僅 將負載電容Cl 116連結至輸入反向器lu時,傳送閘112 並不產生訊號增益。輸入反向器nl實際上提供充電電流 至包括CPin、CPtgl、Cptg2、Cdin與Cpf在内的寄生電容,由於 cin為固定,因而輸入反向器lu驅動電阻固定為Rin,而輸 入反向器111寄生負載固定為Cpin。由於回饋反向器 為一個最小裝置,訊號擷取回饋反向器寄生電容(^為固 定,並且經前段所敘之傳遞最佳化後,Cdin為固定。增加傳 送閘112中電晶體之寬度將會降低Rin + Rtg的整體開關電 阻,但也增加寄生電容(^⑷與cPtg2。不過在傳送閘112之 裝置寬度增加之時,傳送閘112的傳遞延遲將會減少,直 到整體寄生電容CPtsl + CPtg2達到與cdin、cPf與cPin所呈現整 體電容相同之量。 組合傳送閘112與輸出驅動器113之最小傳遞延遲的 最佳化,可產生一最小傳遞延遲最佳化的閂。最小化的時 18 1316787 * 序路徑係由0/7埠通過傳送閘112、輸出驅動器113至在Q 埠所見之負載電容Cl Π6。 閂設定時間的最佳化一般而言不同於傳遞延遲的最佳 化,因為需要強調不同的時序路徑。例如,在圖Π的閘中, 訊號擷取機制Π5須儘可能快速地切換。為達到此,必須 最小化從接點12到Q再回到12之迴圈延遲,這意味需限 制可容忍之負載電容ClI 16。降低從接點12到Q再回到12 • 之迴圈延遲需要降低輸出驅動器113之輸入電容Cdin,這意 味驅動器113之寬度需降低至一最小值,設定時間可降低 但需付出代價在閃傳遞延遲之上。表現在傳送閘112的電 容負載亦需要最小化,而傳送閘寬度降低至寄生電容CPtgl 與(:响2相近於被降低之CdinK呈現之負載。 組合傳送閘112與輸出驅動器113之最小設定最佳化 可得一最小設定最佳化之閂。此最佳化之路徑係從D埠通 鲁 過輸入反向器111、傳送閘112、輸出驅動器113,最後通 過訊號擷取回饋反向器114再回到12埠。來自D埠的輸入 訊號必需遞送通過該路徑,並且完成訊號擷取功能,這必 需在藉由訊號^與^將傳送閘112停止運作以隔絕訊號擷取 機制115之前來完成。 對圖11(a)之閂作基本結構修改亦可用於設定時間之 最佳化。其中一個最小化設定時間的裝置涉及縮小輸出驅 19 1316787 動器113與最小化負載電容Cl 116。限制一個閂之Cl 125 影響的之常見裝置係利用負載電容Cl 125缓衝接點14,如 圖12(a)所示。緩衝接點13可降低從12經13再回到12 之整個迴圈的延遲,但注意傳遞延遲已被通過缓衝器124 的延遲所增加。 降低設定時間的一額外裝置包含移除輸入反向缓衝器 120與依賴前一階段的輸出來驅動閂資料輸入D,如圖12(b) • 所示。圖12(a)之相同的緩衝概念可用於協調D至Q的邏 輯極性。由於資料傳遞延遲路徑已經被一反向器傳遞延遲 所降低,並且設定路徑牽涉資料與時脈路徑的相對時序, 設定時間大致上已被圖12(a)之一反向器傳遞延遲所降 低。解除輸入資料反向器其一可能的缺點為在考量閂輸入 阻抗與前一階段的驅動能力之下,此方法需要額外的合成 限制與特性。 ® 本發明的本質為從一目標函式庫合成一設計,該目標 函式庫具有兩個相同的功能但不同的最佳化時序之序向單 元。序向單元涉及一大型單元家族,其擁有儲存資料狀態 之能力。遍及這家族的為一群閂與正反器,只要其能夠以 不同之設定或傳遞延遲最佳化來建立序向單元,這些裝置 中的每一個都可以用以施行於本發明。最佳化CMOS閂與一 D型正反器之方法已經詳盡地探討過了,然而這些方法可 20 1316787 同樣地應用在其他型式的正反器上。 雖然本發明運用一 D型正反器,藉由增加外部閘以將 一形式之正反器轉換至另一形式為常見可行的作法,更多 有關正反器轉換形式的資訊可參考Fundamentals of Logic Design by Charles H. Roth, West Publishing Company, 1979,p 233。例如,可以用圖13所示一設定/重設正反器 來取代D型正反器,將原本的D邏輯路徑切成一正與負邏 • 輯路徑來作為設定(S)與重設(R)輸入即可簡單地達成。 與D型正反器相似的方式,圖14中設定/重設正反器 包含兩個閂141、142由一時脈緩衝網路143所連結。另外, 相似於D型閂,每一個RS閂(RS-latch)係由一輸入缓衝反 向階段、一時脈隔絕機制151與一訊號擷取機制152所組 成,如圖15所示。D型閂使用一傳送閘做為時脈隔絕機制, 其中RS閂利用一 NAND功能去切割資料路徑S與R成為訊 ® 號擷取機制152。就D型閂與RS閂以及D型正反器與設定 /重設正反器之間的相似性來考量,上述藉由修改時脈缓衝 網路與簡化閃來最佳化設定時間與傳遞延遲之方法亦可用 在設定/重設正反器的設計上。待一時脈傳遞最佳化的設定 /重設正反器與一設定最佳化的設定/重設正反器建構完成 後,即可加入合成目標函式庫,並且以本發明圖16中所示 之方法來施行。 21 1316787 · 關鍵路徑時序開始於設定/重設正反器161之—時脈 至Q/召傳遞延遲,如互補路徑P1與汚所示’該路徑時序繼 續經過路徑邏輯電路163之組合邏輯電路。關鍵路徑時序 尚需加入設定/重設正反器162之設定時間,其以路徑時序 P2與丙表示。圖16舉例了本發明的一實施方式,正反器 161係針對快速時脈至Q/3之傳遞最佳化,而正反器162 係針對快速設定/重設輸入設定至時脈訊號CU最佳化。該 電路係根據現今技術進行改良,其中每一個相同功能的二 反器亦具有相同之時序最佳化。 圖17繪不-合成設計流程之一關鍵路徑時序,此路徑 時序包含-傳遞延遲最佳化的時脈邏輯電路單元與一設: 時間最佳化的時脈邏輯電路單心第—時脈邏輯電路=元 171係經特別設計以最佳化其時脈至The flip-flop of Fig. 8 is more optimized than the flip-flop of 圄1 τ U τ , and the flip-flop of Fig. 8 is the choice of off + in Fig. 6. The start of the path timing flip-flop 61 is better to review the set time, the table shows the m shovel I) ^ ~,,, Figure 2 (b) 1 埠 and 3 埠 control allows the data to be passed through the reverser 21 ^ 9q . 0a 〇 ^ pass the gate 22 and affect the data acquisition mechanism 23 . In the latch 20, the step is adjusted to 1. Then, the transfer gate 22 is closed and the data stream D and the signal acquisition mechanism 23 are asked to further data flow. The set time is the delay of the transition between the data D and 〆#, so that a possible transition in the owed _ more can be divided? The conversion closes the transfer 2 and is correctly delivered and stored in the number capture mechanism 23. Figure 3 shows the measurement waveform of the network +, the channel α, , and the day-to-tDc. The positive and negative of Figure 8 closes flash 1 (81) faster than the flip-flop of Figure 4, since the flip-flop of Figure 8 uses a clock network 83 with fewer buffered inverter stages. Assume that the two flip-flops are 1 ((1) are designed to be the same, as shown in Figure 8 ^ For the flip-flop, the data D 1 will arrive earlier, because the 4 and the signals of the flip-flop of Figure 8 arrive earlier. That is, the flip-flop of Fig. 8 shows a set time of one wheel. Therefore, in terms of the sock gas +/- χ heart time, the positive and negative phases of the ® 4 are more optimized, and The critical path of Figure 6 is 1316787. Overall, the flip-flop of Figure 4 will be a better choice for the flip-flop 62. It can be seen that the optimization of either the transfer delay or the set time can be adjusted by a given positive The delay is achieved by the delay of the clock network. The second method of reducing the size of the latch component to optimize the set time and the transfer delay is well known to those skilled in the relevant art. For details, please refer to Logical Effort (Logical Effort by I) Sutherland, et al, Morgan Kaufmann Publishers, 1999, pp. 45-61). Some degree of pass-through delay or set-time optimization can be performed on the flip-flop through transistor reduction and buffer configuration. The latch of the component itself. The transistor in a digital circuit can be imagined as An electronic switch, as shown in Figure 9. A latching element, such as the CMOS inverter 90 shown in Figure 9(a) (also referred to 21 of Figure 2(b)) has an N-channel device 92 and a P-channel The device 93, as shown in Fig. 9(b), has a width/length ratio of Wn/Ln and Wp/Lp, respectively. The circuit can be modularized into a network of two switches 94, 95 as shown in Fig. 9(c). The conduction resistance Rnl of the switch is inversely proportional to the width/length ratio of the N-channel device 92. Similarly, the conduction resistance RP1 of the switch is inversely proportional to the width/length ratio of the P-channel device 93. The resistors Rnl and RPl Limiting the current that can be forced through the transistor switches 94, 95 for a given supply voltage. All solid structures themselves have a capacity to store a certain amount of charge, a property known as a capacitor. In the application of the transfer delay, it is a parasitic phenomenon that limits the opening and closing speed of a transistor. This is 15 1316787 because the voltage change rate of an electrical contact is proportional to the current charging of the contact' and the contact The capacitance characteristics are inversely proportional. For example, there are two capacitors Cil and Cpl in the qjos inverter 90 of Figure 9(c). Capacitance of Cii Into the junction A, and proportional to the gate region WpLp + WnLn of the transistor. Capacitor Q is an output valley, which is related to the structure of the source and the drain, and is proportional to the sum of the widths of the transistors wp + wn. 10(ac) is a similar module analysis of a basic latch (refer to component 22 shown in Figure 2(b)). A detailed module analysis of Figure 1 (c), switch resistor R „2 and RP2 are inversely proportional to Wn/Ln& ^/^, respectively. Unlike the inverter 90, which activates only one of the n-channel 92 and the p-channel 93 in a given state, the transfer gate switches 104, 1〇5 are simultaneously turned on or simultaneously turned off. Signal # must drive an input capacitor CiZn, which is proportional to the area of the n-channel transistor W„Ln. Similarly, the signal must drive an input capacitor C%, which is proportional to the area of the P-channel transistor WpLp. Capacitor U2a Similar to the size of the 匕^ system and proportional to the sum of the widths of the ^ WP transistors. In order to reduce the delay of a transistor circuit, it is necessary to minimize the switching resistance and the load capacitance charged by the switching resistor, the switching resistance and the load capacitance. The product is directly proportional to the transfer delay. In the prior art, if a device is maintained for a constant length, the width of the device can be increased to lower the switching resistance of the transistor, thereby reducing the driving of a given load. The transfer delay of the switch of the capacitor needs to be optimized when the device is added to the network 16 1316787. This is because increasing the width of a transistor presents a large load capacitance to the previous state of driving the transistor. If the basic transistor module theory is applied to the latch 20 of Figure 2, the possibility of setting the latch 20 and optimizing the transfer delay can be listed. The limit, as shown in Figure 11, for simplicity, a simple analysis describes the single low-to-high transition of the switch in D. A common specification in the unit design (ce 11 design) is the limit • Maximum input and load Capacitance. Referring to Figure 11(a), these capacitors are Cin and Cl. Setting the latch input capacitance establishes the input capacitance of the input inverter 111, thereby limiting the maximum width and limiting the minimum switching resistance Rin and parasitic capacitance. CPin. In Figure 11(b), the signal acquisition mechanism feedback inverter 114 only needs to compensate for the process 1 eakage and increase the latch-to-missing of the latches, so a large-width transistor is not necessary. In addition, large-width transistors also increase Cfin, thus increasing the load capacitance of the output driver 113 in addition to the ClI 16 •. For these reasons, the pumping mechanism feedback inverter 114 is typically reduced to the minimum transistor allowed by the process. Width. Due to the above limitation, substantially only the transfer gate 112 and the output driver 113 can be optimized as basic components, although precise optimization requires complicated modularization and power. Simulation, some basic concepts can still be obtained for a device that optimizes the transfer delay or set time. For example, in Figure 11(b), the width of the transistor including the output driver 113 17 1316787 can be increased. The transfer delay of the latch is reduced until the parasitic capacitance CPd reaches the effective load capacitance exhibited by the capacitances Cfin and Cl. Increasing the transistor width reduces the drive resistance Rd and minimizes the transfer delay of the output driver 113. The step-by-step increase in the transistor width is Substantially, the delay is not reduced because the reduction in the drive resistance is achieved by proportionally increasing the parasitic capacitance Cpd of the transistor itself. Minimizing the transfer delay through the transfer gate U2 is more complicated because the transfer gate 112 does not generate a signal gain when only the load capacitance Cl 116 is coupled to the input inverter lu. The input inverter nl actually supplies a charging current to a parasitic capacitance including CPin, CPtgl, Cptg2, Cdin, and Cpf. Since cin is fixed, the input inverter lu drive resistance is fixed to Rin, and the input inverter 111 is provided. The parasitic load is fixed to the pin. Since the feedback inverter is a minimum device, the signal captures the parasitic capacitance of the feedback inverter (^ is fixed, and after the transmission described in the previous paragraph is optimized, Cdin is fixed. Increasing the width of the transistor in the transfer gate 112 will It will reduce the overall switching resistance of Rin + Rtg, but also increase the parasitic capacitance (^(4) and cPtg2. However, when the width of the device of the transfer gate 112 increases, the transfer delay of the transfer gate 112 will decrease until the overall parasitic capacitance CPtsl + CPtg2 The same amount of capacitance as presented by cdin, cPf and cPin is achieved. The optimization of the minimum transfer delay of the combined transfer gate 112 and the output driver 113 produces a minimum transfer delay optimized latch. Minimized time 18 1316787 * The sequence path is from 0/7埠 through the transfer gate 112, the output driver 113 to the load capacitance Cl Π6 seen at Q 。. The optimization of the latch set time is generally different from the optimization of the transfer delay because of the need to emphasize Different timing paths. For example, in the gate of Figure ,, the signal acquisition mechanism Π5 must be switched as quickly as possible. To achieve this, it is necessary to minimize the contact from 12 to Q and back to 12 Loop delay, which means limiting the tolerable load capacitance ClI 16. Reducing the loop delay from contact 12 to Q and back to 12 • reduces the input capacitance Cdin of the output driver 113, which means that the width of the driver 113 needs to be reduced. To a minimum, the settling time can be reduced but at the expense of the flash transfer delay. The capacitive load exhibited by the transfer gate 112 also needs to be minimized, while the transfer gate width is reduced to the parasitic capacitance CPtgl and (: ring 2 is close to being The reduced load of CdinK is presented. The minimum setting optimization of the combined transfer gate 112 and the output driver 113 provides a minimum set optimized latch. The optimized path is from the D input through the input inverter 111. The transmission gate 112, the output driver 113, and finally the feedback inverter 114 is returned to the signal through the signal. The input signal from the D埠 must be delivered through the path, and the signal acquisition function is completed, which must be performed by the signal. ^ and ^ stop the transfer gate 112 to isolate the signal capture mechanism 115. The basic structural modification of the latch of Fig. 11(a) can also be used to optimize the set time. A device that minimizes settling time involves shrinking the output drive 19 1316787 actuator 113 and minimizing the load capacitance Cl 116. A common device that limits the effect of a latched Cl 125 is to use the load capacitance Cl 125 to buffer the contact 14 as shown in FIG. (a) shows that the buffer contact 13 can reduce the delay from 12 to 13 and back to the entire loop of 12, but note that the transfer delay has been increased by the delay of the buffer 124. An additional device that reduces the set time The removal of the input inverting buffer 120 and the relying on the output of the previous stage are included to drive the latch data input D, as shown in Figure 12(b). The same buffering concept of Figure 12(a) can be used to coordinate the logical polarity of D to Q. Since the data transfer delay path has been reduced by an inverter transfer delay, and the set path involves the relative timing of the data and the clock path, the set time is substantially reduced by the reverser transfer delay of one of Figure 12(a). One possible disadvantage of releasing the input data inverter is that this method requires additional synthesis constraints and characteristics, taking into account the latch input impedance and the drive capability of the previous stage. The essence of the invention is to synthesize a design from a target library that has two identical functions but different ordering units for optimizing timing. A sequence unit involves a large family of cells that have the ability to store data status. Throughout this family are a group of latches and flip-flops, each of which can be used in the present invention as long as it can establish a sequence unit with different settings or transfer delay optimizations. Methods for optimizing CMOS latches and a D-type flip-flop have been discussed in detail, however, these methods can be applied to other types of flip-flops in the same way as 20 1316787. Although the present invention utilizes a D-type flip-flop, it is a common practice to add an external gate to convert a form of flip-flop to another form. For more information on the form of the flip-flop conversion, refer to Fundamentals of Logic. Design by Charles H. Roth, West Publishing Company, 1979, p 233. For example, a D-type flip-flop can be replaced with a set/reset flip-flop as shown in FIG. 13 to cut the original D logical path into a positive and negative logical path for setting (S) and resetting ( R) Input can be easily achieved. In a similar manner to the D-type flip-flop, the set/reset flip-flop in FIG. 14 includes two latches 141, 142 connected by a clock buffer network 143. In addition, similar to the D-type latch, each RS latch is composed of an input buffer reverse phase, a clock isolation mechanism 151 and a signal capture mechanism 152, as shown in FIG. The D-type latch uses a transfer gate as a clock isolation mechanism, wherein the RS latch uses a NAND function to cut the data paths S and R into a signal capture mechanism 152. Considering the similarity between the D-type latch and the RS latch and the D-type flip-flop and the set/reset flip-flop, the above-described optimization of the settling time and transmission is achieved by modifying the clock buffer network and simplifying the flash. The delay method can also be used to set/reset the design of the flip-flop. After the setting/reset flip-flop of a clock transfer optimization and the setting/reset of the set optimization are completed, the synthesis target library can be added, and the image of the synthesis target library is used in the present invention. Show the method to implement. 21 1316787 • The critical path timing begins with setting/resetting the flip-flop 161 to the Q/call transfer delay, as shown by the complementary path P1 and the dirty path. The path timing continues through the combinational logic of the path logic circuit 163. Critical Path Timing It is necessary to add the set time of the set/reset flip 162, which is represented by the path timings P2 and C. Figure 16 illustrates an embodiment of the present invention. The flip-flop 161 is optimized for fast clock to Q/3 transfer, and the flip-flop 162 is set for the fast set/reset input to the clock signal CU. Jiahua. The circuit is modified in accordance with today's technology, in which each of the same function flip-flops has the same timing optimization. Figure 17 depicts a critical path sequence for a non-synthesis design flow. The path timing includes a clock logic unit optimized for the transfer delay and a set: time-optimized clock logic circuit single-core-clock logic Circuit = Element 171 is specially designed to optimize its clock to
傳遞延遲,㈣二時脈邏輯電路單 元172係最佳化其In_2至時脈(In^t〇—ακ)設定時間。 熟知相關技術者可_㈣推知1脈賴電路單元可有 更多的輸人及/或更多的輸出,在這樣的情形下,每一個時 脈至Out—i傳遞延遲與每-個In」至時脈設定時間必需各 自作最佳化。每-個時脈邏輯電路單元只最佳化一部份, 例如傳遞延遲或設定_兩者之―,來排除先前技術中在 這兩個時序間所做的妥協。關鍵路徑時序係以時脈邏輯電 22 1316787 路單元1、171之時脈至Out_l傳遞延遲、路徑邏輯電路 173傳遞延遲、與In_2至時脈設定時間來決定。顯然根據 具體實施例之最佳化時脈邏輯電路單元縮短了關鍵路徑時 序,間接地加速了電路的作業。 參照第18圖,其示意本發明之一合成設計流程之一作 業流程圖。該作業啟始於步驟181,其中一第一時脈邏輯 電路單元乃設計為具有一最佳化時脈至 鲁 Out_l(Clock-to-Out_l)傳遞延遲。該最佳化可由在正反器 層用簡化閘元件或調整時脈網路延遲來達成。在步驟182, 一第二時脈邏輯電路單元乃設計為具有一最佳化之In_2 至時脈(In_2-t〇-CLK)設定時間,該最佳化係如上述對第一 時脈邏輯電路單元所做之最佳化來達成。步驟183將第一 時脈邏輯電路單元配置於一路徑邏輯電路之前,同樣地, 步驟184將第二時脈邏輯電路單元配置於該路徑邏輯電路 ® 之後。關鍵時序路徑係由第一時脈邏輯電路單元之時脈至 Out_l傳遞延遲、路徑邏輯電路之傳遞延遲與第二時脈邏 輯電路單元之In_2至時脈設定時間來決定。在這種情形 下,藉由關鍵路徑之較佳的時序最佳化,本發明將可以改 善設計速度與降低電力消耗,並且本發明可以現今之邏輯 電路合成技術來施行該設計。 雖然上述之一些具體實施例中是從設計一具有最佳化 23 1316787 遞送延遲正反器與另一具有最佳化的設定時間之正反器來 考量,以降低關鍵路徑時序,包含其精神與領域之其他方 式亦可用以施行於本發明。例如,其它時脈邏輯電路單元 可用以被最佳化來降低關鍵路徑時序,在此考量下,圖6 與圖8所述之具體實施例僅為了用來幫助呈現本發明運用 正反器或時脈邏輯電路所達成之相關優點,並非用以限定 本發明。 顯然地,依照上面實施例中的描述,本發明可能有許 多的修正與差異。因此需要在其附加的權利要求項之範圍 内加以理解,除了上述詳細的描述外,本發明還可以廣泛 地在其他的實施例中施行。上述僅為本發明之較佳實施例 而已,並非用以限定本發明之申請專利範圍;凡其它未脫 離本發明所揭示之精神下所完成的等效改變或修飾,均應 包含在下述申請專利範圍内。 【圖式簡單說明】 圖1係為合成設計流程中具有兩標準正反器之一關鍵 路徑流程示意圖; 圖2(a)係為一典型閂的符號表示; 圖2(b)係以電晶體來實現之一典型閂示意圖; 圖3係一典型閂之時序關係示意圖; 圖4係一包含兩個閂與一時脈網路之典型正反器單元 24 • 1316787 之不意圖, 圖5係一典型正反器之時序關係示意圖; 圖6係在合成設計流程中具有一傳遞延遲最佳化之正 反器與一設定時間最佳化之正反器之一關鍵路徑時序示意 圖, 圖7係本發明在關鍵時序路徑之時序關係示意圖; 圖8係藉由修正時脈緩衝網路來最佳化之正反器時脈 • 傳遞延遲示意圖; 圖9(a)至圖9(c)係一緩衝反向器之電路模組示意 圖,該缓衝反向器一基本的閂元件。 圖10(a)至圖(c)係一傳送閘之電路模組,該傳送閘係 一基本的閂元件; 圖11係一典型D型閂之簡化電路模組; 圖12(a)與圖12(b)係典型D型閂之另外的結構,其最 ®佳化了資料設定時間; 13圖示意了在D型正反器與設定/重設正反器功能間 的關係; 圖14示意了包含兩RS閂與一時脈缓衝正反器之一典 型設定/重設正反器; 圖15示意包含組合了輸入緩衝/時脈隔絕階段與輸出 缓衝/訊號擷取階段之典型RS閂; 25 1316787 圖16示意了在合成設計流程中具有一傳遞延遲最佳 化之設定/重設正反器與一設定時間最佳化之設定/重設正 反器之一關鍵路徑時序; 圖17係在合成設計流程中具有傳遞延遲最佳化之時 脈邏輯電路單元與一設定時間最佳化之時脈邏輯單元之一 關鍵路徑時序示意圖;以及 圖18係本發明之一合成設計流程之流程圖。 • 【主要元件符號說明】 卢/》埠 A 輸入接點 Cdin 電容 Cf in 電容 Cil 電容 Ci2p 電容 Ci2n 電容 Cl 電容 CpI電容 Cp2a 電容 Cp2b 電容 CPd寄生電容 Cpf 電容 26 1316787 ·The transfer delay, (4) two-clock logic circuit unit 172 optimizes its In_2 to clock (In^t〇-ακ) set time. Those skilled in the art can _(4) to infer that a pulse circuit unit can have more input and/or more output. In this case, each clock to Out-i transmits a delay and every In" The time to clock setting must be optimized separately. Each clock circuit unit optimizes only a portion, such as pass delay or set _ both, to eliminate the compromises made between the two timings in the prior art. The critical path timing is determined by the clock logic 22 1316787 channel unit 1, 171 clock to Out_l transfer delay, path logic circuit 173 transfer delay, and In_2 to clock set time. It is apparent that the optimized clock logic unit in accordance with a particular embodiment shortens the critical path timing and indirectly accelerates the operation of the circuit. Referring to Fig. 18, there is shown a flow chart of one of the synthetic design flows of the present invention. The operation begins in step 181, wherein a first clock logic circuit unit is designed to have an optimized clock to Out_l (Clock-to-Out_l) transfer delay. This optimization can be achieved by using a simplified gate element or adjusting the clock network delay at the flip-flop layer. In step 182, a second clock logic circuit unit is designed to have an optimized In_2 to clock (In_2-t〇-CLK) set time, the optimization being as described above for the first clock logic circuit The optimization of the unit is achieved. Step 183 configures the first clock logic circuit unit before a path logic circuit. Similarly, step 184 configures the second clock logic circuit unit after the path logic circuit ® . The critical timing path is determined by the clock of the first clock logic unit to the Out_l transfer delay, the transfer delay of the path logic circuit, and the In_2 to clock set time of the second clock logic circuit unit. In this case, the present invention will improve design speed and power consumption by better timing optimization of critical paths, and the present invention can be implemented by today's logic circuit synthesis techniques. Although some of the above specific embodiments are designed to reduce the critical path timing from the design of an optimized 23 1316787 delivery delay flip-flop with another optimized set-time flip-flop, including its spirit and Other ways of the field can also be used to implement the invention. For example, other clock logic circuit units can be optimized to reduce critical path timing. In this regard, the specific embodiments illustrated in Figures 6 and 8 are only used to help present the present invention using a flip-flop or time. The related advantages achieved by the pulse logic circuit are not intended to limit the invention. Obviously, many modifications and differences may be made to the invention in light of the above description. It is therefore to be understood that within the scope of the appended claims, the invention may be The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the claims of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following claims. Within the scope. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a critical path flow with two standard flip-flops in a synthetic design flow; Figure 2(a) is a symbolic representation of a typical latch; Figure 2(b) is a transistor A typical latch diagram is shown; Figure 3 is a schematic diagram of the timing relationship of a typical latch; Figure 4 is a schematic diagram of a typical flip-flop unit 24 • 1316787 comprising two latches and a clock network, Figure 5 is a typical Schematic diagram of the timing relationship of the flip-flop; FIG. 6 is a schematic diagram of a critical path timing of a flip-flop having a transfer delay optimization and a set time optimization in the synthetic design flow, and FIG. 7 is a schematic diagram of the present invention. Schematic diagram of the timing relationship in the critical timing path; Figure 8 is a schematic diagram of the forward and reverse clocks and propagation delays optimized by modifying the clock buffer network; Figure 9(a) to Figure 9(c) are a buffered inverse A schematic diagram of a circuit module of a transmitter, the buffer inverter being a basic latch component. Figure 10 (a) to (c) is a circuit module of a transfer gate, the transfer gate is a basic latch component; Figure 11 is a simplified circuit module of a typical D-type latch; Figure 12 (a) and Figure 12(b) is another structure of a typical D-type latch, which is the best for data setting time; Figure 13 shows the relationship between the D-type flip-flop and the setting/reset flip-flop function; A typical set/reset flip-flop that includes two RS latches and a clock buffer flip-flop is shown; Figure 15 shows a typical RS that combines the input buffer/clock isolation phase with the output buffer/signal capture phase. Latch; 25 1316787 Figure 16 illustrates one of the critical path timings of a set/reset flip-flop with a set delay optimization and a set time optimization of the transfer delay optimization in the synthetic design flow; 17 is a schematic diagram of a critical path timing of a clock logic unit with a transfer delay optimization in a synthetic design flow and a time-optimized clock logic unit; and FIG. 18 is a synthetic design flow of the present invention. flow chart. • [Main component symbol description] Lu / "埠 A input contact Cdin capacitor Cf in capacitor Cil capacitor Ci2p capacitor Ci2n capacitor Cl capacitor CpI capacitor Cp2a capacitor Cp2b capacitor CPd parasitic capacitor Cpf capacitor 26 1316787 ·
Cpin 電容Cpin capacitor
Cptgl電容 Cptg2電容 CLK 時脈 D 貧料輸入 11 接點 12 接點 • 13接點Cptgl capacitor Cptg2 capacitor CLK clock D poor input 11 contact 12 contact • 13 contact
In_l輸入埠 In_2輸入埠 Out_l 輸出埠 Out_2 輸出埠 P1 傳遞路徑 P2 傳遞路徑 ® ρϊ 與P1互補之傳遞路徑 Μ與P2互補之傳遞路徑 Q 埠 δ 埠 S 設定埠 R 重設埠In_l input 埠 In_2 input 埠 Out_l output 埠 Out_2 output 埠 P1 transfer path P2 transfer path ® ρ 互补 Complementary transfer path with P1 传递 Complementary transfer path with P2 Q 埠 δ 埠 S Set 埠 R Reset 埠
Rd 電阻 27 1316787 ·Rd resistance 27 1316787 ·
Rf 電阻Rf resistance
Rin 電阻 Rni電阻 Rn2電阻 RP1電阻 RP2電阻 Rtg 電阻 Wn/Ln長寬比 Wp/Lp長寬比 Y 輸出接點 tcQ 傳遞延遲 tcQi 時脈至Q(C1 ock-to-Q)的傳遞延遲 tcQ2 時脈至Q(C1 ock_to-Q)的傳遞延遲 tDC 設定時間 tDci D至時脈(D_to-Clock)之設定時間 tDC2 D至時脈(D-to-Clock)之設定時間 tpathlogic路徑邏輯電路13之傳遞延遲 11 標準正反器1 12 標準正反器2 13 路徑邏輯電路 20 閘 28 1316787 21 緩衝反向器 22 傳送閘 23 訊號擷取機制 41 閂1 42 閂2 43 時脈網路 61 具有快速時脈至Q延遲(Clock-to-Q)之正反器 I 62 具有快速D至時脈設定(D-to-Clock)之正反器 63 路徑邏輯電路 81 閂1 82 閂2 83 時脈網路 90 正反器 92 反向器 ^ 93 P通道裝置 94 開關 95 開關 100 傳送閘 102 閘 103 閘 104 傳送閘開關 29 .1316787 105 傳送閘開關 111 輸入反向器 112 傳送閘 113 輸出驅動器 114 擷取機制回饋反向器 115 訊號擷取機制 116 負載電容 • 120 輸入反向緩衝器 121 傳送閘 122 緩衝反向器 123 缓衝反向器 124 缓衝器 125 電容 126 傳送閘 • 127 緩衝反向器 128 緩衝反向器 129 缓衝反向器 141 RS閂 142 RS閂 151 時脈隔絕機制 152 訊號擷取機制 30 1316787 161 設定/重設正反器 162 設定/重設正反器 163 路徑邏輯電路 171 第一時脈邏輯電路單元 172 第二時脈邏輯電路單元 173 路徑邏輯電路 181 設計一具有最佳化之傳遞延遲之第一時脈邏輯電 Φ 路單元 182 設計一具有最佳化之設定時間之一第二時脈邏輯 電路單元 183 配置第一時脈邏輯電路單元於路徑邏輯電路之前 184 配置第二時脈邏輯電路單元於路徑邏輯電路之後 31Rin resistor Rni resistor Rn2 resistor RP1 resistor RP2 resistor Rtg resistor Wn/Ln aspect ratio Wp/Lp aspect ratio Y output contact tcQ transfer delay tcQi clock-to-Q (C1 ock-to-Q) transfer delay tcQ2 clock The transfer delay tDC to Q (C1 ock_to-Q) sets the time tDci D to the set time of the clock (D_to-Clock) tDC2 D to the set time of the clock (D-to-Clock) tpathlogic the transfer delay of the path logic circuit 13 11 Standard flip-flops 1 12 Standard flip-flops 2 13 Path logic 20 Gate 28 1316787 21 Buffer reverser 22 Transfer gate 23 Signal capture mechanism 41 Latch 1 42 Latch 2 43 Clock network 61 has a fast clock to Q-delay (Clock-to-Q) flip-flop I 62 flip-flop with fast D to clock-set (D-to-Clock) 63 path logic 81 latch 1 82 latch 2 83 clock network 90 positive Counter 92 Inverter ^ 93 P channel device 94 Switch 95 Switch 100 Transfer gate 102 Gate 103 Gate 104 Transfer gate switch 29 .1316787 105 Transfer gate switch 111 Input inverter 112 Transfer gate 113 Output driver 114 Capture mechanism feedback Transmitter 115 Signal Acquisition Mechanism 116 Load Capacitance • 120 Input Reverse Buffer 121 Transfer Gate 122 Buffer Inverter 123 Buffer Inverter 124 Buffer 125 Capacitor 126 Transfer Gate • 127 Buffer Inverter 128 Buffer Inverter 129 Buffer Inverter 141 RS Latch 142 RS Latch 151 Clock isolation mechanism 152 Signal acquisition mechanism 30 1316787 161 Setting/resetting flip-flop 162 Setting/resetting flip-flop 163 Path logic circuit 171 First clock logic circuit unit 172 Second clock logic circuit unit 173 Path The logic circuit 181 designs a first clock logic φ circuit unit 182 having an optimized transfer delay. The 182 circuit unit 182 is configured to have an optimized set time. The second clock logic circuit unit 183 configures the first clock logic circuit unit. Before the path logic circuit 184 configures the second clock logic circuit unit after the path logic circuit 31
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