TWI316787B - Method for optimizing critical path timing in a logic synthesis flow and data processing system - Google Patents

Description

1316787 * IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to logic synthesis of electronic circuit design, and more particularly to a system and method for optimizing critical path timing in a logic circuit synthesis process . [Prior Art]

The logic circuit synthesis is designed by the basic logic circuit function block to design a complex logic circuit function, which is derived from the target function library of the basic logic circuit function. The compositing process usually begins with defining the complex functions to be achieved in a high-order description language. Synthesizing the process and establishing an interconnected set of basic logic circuit blocks to achieve the above-described defined complex logic circuit functions. 'Each basic logic circuit block or unit (eell) contains a group of one or more circuit elements, these are pieces Discrete transistors, electric valleys, and other groups of basic circuit components that perform simple-simple basic functions. There are at least two types of logic circuit units: the combination unit—toriai cells) and the sequence unit (the piano (9) coffee (10) small combination single 7L performs the most basic Boolean logic function.

Such as NAND, M0R, logic inversion, its # by _bining electronic signal input into a simple logic output 'to achieve these simple functions. All achievable electronic circuits require finite time to pass a logic circuit function. This time is called the transfer delay. Due to the need to be combined by the basic transistor 5 1316787 * components into different configurations 'different logic circuit functions usually have different transfer delays. The more complex the logic circuit functions synthesized by the combination block, the more substantial the number of logic circuit paths formed, which are the input of the electronic signal from the input set of the combination unit to the output path. The more complex logic circuits are implemented, the more difficult it is to coordinate the timing of the transfer of logic paths. If the timing of the logic circuit is not well coordinated, the logic circuit function may exhibit an abnormal behavior that cannot be reproduced or a complete failure. The sequence unit is a special logic circuit that cooperates with a so-called clock synchronization signal to adjust the timing of the logic circuit path. These units stop or permit logic signals to pass through a complex logic function, such as traffic signals to coordinate traffic flow, as the entire design synchronization event occurs. The sequence unit stops the logic data by storing the data in a memory function until the clock passing time occurs. The time required to pass the stored logical data to the unit clock is called the clock transmission delay (cl〇ck pr〇pagati〇]1 delay). Before the logic-haiting ci〇ck event perfects the storage of data, the time required to present this data is called the set time (setup tlme). The order of the sequence unit, such as the flip-flop (flip- Flops) and latches. A logic circuit path that begins with a clock event with a flip-flop or latch data and stops the clock event with a flip-flop or a data message is called a 1316787-timing path. It follows from this that a timing path with two sequential units needs to be connected by the combining unit to the two sequential units. A timing path includes the clock transfer delay of the first sequence unit, the transfer delay of the combining unit, and the set time required by the second sequence unit. The longest timing path in a logic circuit design often limits the overall design performance and is therefore referred to as a critical timing path. Optimizing this logic to improve a logic circuit design during synthesis • Timing paths are extremely important. Figure 1 is a schematic diagram of a critical timing path with two standard flip-flops in a synthetic design flow. This path logic circuit contains a special combination of unit logic circuits capable of performing any of the logic circuit functions. As shown in FIG. 1, the critical timing path is delayed by the clock of the flip-flops 1 and 11 to Q (Clock-to-Q). (tc〇i), the transfer delay of the path logic circuit 13 (tpathiogic), and the set time t1) C2 of the D to the clock of the flip-flops 2 and 12 (D-to-Clock). ® —The standard flip-flop contains two similar latches, one primary latch determines the settling time from D to the clock, and the other slave latch provides the clock-to-Q transfer delay. If the D to the set time of the clock is optimized, the delay to the clock to Q will be adverse, and vice versa. Therefore, for a standard flip-flop, a compromise must be made between the primary and secondary latches. In addition to the flip-flops, common design techniques can utilize two separate latches to implement timing functions and provide path logic between the two latches, 7 1316787 but these techniques require more complex timing analysis and are more difficult It is done automatically by a logic synthesis tool. There is therefore a need for a method or system to optimize critical path timing in a logic circuit assembly process that can be implemented in the prior art of logic circuit synthesis. SUMMARY OF THE INVENTION In view of the above described background, in order to meet the needs of industrial interests, an embodiment of the present invention provides a method and system for optimizing critical path timing in a logic circuit synthesis process, which can be used to solve the above conventional techniques. Failure to achieve the target. In one embodiment, a system for optimizing critical path timing in a logic circuit synthesis flow is disclosed, the system including a first clock logic circuit unit for optimizing the transfer delay, and a set time optimization A two-way logic circuit unit and a path logic circuit. The output of the first clock logic circuit unit is coupled to the path logic circuit and transmitted to the path logic circuit for processing. The second clock logic circuit unit has the same logic circuit function as the first clock logic circuit unit, the input of which is coupled to the output of the path logic circuit. The output of the path logic circuit is passed to the second clock logic circuit unit for processing. The critical path timing is determined by the transfer delay of the first clock logic circuit unit, the transfer delay of the path logic circuit, and the set time of the second clock logic circuit unit. In the logic synthesis process, the design speed and power consumption can be improved by the better critical path of the clock. Another embodiment of the present invention provides a system for optimizing critical path timing in a logic circuit synthesis flow, the system having a path logic circuit and a transfer delay optimized clock logic circuit unit. The output of the clock logic circuit unit is coupled to the input of the path logic circuit and passed to the path logic circuit for processing. Yet another embodiment of the present invention provides a system for optimizing the key path clock in a logic synthesis process. The system includes a path logic circuit and a set time optimized clock circuit unit. The clock logic circuit unit is coupled to the path logic circuit for receiving and processing the output of the path logic circuit. In one embodiment, the present invention provides a method of optimizing a critical path clock in a logic synthesis process. The method includes designing a first clock logic circuit unit having an optimized transfer delay and a second clock logic circuit unit having an optimized settling time. The method includes the steps of coupling the first clock logic circuit unit to the path logic unit and transmitting the output of the first clock logic circuit unit to the path logic unit for processing. The method further includes coupling the second clock logic circuit unit to the path logic circuit to receive and output the processing circuit logic circuit, the second clock logic circuit unit having the same logic function as the first clock logic circuit unit. [Embodiment] The direction of the present invention discussed herein is a method and method for optimizing the _path timing in a logic circuit synthesis flow. In order to fully understand the present invention, detailed steps and compositions thereof will be presented in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the art of methods and methods for optimizing the routing of logic circuits. The other aspects are well-known (four) into steps or steps are not described in the details, in order to avoid the necessary restrictions on the hair of the rabbit. The present invention (four) preferred embodiment will be detailed, as detailed below 1 and except for these detailed descriptions The invention can also

It is widely practiced in other embodiments, and the scope of the invention is not limited, and the scope of the listed patents will control. It can be seen from Fig. 1 that the flip-flops η, 12 and the path logic unit 13 construct the most critical sequential circuits to organize the signal timing and flow of the system. The main component used to construct a flip-flop is a latch. In Fig. 2(a), a representative symbol of a code 20 is used; and with reference to Fig. 2b, a schematic diagram of a tag 20 for performing a transistor is exemplified. The latch 20 includes a buffer inverter 21, a transfer gate 22 and a signal extraction mechanism 23. When the complementary clock signal 彡 and g enable the transmission gate 22, the output of the buffer reverse n 21 is output to the signal acquisition mechanism 23. The structure enables the wheelman signal D to drive the buffer reverser 21 spot transmission gate 22, and controls the signal acquisition mechanism ', 嚆", 妳传诚's shape L, and appears at the end of the Q wheel. Round eight · Tiger please, 4 sides become - lose # pass time W flash ... With the day as shown in Figure 3, -1 another characteristic delay is tCQ, the delay is when the tank TM is turned on, stable input News 2;; 1316787 Time required to output Q. To achieve a fast circuit, the transfer delays tDQ and tcQ need to be reduced to their minimum values. Another primary timing relationship is the set time tDC, which occurs before the complementary clock signal turns off the transmit gate 22 and the isolated signal capture mechanism 23, as shown in FIG. In order for the signal acquisition mechanism 23 to reflect the correct state of the signal D, the signal D must reach a stable logic state before the signal acquisition mechanism 23 is blocked by the transmission gate 22 for a certain period of time. For a fast circuit, the minimum lubricated set time tDC is also required. Since the buffer reverser 21, the transfer gate 22 and the signal capture mechanism 23 are interconnected, the timing parameters tDC, tDQ and 1^ of a latch are not independent of each other. For example, increasing the drive strength of the transfer gate 22 reduces the transfer time tCQ, but the additional parasitic load causes the set time to increase. Thus, those skilled in the art will be able to easily infer the inverse relationship between the parameters tcQ and tDC. Referring to Figure 4, a typical inverter unit is illustrated which includes two series of latches 41, 42 and a clock network 43. The clock network 43 allows data to pass through the latches 41, 42 to adjust the data stream when the clock is inverted. Figure 5 illustrates the timing relationship of the clock CLK, the data input D, and the flip-flop output Q from the external ports of the flip-flop. If the transmission delay through the clock network is negligible, it can be known that the set time of the flip-flop tDC is the set time of the latch 1 (41) in the flip-flop circuit. Similarly, if the 11 1316787 delay of the clock network can be ignored, the forward-transfer delay tcQ is the tDC of the latch 2 (42).丄9 finite delay lengthens the delay of tcQ, and reduces the 'function library' to include the function of the standard flip-flop logic circuit. At the same time, "the delay between the delay delay ^ and the D to the clock setting time, ~ between the two parameters It has an inverse relationship. As shown in the figure--, in a synthetic design flow with two standard flip-flops, the clock-to-Q transfer L is delayed by tci, and D is set to the time of the clock. The key timing circuit & this is because each flip-flop and the critical path timing: f is limited to non-critical path timing. Figure 6 illustrates one of the aspects of the present invention U read 'its critical path timing has a pass The transmission of the delay optimization is positive, and the S 61 and the set-up time-optimized receiving flip-flops 62 have the same logic circuit function 35, but are designed with different (four) ordering. The pass flip-flop 61 optimizes the small transfer delay tcQi and the receive flip-flop 62 optimizes the smaller set time tDC2. The present invention provides for two independent and optimized ordering units. The library is used for the synthesis process. Passing the flip-flop 61 and all the way The transfer path between the path logic circuits 63 is P1, and the transfer path between the path logic circuit (10) and the receive flip-flop 62 is p2. Referring to Fig. 7, the timing relationship of the critical path timings in Fig. 6 is illustrated. Pulse cycle time teyeie, pass-through delay t(10) optimization pass 12 1316787

The flip-flop 61 is reflected on the transfer path ρι, and the receive flip-flop 62 of the set time is reflected on the transfer path p2. #化化—— The transfer delay of the flip-flop (such as the transfer flip-flop 61) and the optimization of another flip-flop (such as receiving the positive and negative H 62) ^, limb (four) / delivery delay The problem can be solved independently of the transfer delay tPathlogic of the general combination path logic circuit. Since the transfer of the flip-flop 7 and the tDC2 of the receive flip-flop are individually optimized to reduce the critical path timing, this innovative method of man-made is compared to the synthetic two method of using the trade-off/transfer delay flip-flop. A faster design can be achieved. Optimizing the flip-flop settings and transfer delays can be accomplished in two conventional ways, including adding/removing the clock network delay and controlling the size of the latch elements in the flip-flop layer. For details on the settings and transfer delays for optimizing the flip-flops, see Skew Tolerant Circuit Design - Book (Skew)

Tolerant Circuit Design by David Harris, Morgan Kaufmann Publishers, 2001, pp. 52-54). If the first method is used to adjust the clock network to optimize the transfer delay, please refer to FIG. 4 again. It can be seen that the clock-to-Q transfer delay timing starts at CLK埠, and the two clock networks 43 in the figure are delivered. The inverter is activated and the latch 2 (42) is activated to a transparent state such that it can deliver the data to Q埠. The shortest path from CLK 埠 to 闪 2 (42) is a single clock network reverser to 3 埠, this shortest path determines flash 2 (42) and the flip flops start to deliver the whole 13 1316787 The data of the latch 2 (42) is sputum and sputum, and the sputum takes the early time. Figure 8 shows a similar function of the bogey network, the network directly. 7 directly link CLK埠 to the latch 2 (82) $埠, establish a can be from the latch 2 (82) value, close the state Make (four)... a faster path to the data. This faster path leads to a shorter delivery delay. because

The flip-flop of Fig. 8 is more optimized than the flip-flop of 圄1 τ U τ , and the flip-flop of Fig. 8 is the choice of off + in Fig. 6. The start of the path timing flip-flop 61 is better to review the set time, the table shows the m shovel I) ^ ~,,, Figure 2 (b) 1 埠 and 3 埠 control allows the data to be passed through the reverser 21 ^ 9q . 0a 〇 ^ pass the gate 22 and affect the data acquisition mechanism 23 . In the latch 20, the step is adjusted to 1. Then, the transfer gate 22 is closed and the data stream D and the signal acquisition mechanism 23 are asked to further data flow. The set time is the delay of the transition between the data D and 〆#, so that a possible transition in the owed _ more can be divided? The conversion closes the transfer 2 and is correctly delivered and stored in the number capture mechanism 23. Figure 3 shows the measurement waveform of the network +, the channel α, , and the day-to-tDc. The positive and negative of Figure 8 closes flash 1 (81) faster than the flip-flop of Figure 4, since the flip-flop of Figure 8 uses a clock network 83 with fewer buffered inverter stages. Assume that the two flip-flops are 1 ((1) are designed to be the same, as shown in Figure 8 ^ For the flip-flop, the data D 1 will arrive earlier, because the 4 and the signals of the flip-flop of Figure 8 arrive earlier. That is, the flip-flop of Fig. 8 shows a set time of one wheel. Therefore, in terms of the sock gas +/- χ heart time, the positive and negative phases of the ® 4 are more optimized, and The critical path of Figure 6 is 1316787. Overall, the flip-flop of Figure 4 will be a better choice for the flip-flop 62. It can be seen that the optimization of either the transfer delay or the set time can be adjusted by a given positive The delay is achieved by the delay of the clock network. The second method of reducing the size of the latch component to optimize the set time and the transfer delay is well known to those skilled in the relevant art. For details, please refer to Logical Effort (Logical Effort by I) Sutherland, et al, Morgan Kaufmann Publishers, 1999, pp. 45-61). Some degree of pass-through delay or set-time optimization can be performed on the flip-flop through transistor reduction and buffer configuration. The latch of the component itself. The transistor in a digital circuit can be imagined as An electronic switch, as shown in Figure 9. A latching element, such as the CMOS inverter 90 shown in Figure 9(a) (also referred to 21 of Figure 2(b)) has an N-channel device 92 and a P-channel The device 93, as shown in Fig. 9(b), has a width/length ratio of Wn/Ln and Wp/Lp, respectively. The circuit can be modularized into a network of two switches 94, 95 as shown in Fig. 9(c). The conduction resistance Rnl of the switch is inversely proportional to the width/length ratio of the N-channel device 92. Similarly, the conduction resistance RP1 of the switch is inversely proportional to the width/length ratio of the P-channel device 93. The resistors Rnl and RPl Limiting the current that can be forced through the transistor switches 94, 95 for a given supply voltage. All solid structures themselves have a capacity to store a certain amount of charge, a property known as a capacitor. In the application of the transfer delay, it is a parasitic phenomenon that limits the opening and closing speed of a transistor. This is 15 1316787 because the voltage change rate of an electrical contact is proportional to the current charging of the contact' and the contact The capacitance characteristics are inversely proportional. For example, there are two capacitors Cil and Cpl in the qjos inverter 90 of Figure 9(c). Capacitance of Cii Into the junction A, and proportional to the gate region WpLp + WnLn of the transistor. Capacitor Q is an output valley, which is related to the structure of the source and the drain, and is proportional to the sum of the widths of the transistors wp + wn. 10(ac) is a similar module analysis of a basic latch (refer to component 22 shown in Figure 2(b)). A detailed module analysis of Figure 1 (c), switch resistor R „2 and RP2 are inversely proportional to Wn/Ln& ^/^, respectively. Unlike the inverter 90, which activates only one of the n-channel 92 and the p-channel 93 in a given state, the transfer gate switches 104, 1〇5 are simultaneously turned on or simultaneously turned off. Signal # must drive an input capacitor CiZn, which is proportional to the area of the n-channel transistor W„Ln. Similarly, the signal must drive an input capacitor C%, which is proportional to the area of the P-channel transistor WpLp. Capacitor U2a Similar to the size of the 匕^ system and proportional to the sum of the widths of the ^ WP transistors. In order to reduce the delay of a transistor circuit, it is necessary to minimize the switching resistance and the load capacitance charged by the switching resistor, the switching resistance and the load capacitance. The product is directly proportional to the transfer delay. In the prior art, if a device is maintained for a constant length, the width of the device can be increased to lower the switching resistance of the transistor, thereby reducing the driving of a given load. The transfer delay of the switch of the capacitor needs to be optimized when the device is added to the network 16 1316787. This is because increasing the width of a transistor presents a large load capacitance to the previous state of driving the transistor. If the basic transistor module theory is applied to the latch 20 of Figure 2, the possibility of setting the latch 20 and optimizing the transfer delay can be listed. The limit, as shown in Figure 11, for simplicity, a simple analysis describes the single low-to-high transition of the switch in D. A common specification in the unit design (ce 11 design) is the limit • Maximum input and load Capacitance. Referring to Figure 11(a), these capacitors are Cin and Cl. Setting the latch input capacitance establishes the input capacitance of the input inverter 111, thereby limiting the maximum width and limiting the minimum switching resistance Rin and parasitic capacitance. CPin. In Figure 11(b), the signal acquisition mechanism feedback inverter 114 only needs to compensate for the process 1 eakage and increase the latch-to-missing of the latches, so a large-width transistor is not necessary. In addition, large-width transistors also increase Cfin, thus increasing the load capacitance of the output driver 113 in addition to the ClI 16 •. For these reasons, the pumping mechanism feedback inverter 114 is typically reduced to the minimum transistor allowed by the process. Width. Due to the above limitation, substantially only the transfer gate 112 and the output driver 113 can be optimized as basic components, although precise optimization requires complicated modularization and power. Simulation, some basic concepts can still be obtained for a device that optimizes the transfer delay or set time. For example, in Figure 11(b), the width of the transistor including the output driver 113 17 1316787 can be increased. The transfer delay of the latch is reduced until the parasitic capacitance CPd reaches the effective load capacitance exhibited by the capacitances Cfin and Cl. Increasing the transistor width reduces the drive resistance Rd and minimizes the transfer delay of the output driver 113. The step-by-step increase in the transistor width is Substantially, the delay is not reduced because the reduction in the drive resistance is achieved by proportionally increasing the parasitic capacitance Cpd of the transistor itself. Minimizing the transfer delay through the transfer gate U2 is more complicated because the transfer gate 112 does not generate a signal gain when only the load capacitance Cl 116 is coupled to the input inverter lu. The input inverter nl actually supplies a charging current to a parasitic capacitance including CPin, CPtgl, Cptg2, Cdin, and Cpf. Since cin is fixed, the input inverter lu drive resistance is fixed to Rin, and the input inverter 111 is provided. The parasitic load is fixed to the pin. Since the feedback inverter is a minimum device, the signal captures the parasitic capacitance of the feedback inverter (^ is fixed, and after the transmission described in the previous paragraph is optimized, Cdin is fixed. Increasing the width of the transistor in the transfer gate 112 will It will reduce the overall switching resistance of Rin + Rtg, but also increase the parasitic capacitance (^(4) and cPtg2. However, when the width of the device of the transfer gate 112 increases, the transfer delay of the transfer gate 112 will decrease until the overall parasitic capacitance CPtsl + CPtg2 The same amount of capacitance as presented by cdin, cPf and cPin is achieved. The optimization of the minimum transfer delay of the combined transfer gate 112 and the output driver 113 produces a minimum transfer delay optimized latch. Minimized time 18 1316787 * The sequence path is from 0/7埠 through the transfer gate 112, the output driver 113 to the load capacitance Cl Π6 seen at Q 。. The optimization of the latch set time is generally different from the optimization of the transfer delay because of the need to emphasize Different timing paths. For example, in the gate of Figure ,, the signal acquisition mechanism Π5 must be switched as quickly as possible. To achieve this, it is necessary to minimize the contact from 12 to Q and back to 12 Loop delay, which means limiting the tolerable load capacitance ClI 16. Reducing the loop delay from contact 12 to Q and back to 12 • reduces the input capacitance Cdin of the output driver 113, which means that the width of the driver 113 needs to be reduced. To a minimum, the settling time can be reduced but at the expense of the flash transfer delay. The capacitive load exhibited by the transfer gate 112 also needs to be minimized, while the transfer gate width is reduced to the parasitic capacitance CPtgl and (: ring 2 is close to being The reduced load of CdinK is presented. The minimum setting optimization of the combined transfer gate 112 and the output driver 113 provides a minimum set optimized latch. The optimized path is from the D input through the input inverter 111. The transmission gate 112, the output driver 113, and finally the feedback inverter 114 is returned to the signal through the signal. The input signal from the D埠 must be delivered through the path, and the signal acquisition function is completed, which must be performed by the signal. ^ and ^ stop the transfer gate 112 to isolate the signal capture mechanism 115. The basic structural modification of the latch of Fig. 11(a) can also be used to optimize the set time. A device that minimizes settling time involves shrinking the output drive 19 1316787 actuator 113 and minimizing the load capacitance Cl 116. A common device that limits the effect of a latched Cl 125 is to use the load capacitance Cl 125 to buffer the contact 14 as shown in FIG. (a) shows that the buffer contact 13 can reduce the delay from 12 to 13 and back to the entire loop of 12, but note that the transfer delay has been increased by the delay of the buffer 124. An additional device that reduces the set time The removal of the input inverting buffer 120 and the relying on the output of the previous stage are included to drive the latch data input D, as shown in Figure 12(b). The same buffering concept of Figure 12(a) can be used to coordinate the logical polarity of D to Q. Since the data transfer delay path has been reduced by an inverter transfer delay, and the set path involves the relative timing of the data and the clock path, the set time is substantially reduced by the reverser transfer delay of one of Figure 12(a). One possible disadvantage of releasing the input data inverter is that this method requires additional synthesis constraints and characteristics, taking into account the latch input impedance and the drive capability of the previous stage. The essence of the invention is to synthesize a design from a target library that has two identical functions but different ordering units for optimizing timing. A sequence unit involves a large family of cells that have the ability to store data status. Throughout this family are a group of latches and flip-flops, each of which can be used in the present invention as long as it can establish a sequence unit with different settings or transfer delay optimizations. Methods for optimizing CMOS latches and a D-type flip-flop have been discussed in detail, however, these methods can be applied to other types of flip-flops in the same way as 20 1316787. Although the present invention utilizes a D-type flip-flop, it is a common practice to add an external gate to convert a form of flip-flop to another form. For more information on the form of the flip-flop conversion, refer to Fundamentals of Logic. Design by Charles H. Roth, West Publishing Company, 1979, p 233. For example, a D-type flip-flop can be replaced with a set/reset flip-flop as shown in FIG. 13 to cut the original D logical path into a positive and negative logical path for setting (S) and resetting ( R) Input can be easily achieved. In a similar manner to the D-type flip-flop, the set/reset flip-flop in FIG. 14 includes two latches 141, 142 connected by a clock buffer network 143. In addition, similar to the D-type latch, each RS latch is composed of an input buffer reverse phase, a clock isolation mechanism 151 and a signal capture mechanism 152, as shown in FIG. The D-type latch uses a transfer gate as a clock isolation mechanism, wherein the RS latch uses a NAND function to cut the data paths S and R into a signal capture mechanism 152. Considering the similarity between the D-type latch and the RS latch and the D-type flip-flop and the set/reset flip-flop, the above-described optimization of the settling time and transmission is achieved by modifying the clock buffer network and simplifying the flash. The delay method can also be used to set/reset the design of the flip-flop. After the setting/reset flip-flop of a clock transfer optimization and the setting/reset of the set optimization are completed, the synthesis target library can be added, and the image of the synthesis target library is used in the present invention. Show the method to implement. 21 1316787 • The critical path timing begins with setting/resetting the flip-flop 161 to the Q/call transfer delay, as shown by the complementary path P1 and the dirty path. The path timing continues through the combinational logic of the path logic circuit 163. Critical Path Timing It is necessary to add the set time of the set/reset flip 162, which is represented by the path timings P2 and C. Figure 16 illustrates an embodiment of the present invention. The flip-flop 161 is optimized for fast clock to Q/3 transfer, and the flip-flop 162 is set for the fast set/reset input to the clock signal CU. Jiahua. The circuit is modified in accordance with today's technology, in which each of the same function flip-flops has the same timing optimization. Figure 17 depicts a critical path sequence for a non-synthesis design flow. The path timing includes a clock logic unit optimized for the transfer delay and a set: time-optimized clock logic circuit single-core-clock logic Circuit = Element 171 is specially designed to optimize its clock to

The transfer delay, (4) two-clock logic circuit unit 172 optimizes its In_2 to clock (In^t〇-ακ) set time. Those skilled in the art can _(4) to infer that a pulse circuit unit can have more input and/or more output. In this case, each clock to Out-i transmits a delay and every In" The time to clock setting must be optimized separately. Each clock circuit unit optimizes only a portion, such as pass delay or set _ both, to eliminate the compromises made between the two timings in the prior art. The critical path timing is determined by the clock logic 22 1316787 channel unit 1, 171 clock to Out_l transfer delay, path logic circuit 173 transfer delay, and In_2 to clock set time. It is apparent that the optimized clock logic unit in accordance with a particular embodiment shortens the critical path timing and indirectly accelerates the operation of the circuit. Referring to Fig. 18, there is shown a flow chart of one of the synthetic design flows of the present invention. The operation begins in step 181, wherein a first clock logic circuit unit is designed to have an optimized clock to Out_l (Clock-to-Out_l) transfer delay. This optimization can be achieved by using a simplified gate element or adjusting the clock network delay at the flip-flop layer. In step 182, a second clock logic circuit unit is designed to have an optimized In_2 to clock (In_2-t〇-CLK) set time, the optimization being as described above for the first clock logic circuit The optimization of the unit is achieved. Step 183 configures the first clock logic circuit unit before a path logic circuit. Similarly, step 184 configures the second clock logic circuit unit after the path logic circuit ® . The critical timing path is determined by the clock of the first clock logic unit to the Out_l transfer delay, the transfer delay of the path logic circuit, and the In_2 to clock set time of the second clock logic circuit unit. In this case, the present invention will improve design speed and power consumption by better timing optimization of critical paths, and the present invention can be implemented by today's logic circuit synthesis techniques. Although some of the above specific embodiments are designed to reduce the critical path timing from the design of an optimized 23 1316787 delivery delay flip-flop with another optimized set-time flip-flop, including its spirit and Other ways of the field can also be used to implement the invention. For example, other clock logic circuit units can be optimized to reduce critical path timing. In this regard, the specific embodiments illustrated in Figures 6 and 8 are only used to help present the present invention using a flip-flop or time. The related advantages achieved by the pulse logic circuit are not intended to limit the invention. Obviously, many modifications and differences may be made to the invention in light of the above description. It is therefore to be understood that within the scope of the appended claims, the invention may be The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the claims of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following claims. Within the scope. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram of a critical path flow with two standard flip-flops in a synthetic design flow; Figure 2(a) is a symbolic representation of a typical latch; Figure 2(b) is a transistor A typical latch diagram is shown; Figure 3 is a schematic diagram of the timing relationship of a typical latch; Figure 4 is a schematic diagram of a typical flip-flop unit 24 • 1316787 comprising two latches and a clock network, Figure 5 is a typical Schematic diagram of the timing relationship of the flip-flop; FIG. 6 is a schematic diagram of a critical path timing of a flip-flop having a transfer delay optimization and a set time optimization in the synthetic design flow, and FIG. 7 is a schematic diagram of the present invention. Schematic diagram of the timing relationship in the critical timing path; Figure 8 is a schematic diagram of the forward and reverse clocks and propagation delays optimized by modifying the clock buffer network; Figure 9(a) to Figure 9(c) are a buffered inverse A schematic diagram of a circuit module of a transmitter, the buffer inverter being a basic latch component. Figure 10 (a) to (c) is a circuit module of a transfer gate, the transfer gate is a basic latch component; Figure 11 is a simplified circuit module of a typical D-type latch; Figure 12 (a) and Figure 12(b) is another structure of a typical D-type latch, which is the best for data setting time; Figure 13 shows the relationship between the D-type flip-flop and the setting/reset flip-flop function; A typical set/reset flip-flop that includes two RS latches and a clock buffer flip-flop is shown; Figure 15 shows a typical RS that combines the input buffer/clock isolation phase with the output buffer/signal capture phase. Latch; 25 1316787 Figure 16 illustrates one of the critical path timings of a set/reset flip-flop with a set delay optimization and a set time optimization of the transfer delay optimization in the synthetic design flow; 17 is a schematic diagram of a critical path timing of a clock logic unit with a transfer delay optimization in a synthetic design flow and a time-optimized clock logic unit; and FIG. 18 is a synthetic design flow of the present invention. flow chart. • [Main component symbol description] Lu / "埠 A input contact Cdin capacitor Cf in capacitor Cil capacitor Ci2p capacitor Ci2n capacitor Cl capacitor CpI capacitor Cp2a capacitor Cp2b capacitor CPd parasitic capacitor Cpf capacitor 26 1316787 ·

Cpin capacitor

Cptgl capacitor Cptg2 capacitor CLK clock D poor input 11 contact 12 contact • 13 contact

In_l input 埠 In_2 input 埠 Out_l output 埠 Out_2 output 埠 P1 transfer path P2 transfer path ® ρ 互补 Complementary transfer path with P1 传递 Complementary transfer path with P2 Q 埠 δ 埠 S Set 埠 R Reset 埠

Rd resistance 27 1316787 ·

Rf resistance

Rin resistor Rni resistor Rn2 resistor RP1 resistor RP2 resistor Rtg resistor Wn/Ln aspect ratio Wp/Lp aspect ratio Y output contact tcQ transfer delay tcQi clock-to-Q (C1 ock-to-Q) transfer delay tcQ2 clock The transfer delay tDC to Q (C1 ock_to-Q) sets the time tDci D to the set time of the clock (D_to-Clock) tDC2 D to the set time of the clock (D-to-Clock) tpathlogic the transfer delay of the path logic circuit 13 11 Standard flip-flops 1 12 Standard flip-flops 2 13 Path logic 20 Gate 28 1316787 21 Buffer reverser 22 Transfer gate 23 Signal capture mechanism 41 Latch 1 42 Latch 2 43 Clock network 61 has a fast clock to Q-delay (Clock-to-Q) flip-flop I 62 flip-flop with fast D to clock-set (D-to-Clock) 63 path logic 81 latch 1 82 latch 2 83 clock network 90 positive Counter 92 Inverter ^ 93 P channel device 94 Switch 95 Switch 100 Transfer gate 102 Gate 103 Gate 104 Transfer gate switch 29 .1316787 105 Transfer gate switch 111 Input inverter 112 Transfer gate 113 Output driver 114 Capture mechanism feedback Transmitter 115 Signal Acquisition Mechanism 116 Load Capacitance • 120 Input Reverse Buffer 121 Transfer Gate 122 Buffer Inverter 123 Buffer Inverter 124 Buffer 125 Capacitor 126 Transfer Gate • 127 Buffer Inverter 128 Buffer Inverter 129 Buffer Inverter 141 RS Latch 142 RS Latch 151 Clock isolation mechanism 152 Signal acquisition mechanism 30 1316787 161 Setting/resetting flip-flop 162 Setting/resetting flip-flop 163 Path logic circuit 171 First clock logic circuit unit 172 Second clock logic circuit unit 173 Path The logic circuit 181 designs a first clock logic φ circuit unit 182 having an optimized transfer delay. The 182 circuit unit 182 is configured to have an optimized set time. The second clock logic circuit unit 183 configures the first clock logic circuit unit. Before the path logic circuit 184 configures the second clock logic circuit unit after the path logic circuit 31

Claims (1)

1316787 Case No. 095112951 Revised on June 19, 1998, this year is the year/month, and the date is revised. The scope of application for patent:--- 1. A data processing system, the data processing system includes: a path logic circuit; a clock logic circuit unit, the first clock logic circuit unit is coupled to the path logic circuit, and an output of the first clock logic circuit unit is transmitted to the path logic circuit to process the first clock logic circuit An output of the unit, wherein the first clock logic circuit unit optimizes a transfer delay, wherein the optimizing is to shorten a delay time of the first clock logic circuit unit; and a second clock logic circuit a second clock logic circuit unit having the same logic circuit function as the first clock logic circuit unit and coupled to the path logic circuit for receiving and processing an output of the path logic circuit, wherein the second clock The logic circuit unit optimizes the set time, wherein the optimization is to shorten the set time of the second clock logic circuit unit. 2. The data processing system of claim 1, wherein a transfer delay of the first clock logic unit, a transfer delay of the path logic circuit, and a set time of the second clock logic unit determine a critical path Timing. 3. The data processing system of claim 1, wherein the first clock logic circuit unit shortens the transfer delay by simplifying the latch in the first clock logic unit. 4. The data processing system of claim 1, wherein the first clock logic unit shortens the transfer delay by adjusting a clock network. 5. The data processing system of claim 1, wherein the second clock logic unit shortens the set time by simplifying a latch in the second clock logic circuit unit. 6. The data processing system of claim 1, wherein the second clock logic unit shortens the set time by adjusting a clock network. 7. The data processing system of claim 1, wherein the transfer delay of the first clock logic unit is a time required to stabilize an input data to generate an output in a phase transition of a clock. 8. The data processing system of claim 1, wherein the set time of the second clock logic unit is a time required for an input data to be stored in a stable logic state. 9. A data processing system, comprising: a path logic circuit; and a clock logic circuit unit coupled to the path logic circuit, and an output of the clock logic circuit unit is sent to the path logic The circuit processes the output of the clock logic circuit unit, 33 1316787, wherein the clock logic circuit unit optimizes the transfer delay, wherein the optimization is to shorten the delay time of the clock logic circuit unit. 10. The data processing system of claim 9, wherein the shortening of the transfer delay of the clock logic circuit unit minimizes critical path timing. 11. The data processing system of claim 9, wherein the clock logic circuit unit shortens the transfer delay by simplifying the flash in the clock logic unit. 12. The data processing system of claim 9, wherein the clock logic unit shortens the transfer delay by adjusting a clock network. 13. The data processing system of claim 9, wherein the propagation delay of the clock logic unit is a time required to stabilize an input data to generate an output in a phase transition of a clock. A data processing system comprising: a path logic circuit; and a clock logic circuit unit coupled to the path logic circuit for receiving and processing an output of the path logic circuit, wherein the clock The logic circuit unit optimizes the set time, wherein the optimization is to shorten the time of the clock logic circuit unit. 15. According to the data processing system of claim 14, the setting time of the clock logic unit in 34 1316787 is optimized to shorten the critical path timing. 16. The data processing system of claim 14, wherein the clock logic circuit unit shortens the set time by simplifying the latch in the clock logic circuit unit. 17. The data processing system of claim 14, wherein the clock logic unit shortens the set time by adjusting a clock network. 18. The data processing system of claim 14, wherein the set time of the clock logic unit is a time required for an input data to be stored in a stable logic state. 19. A method of optimizing critical path timing, the method comprising: providing a first clock logic circuit unit having an optimized transfer delay, wherein the optimizing is to shorten the first clock logic circuit unit a delay time of the ®; providing a second clock logic unit with an optimized set time, wherein the optimizing is to shorten the set time of the second clock logic unit; coupling the first clock a logic circuit unit to a path logic circuit, and transmitting an output of the first clock logic circuit unit to the path logic circuit to process an output of the first clock logic circuit unit; and 35 1316787 to lightly connect the first clock The logic circuit sings it to the path logic circuit and processes the output of the path logic circuit. The second clock logic 70 has the same logic circuit function as the first clock logic circuit unit. 20. The method of optimizing critical path timing according to item 19 of the scope of the invention of the invention, wherein the transfer delay of the first-clock logic circuit unit, the transfer delay of the logic circuit of the circuit I, and the second clock logic circuit unit The set time is determined - the eritieal path timing. 21. According to the method of optimizing the critical path timing of claim 19 of the patent scope, the delivery delay of the first-permanent circuit unit is stabilized by the input data to generate a The time required for the output. 22. The method of optimizing the surface path timing of claim 19 of the patent application, wherein the set time of the second clock logic unit is - the time required for the input material to be stored into a stable logic state. 23. The method according to claim 19, wherein the designing the first clock logic unit having an optimized transfer delay comprises simplifying a latch in the first-clock logic circuit unit . 24. The method according to claim 19, wherein the designing the first of the optimized transfer delays includes the adjustment of a clock network. 25. The method of optimizing critical path timing according to claim 19, wherein the designing the second clock logic circuit unit with optimized settling time comprises simplifying in the second clock logic circuit unit latch. 26. The method of optimizing the critical path sequence according to claim 19 of the patent application wherein the second clock logic circuit unit having the optimized set time is designed to include a watch-clock network. One 37, 1316787 Case No. 095112951 November 27, 2007 _ Revision Page w Year "Fig Correction Replacement Page CLK pass delay 1 Set time one -| D Q 85 .1316787 9 details "month q day correction replacement page I-----------------------------1 Figure 10 1316787 τ? Year of the month η day correction replacement page Figure 11a Figure lib 1316787* 4 % year q month 曰 correction replacement page 120 ^ 121 E Figure 12a 126 QQ Figure 13 1316787 VII. Designated representative circle: (1) The representative representative of the case is the picture (18). (2) A brief description of the component symbols of the representative figure: =-pass-time optimized H-channel logic circuit unit-second clock logic circuit unit configuration brother-time logic circuit unit is configured at 181 182 183 184 second time Transfer circuit 8. If there is a chemical formula in this case, please reveal the most basic chemical formula.