TWI316754B - Image sensor fabrication method and structure - Google Patents

Image sensor fabrication method and structure Download PDF

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TWI316754B
TWI316754B TW93107173A TW93107173A TWI316754B TW I316754 B TWI316754 B TW I316754B TW 93107173 A TW93107173 A TW 93107173A TW 93107173 A TW93107173 A TW 93107173A TW I316754 B TWI316754 B TW I316754B
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layer
height
substrate
color
flat
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TW93107173A
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TW200532904A (en
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Chinchen Kuo
Chihkung Chang
Hungjen Hsu
Futien Weng
Te Fu Tseng
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Taiwan Semiconductor Mfg
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1316754 五、發明說明(1) 【發明所屬之技術領域】 本發明與一種半導體元件有關’特別是與一種固態彩色淚 •光片有關。 α 【先前技術】 本發明為2003年6日6日申請之美國專利申請案1〇/456, 759 之續案。 彩色濾光片可適用於彩色影像感測器上,曾被描述於美國 專利案號61 71 885,6395576,6274 91 7,6482669 和 、 6495813中,上述均為本案之參考資料。 一彩色影像感測器之結構典型上可為一感光耦合元件 (Charge-Coupled Device)或是為一互補式金屬氧化物 半導體(CMOS )光二極體陣列結構。此結構包括一光敏 層’此光敏層位於被圖案化成彩色光濾波器陣列之一或多 層之下,而位於一形成有微鏡元件之表面層陣列之上。在 某些傳統架構下,在依影像感測器中使用四個相鄰畫素形 成一彩色畫素’此四個相鄰晝素中之每一個被一個不同顏 色之濾光片所覆蓋,其中濾光片之顏色是是選自紅、藍和 兩個綠色之畫素,從而每一單色晝素僅能暴露出此三種基 本顏色中之一個,並藉由此三種顏色之簡單幾何加減,而 能呈現出全彩畫素。 第1A圖和第1B圖顯示出一具有條型缺陷(strip-defect ) 之彩色濾光片。這條塑缺陷之發生原因是因為其中一彩色 阻層(color resist layer )之厚度大於或小於一正常1316754 V. DESCRIPTION OF THE INVENTION (1) Field of the Invention The present invention relates to a semiconductor element, particularly to a solid color tear film. ??? [Prior Art] The present invention is a continuation of U.S. Patent Application Serial No. 1/456,759, filed on Jan. 6, 2003. Color filters are suitable for use in color image sensors and have been described in U.S. Patent Nos. 61,71,885, 6,395,576, 6,,,,,,,,,,,,,,,,,,, The structure of a color image sensor can be typically a Charge-Coupled Device or a Complementary Metal Oxide Semiconductor (CMOS) photodiode array structure. The structure includes a photosensitive layer which is patterned under one or more layers of the color optical filter array and over an array of surface layers on which the micromirror elements are formed. In some conventional architectures, four adjacent pixels are used in the image sensor to form a color pixel. Each of the four adjacent pixels is covered by a filter of a different color, wherein The color of the filter is selected from red, blue and two green pixels, so that each monochromatic element can only expose one of the three basic colors, and the simple geometric addition and subtraction of the three colors. It can present a full-color picture. Figs. 1A and 1B show a color filter having a strip-defect. This plastic defect occurs because the thickness of one of the color resist layers is greater or less than a normal thickness.

第7頁 1316754Page 7 1316754

五、發明說明(2) ΐ厚,條型缺陷之發生是因為藍、綠彩色阻層 =又不同。感測器包括有複數條刻畫線(scribe 在;=陣列中’複數個濾光片區域由著些刻畫線 ί=眉陷是形成在複數區域中,此缺陷不是 -正常度ΐ於一正就是綠色阻層之厚度小於 3=值,或不是不是綠色阻層之厚度大於一正常值,就 ^ ρ,層之厚度小於一正常值。相似的,在第1 β ®中, 此缺陷,因為紅、綠彩色阻層之厚度不同。圓τ 第ic圖是一傳統CM0S影像感測器(CIS ) ι〇〇之剖面結 圖。CMOS影像感測器丨〇〇有一具有複數刻晝線丨〇9之基板 ,其中刻畫線109係環繞至少一濾光片區域1〇1。此基 反107可以是一個絕緣基板,或是一位於一半導體基板上 H緣層’例如為二氧化石夕Si〇2。於一具有很多據光片區 域101之晶圓上,此複數個刻晝線1〇9形成垂直線格子。濾 先片區域101包括主動區丨02和具有接腳墊122於其中之接 腳墊區域108。主動區域1〇2有一光二極體形成於其中之η一 或P+i•之井區,例如為多晶碎層。主動區有一保護層 ^4,例如為氮化矽層SiN,保護層114具有複數底金屬區 3。保護層114有一第一平坦層1〇乜形成於其上,可為 一阻層,厚度高於晶圓表面之步階高度。第一平坦層丨 I,一於晶圓表面上之模子並可被平坦化,例如藉由在一 提尚之烘烤溫度下讓光阻形成黏狀流體,或是藉由一平坦 鑄件在加熱時將光阻表面壓平。於第一第一平坦層1〇“之V. INSTRUCTIONS (2) Thickness and strip defects occur because the blue and green color resist layers are different. The sensor includes a plurality of lines (the scribe is in the array; the plurality of filter areas are formed by some lines of ί=the eyebrows are formed in the complex area, and the defect is not - the normality is a true The thickness of the green resist layer is less than 3 = value, or if the thickness of the green resist layer is greater than a normal value, the thickness of the layer is less than a normal value. Similarly, in the first β ® , this defect is due to red The thickness of the green color resist layer is different. The circle τ is the cross-section of a conventional CMOS image sensor (CIS) ι〇〇. The CMOS image sensor has a complex engraved line 丨〇9 The substrate, wherein the scribe line 109 surrounds at least one of the filter regions 〇1. The base reflector 107 may be an insulating substrate or a H-edge layer on a semiconductor substrate, such as a dioxide dioxide 〇Si〇2 The plurality of engraved lines 1〇9 form a vertical line grid on a wafer having a plurality of light-receiving areas 101. The filter sheet area 101 includes an active area 丨02 and a pin having a pad 122 therein. Pad area 108. Active area 1〇2 has a photodiode formed therein The well region of η or P+i• is, for example, a polycrystalline layer. The active region has a protective layer 4, such as a tantalum nitride layer SiN, and the protective layer 114 has a plurality of bottom metal regions 3. The protective layer 114 has a first A flat layer 1 is formed thereon, which may be a resist layer having a thickness higher than a step height of the surface of the wafer. The first flat layer 丨I, a mold on the surface of the wafer, may be planarized, for example By forming the photoresist into a viscous fluid at a given baking temperature, or by flattening the surface of the photoresist while heating by a flat casting, the first first planar layer 1

1316754 五、發明說明(3) 上,形成有藍色、綠色和紅色之彩色阻層定名為丨丨1和 Π3。一第二平坦層1 〇4b是位於濾光片ill和113之上。一 -微鏡(microlens)層106形成於第二平坦層i〇4b之上。 -第二平坦層l〇4b之高度119相對於保護層114頂端約為4 5 微米。一約為丨· 5微米至2微米之額外高度118,約是於接 腳墊122之頂端和保護層114頂端間,因此總步接高度於 1 f 頂端和接腳墊122之頂端約為6微米至6. 5微米。 杉色濾光片之訊號誤差過大,CM〇s影像感測器之 θ文影響,造成良率損失高達15%至20%。例如,本申社索 Π明人玄曉得樣品之彩色訊號標準誤差為:藍色4 3. 93/0 ’率色為2· 84%和紅色為 於〇. 5。 巴馮L 68/,此形成一良率Cpk低 沈積製程和相關微鏡陣列之形成製程會夺響 Γ期時間’測試時間良率和最終成本是廣為I: 色请▲具有較少訊號誤差χ可增㊆良率之r 色濾先片製程方法存有需求。 運良羊之如 【發明内容】 一種半導體基板之M鋥太 少具有-濾、光片區至:包括這些步驟··提供-至 成一平坦層使得沈二接聊塾上以降低步接高度;形 度;和形成至少一_^層具有一近於平坦層高度之高 和色阻層於平坦層上。1316754 V. Inventive Note (3), the color resist layers formed with blue, green, and red are named 丨丨1 and Π3. A second flat layer 1 〇 4b is located above the filters ill and 113. A microlens layer 106 is formed over the second planar layer i〇4b. The height 119 of the second flat layer 104b is about 4 5 microns with respect to the top end of the protective layer 114. An additional height 118 of about 5 microns to 2 microns is about between the top end of the pad 122 and the top end of the protective layer 114, so the total step height is about 1 f and the top of the pad 122 is about 6 5微米。 Micron to 6. 5 microns. The signal error of the sap filter is too large, and the CM s image sensor has a θ effect, resulting in a yield loss of 15% to 20%. For example, the standard error of the color signal of the sample of the Shenxuan people is: blue 4 3. 93/0 ’ rate color is 2.84% and red is 〇. 5. Buffon L 68/, this formation of a good yield Cpk low deposition process and related micro-mirror array formation process will win the flood season 'test time yield and final cost is widely I: color please ▲ with less signal error There is a need for a r-color filter first-stage process method that can increase the yield of seven. Yunliang Yangzhi [Invention] The semiconductor substrate has too few M-filters, and the light-strip area to include: these steps provide a flat layer so that the second layer can be lowered to reduce the step height; And forming at least one layer having a height close to the height of the flat layer and a color resist layer on the flat layer.

第9頁 1316754Page 9 1316754

【實施方式】 2』〇屮3 ί6曰6::請之美國專利申請案1()/456,759如同於此 .提出被並行參考。 Ν於此 具體實施例之描述與相關夕阁+虛η。士# 是本案說明書描述之示被認為 較字眼,例如"較低"、"較上"、"水平"、"水平"、上比 ^^^ „t· Λ··'.„l ϊ $ :些比i應參考如說明書所述或如圖中所晝之位置已 =較佳之瞭解’這些相對性之字眼是以方便描述之 -同時並不要求所插述之裝置需位於-特 =位置上,於圖中’相同之參考數字代表相同。特 發明人決定出造成彩色信號誤差之一個主要原因是條 nm)。條型缺陷形成原因是因為彩色阻層 、(⑶lot· resist layer)厚度於畫素中或畫素間不平 造成,特別是存於藍色和綠色彩色阻層中,當從主動區上 看,這些不平均之彩色阻層會呈現出藍色和綠色條: 規則區域。 、土 4不 發明人亦決定出嚴重之前端圖案問題是造成條型缺陷之原 因。亦即,製程流程前端會於半導體之表面遺留下一不平 坦之表面,而此表面是用以形成彩色濾光片,此不平坦之 表面會對後續於其上沈積一平坦層造成影響。 發明人更決定出於基板上條型缺陷之步階高度越深,條塑[Embodiment] 2 〇屮 3 ί 6 曰 6:: Please refer to US Patent Application 1 () / 456, 759. The description of the specific embodiment is related to the eve + imaginary η. Shi # is the description of the description of this case is considered to be more words, such as "lower", "above","level","level",上比^^^ „t· Λ· ·'.„l ϊ $ : These ratios i should refer to the position as described in the specification or as shown in the figure. = The better understanding of the words 'These relatives are conveniently described' - and are not required to be inserted. The device needs to be located at the -special position, where the same reference numerals represent the same. One of the main reasons why the inventor decided to cause a color signal error was the strip nm). The reason for the formation of strip defects is that the thickness of the color resist layer and the ((3)lot·resist layer are caused by unevenness in the pixels or between the pixels, especially in the blue and green color resist layers, when viewed from the active area, these The uneven color barrier will present blue and green bars: the regular area. , soil 4 does not inventors also decided that the serious front-end pattern problem is the cause of the strip defect. That is, the front end of the process flow leaves an uneven surface on the surface of the semiconductor, and the surface is used to form a color filter, and the uneven surface affects subsequent deposition of a flat layer thereon. The inventor even decided that the deeper the step height of the strip-shaped defects on the substrate, the strip molding

第10頁 1316754 五、發明說明(5)Page 10 1316754 V. Description of invention (5)

缺陷會變得更嚴重。一第二原因是接腳墊之步階高度。另 一原因則包括了光阻之塗佈速度’越高之塗佈速度會增加 條型缺陷。然而’刻畫線之步階高度是條型缺陷之主要成 因’而接腳墊之步階高度則為條型缺陷之另一重要成因。 第2圖所示為一以具體實施例形成之彩色濾光片元件2 〇 〇之 剖面結構圖。元件200有一具有複數刻畫線(scribe lines ) 210之基板207,其中刻畫線210係環繞至少一濾光 片區域201。此基板207可以是一個絕緣基板,或是一位於 一半導體基板上之絕緣層’例如為二氧化矽s丨% ^於一具 有很多遽光片區域201之晶圓上,此複數個刻晝線2丨〇形成 垂直線格子。濾光片區域201包括主動區2〇2和具有接腳墊 222於其中之接腳墊區域208。主動區域2 〇2有一光二極體 形成於其中之η-或p+型之井區,例如為多晶矽層。主動區 202有一保護層214,例如為氮化矽層SiN ,保護層214具有 複數底金屬區203 °保護層214有一第一平坦層2〇4&形成 於其上,可為一阻層,厚度高於晶圓表面之步階高度。較 佳地,第一平坦層204a是由一具高敏感性和高穿透性之光 阻所形成’第一平坦層204a可為一於晶圓表面上之模子並 可被平坦化,例如藉由在一提高之烘烤溫度下讓光阻形 黏狀流體,或是藉由一平坦鑄件在加熱時將光阻表面壓 平。 於第一平坦層204a之上,形成有藍色、綠色和紅色之彩色 阻層(color resist layers)定名為211和213 ’其中紅v 阻層未展示於第2圖中,因為紅色、綠色和藍色阻層$列Defects can get worse. A second reason is the step height of the foot pad. Another reason is that the higher the coating speed of the photoresist, the higher the coating speed, the more the strip defect. However, the step height of the line is the main cause of the strip defect, and the step height of the pad is another important cause of the strip defect. Fig. 2 is a cross-sectional structural view showing a color filter element 2 〇 形成 formed by a specific embodiment. Element 200 has a substrate 207 having a plurality of scribe lines 210, wherein the scribe lines 210 surround at least one of the filter regions 201. The substrate 207 may be an insulating substrate or an insulating layer on a semiconductor substrate, such as cerium oxide, on a wafer having a plurality of illuminating sheet regions 201, and the plurality of scribe lines 2丨〇 forms a vertical line lattice. The filter region 201 includes an active region 2〇2 and a pad region 208 having a pad 222 therein. The active region 2 〇 2 has a well region of the η- or p+ type in which the photodiode is formed, for example, a polycrystalline germanium layer. The active region 202 has a protective layer 214, such as a tantalum nitride layer SiN, and the protective layer 214 has a plurality of bottom metal regions 203. The protective layer 214 has a first planar layer 2〇4& formed thereon, which may be a resist layer, thickness Higher than the step height of the wafer surface. Preferably, the first planar layer 204a is formed by a photoresist having high sensitivity and high transparency. The first planar layer 204a may be a mold on the surface of the wafer and may be planarized, for example, The photoresist surface is flattened by heating the photoresist in a raised baking temperature or by heating it with a flat casting. Above the first planar layer 204a, color resist layers formed with blue, green, and red are named 211 and 213 'where the red v resist layer is not shown in FIG. 2 because of red, green, and Blue resist layer $ column

$ 11頁 1316754 五、發明說明(6) 之關係’然而,一熟習該項技藝者應瞭解到當從上方看入 時,這些阻層是以群組之方式排列,其中四個綠色阻層元 件會排列成一鑽石形狀,而不是紅色阻層元件就是藍色阻 •層元件會排列於每一個鑽石形狀之中央。此相同元件之另 一區域圖形(未展示出)可呈現出僅具有綠色阻層和紅色 阻層元件。一第二平坦層204b是位於濾光片211和213之 上。一微鏡(microlens)層206形成於第二平坦層2〇4b之 上。 刻畫線21 0有一最初之步階高度Η,此步階高度η與積體電 路(IC )技術形式有關。例如’一 〇 · 6微米CMOS影像感測 器有一3.33微米之刻畫線步階高度Η,一 0.35微米之CMOS 影像感測器有一 4. 5 5微米之刻晝線步階高度η,一 〇 2 5微 米之C Μ 0 S影像感測裔有一比4. 5 5微米深之刻畫線步階高度 Η ’其他積體電路(1C)技術將形成不同於上述之相對°應 步階高度Η。 ~ 在一具體實施例中,沈積第一平坦層2 〇 4 a之步驟可調整成 至少包括使用阻層材料來部分填充刻晝線2丨〇,來降低刻 晝線210之南度至H2,其中在部分填充刻晝線21〇後之步階 咼度Η 2疋阻層表面和基板表面間之距離,利用使用阻層 料來至少部分填充刻晝線21 〇,不平坦之外觀可被降低戈 消除’可形成平坦之後續彩色阻層2U和213。 *〆 在第2圖中,阻層2 1 2僅形成於刻晝線2丨〇中,用以部分填 充刻晝線。在某些實施例中,此至少部分填充阻層之刻書 線,係被完全填滿至阻層頂端並位於基板表面下方,亦$ 1316754 五、發明說明(7) 遺留一正步階高度。在其餘之 全填充,此部分將進一步描述於 千’刻畫線21 0被完 -第3圖所示為可用於沈積第2圖中: .在某些實施例中,對於一個备1 2之光罩平面圖。 21 〇部分是透光的’而於非刻* & α ° 光罩於刻晝線 行曝光之後,阻層於刻晝線部分 疋不透光的。在進 而於非刻畫線部分保持可溶脑刀 不溶解,亦即變硬, 於某些實施例中,光罩是;=。 晝線部分造成正光阻情形變成 反的’亦即於非刻 畫線部分,此種光罩對於一個τ 了 ’讓阻層僅保持在刻 分是透光的,而於刻畫線部分β s ’於非刻畫線部 部分保持可溶解,而被移除。疋、光的’阻層於刻畫線 在某些實施例中’施加一化學、'六 、 畫線21 0部分之可溶解阻層。而 '谷解並移除位於非刻 電漿蝕刻製程,利用電漿場加迷之離他^施例中,使用乾 210部分之阻層以化學性溶解阻H =非刻畫線 21〇中。 增眾阻層212留於刻晝線 第4圖所示為彩色濾光片300之另一實施例’其中阻層η? 完全填充於刻畫線中’並繼續填充於基板之上至約與第一 平坦層204a等高。在第4圖中’阻層412被沈積於整個基 板’除了於最鄰近接腳墊222處。這造成一個較佳之平"坦 化’並且被認為可增進彩色阻層21 1和21 3擁有較平均之厚 度。 第5圖所示為第4圖中用來執行光阻沈積步驟以沈積阻層$11页1316754 V. Description of the invention (6) 'However, a person familiar with the art should understand that when viewed from above, these resist layers are arranged in groups, four of which are green resistive elements. They will be arranged in a diamond shape, instead of the red resistive element, which is a blue resist. The layer elements will be arranged in the center of each diamond shape. Another area pattern (not shown) of this same component can appear to have only a green resist layer and a red resist layer element. A second planar layer 204b is located on the filters 211 and 213. A microlens layer 206 is formed over the second planar layer 2〇4b. The characterization line 20 0 has an initial step height η which is related to the integrated circuit (IC) technology form. For example, the 'one-inch 6-micron CMOS image sensor has a step height Η of 3.33 micrometers, and a 0.35 micron CMOS image sensor has a step height η of 0.45 micrometers, a 〇2 5 micron C Μ 0 S image sensing has a ratio of 4. 5 5 microns deep drawn line step height Η 'Other integrated circuit (1C) technology will form a different step height Η from the above. In a specific embodiment, the step of depositing the first planar layer 2 〇 4 a may be adjusted to at least include partially filling the engraved line 2 使用 with a resist material to reduce the southness of the engraved line 210 to H 2 , Wherein the distance between the surface of the resist layer and the surface of the substrate after partially filling the engraved line 21〇, by using the resist material to at least partially fill the engraved line 21 〇, the uneven appearance can be reduced The geper elimination can form a flat subsequent color resist layer 2U and 213. * 〆 In Fig. 2, the resist layer 2 1 2 is formed only in the engraved line 2丨〇 to partially fill the engraved line. In some embodiments, the at least partially filled resist layer is completely filled to the top of the resist layer and below the surface of the substrate. Also, $1316754, the invention description (7) leaves a positive step height. In the rest of the full fill, this section will be further described in the thousands of scribe lines 21 0 is completed - Figure 3 is shown for deposition in Figure 2: In some embodiments, for a light of 1 2 Cover plan. 21 〇 part is light-transmitting' and after the non-engraving * & α ° mask is exposed to the engraved line, the resist layer is opaque to the engraved line. The soluble brain blade remains insoluble in the portion of the non-characterization line, i.e., hardens, and in some embodiments, the reticle is; The portion of the squall line causes the positive photoresist condition to become reversed, that is, in the non-characterization line portion, such a reticle for a τ 'allows the resist layer to remain only in the score is transparent, while the line portion β s ' The non-characterization line portion remains soluble and is removed. The resist layer of germanium and light is in the line of characterization. In some embodiments, a chemical, 'six, and a soluble resistive layer of the portion 210 of the line is applied. And 'gluten solution and remove the non-etching plasma etching process, using the plasma field to add to the fan's method, using the 210 layer of the resist layer to chemically dissolve the resistance H = non-characterization line 21〇. The additional resistance layer 212 is left on the engraved line. Figure 4 shows another embodiment of the color filter 300 in which the resist layer η? is completely filled in the scribe line and continues to be filled on the substrate to about A flat layer 204a is of equal height. In Fig. 4, the resist layer 412 is deposited over the entire substrate except at the nearest neighboring pad 222. This results in a better "canned' and is believed to enhance the average thickness of the color resist layers 21 1 and 21 3 . Figure 5 shows the step of performing a photoresist deposition step to deposit a resist layer in Figure 4.

13167541316754

時所使用光罩400之平面圖。若使用負光阻時,光罩 4j0除了於方形區域3〇2中為不透光外,其餘區域均為透 光’此不透光區域涵蓋接腳墊區2〇8和環繞之接腳墊222。 ,罩於區域302中為不透光,結果,當基板經由光罩4〇〇進 仃曝光,除了位於方形區域3〇2之阻層外,其餘部分之阻 層均被曝光,於曝光程序後,位於方形區域3〇2外之阻層 變成不可溶解,而位於方形區域3〇2内之可溶解阻層會被 移除’例如使用如上所述之化學溶解劑或是電漿乾蝕刻方 法’阻層4 1 2會被保留於刻畫線中。 ;ί二實施例中’光罩之圖案是整個相反的,此時係使用鲁 正光阻,因此僅接腳墊區被曝光,而此曝光部分之阻層變 成可/合解,而位於接腳墊區外之阻層部分,包括位於刻晝 線中之阻層,保持再不被溶解之狀態。 阻層21 2和412之材料可包括任何一種能量敏感性材料,此 材料可形成於一基板上,並於積體電路之製程中形成圖 案’阻層材料212可包括其中包含报多種原料之能量敏感 性(energy-sensitive)聚合物,對於一負光阻而言,於 . ,光後可從溶解性轉變成不溶解性,而對於一正光阻而、 吕,於曝光後則是從不溶解性轉變成溶解性。阻層材料經 常根據特定曝光源來進行定作,在某些實施例中,248nnj # 阻層材料是用於248nm之深紫外光(deep ultraviolet, DUV),而193nm阻層材料則是用於193nm之深紫外光,這僅 是些例子’其他阻層,包括uv、DUV、X射線和E射線阻層 亦可使用於本發明中。A plan view of the reticle 400 used. If a negative photoresist is used, the mask 4j0 is opaque except for the square area 3〇2, and the rest of the area is light transmissive. This opaque area covers the pad area 2〇8 and the surrounding pad. 222. The cover is opaque in the area 302. As a result, when the substrate is exposed through the mask 4, except for the resist layer located in the square area 3〇2, the remaining portions of the resist layer are exposed after the exposure process. The barrier layer outside the square area 3〇2 becomes insoluble, and the soluble barrier layer located in the square area 3〇2 is removed 'for example using the chemical solvent or plasma dry etching method as described above' The resist layer 4 1 2 will be retained in the line of characterization. In the second embodiment, the pattern of the reticle is the opposite. In this case, the Luzheng photoresist is used, so only the pad area is exposed, and the resist layer of the exposed portion becomes achievable/dissolvable, and is located at the pin. The resist layer portion outside the pad area includes a resist layer located in the engraved line to maintain a state in which it is not dissolved. The material of the resist layers 21 2 and 412 may include any energy sensitive material which may be formed on a substrate and form a pattern in the process of the integrated circuit. The resist material 212 may include energy including a plurality of materials. An energy-sensitive polymer, for a negative photoresist, can change from solubility to insolubility after light, but for a positive photoresist, it is never dissolved after exposure. Sex turns into solubility. The barrier material is often tailored to a particular exposure source. In some embodiments, the 248nnj # barrier material is for deep ultraviolet (DUV) at 248 nm, while the 193 nm barrier material is for 193 nm. Deep ultraviolet light, which is only an example of 'other resist layers, including uv, DUV, X-ray and E-ray resist layers can also be used in the present invention.

第14頁 1316754 五、發明說明(9) "一~ ------ mu中丄使用一製程’例如為餘刻製程,來對阻 層212或412進仃平坦化。纟某些實施例中,施加於于阻 212或412上並回蝕阻層212或412以平坦化阻層之 重複執行多次直到達到一意欲之平坦化結果,且於 = 中之步階高度可降低至一意欲之大小。 、$線 在某些實施例中,如第3圖所示之光罩被一次或多次重複 使用以於刻晝線中沈積光阻層,而後並使用如第5圖所示 之光罩於基板207之表面沈積阻層。 於沈積阻層412後’可使用一標準平坦化光罩(於圖中並 未展示出)在位於濾光片區域之主動區域2〇2上沈積光阻 層,以形成一平坦層204a。至少一彩色阻層21 1和21 3被形 成於基板之上’此基板至少包含有一濾光片區域,於此區 域中硬化(不溶解)阻層材料會遺留於刻晝線内,然後, 形成一第二平坦層204b ’和形成一微鏡層206。 一旦阻層41 2被沈積於刻晝線21 0内,阻層可永久被保存於 刻畫線中,於刻畫線中存在之阻層並不會妨礙後續之製程 操作,且不會妨礙元件之表現。當需要時,阻層412可被 選擇性之移除。Page 14 1316754 V. INSTRUCTIONS (9) "One~ ------ mu 丄 Use a process ′ for example, a remnant process to planarize the resist layer 212 or 412. In some embodiments, application to the resist 212 or 412 and etch back the resist layer 212 or 412 to repeat the planarization of the resist layer multiple times until an intended planarization result is achieved, and the step height in = Can be reduced to an intended size. Line in some embodiments, the reticle as shown in Figure 3 is reused one or more times to deposit a photoresist layer in the engraved line, and then use a reticle as shown in Figure 5 A resist layer is deposited on the surface of the substrate 207. After deposition of the resist layer 412, a photoresist layer can be deposited on the active region 2〇2 of the filter region using a standard planarization mask (not shown) to form a planar layer 204a. At least one color resist layer 21 1 and 21 3 is formed on the substrate. The substrate includes at least one filter region in which the hardened (insoluble) barrier material is left in the engraved line and then formed. A second planar layer 204b' and a micromirror layer 206 are formed. Once the resist layer 41 2 is deposited in the engraved line 21 0 , the resist layer can be permanently stored in the trace line, and the resist layer present in the trace line does not hinder the subsequent process operation and does not hinder the performance of the component. . The resist layer 412 can be selectively removed when needed.

在一實驗中,形成一〇. 35微米之CMOS影像感測器,於沈積 阻層41 2前,刻畫線之步階高度為4 . 5 5微米,在使用如第 五圖所示光罩沈積第一阻層後,步階高度,亦即從阻層頂 端至基板頂端之距離’降低至2. 6微米,約減少43%。在使 用相同光罩沈積第二阻層後’步階高度降低至〇. 6微米’ 此代表步階高度約減少8,此實驗顯示良率’ Cpk之計In one experiment, a 35 μm CMOS image sensor was formed. Before the deposition of the resist layer 41 2 , the step height of the line was plotted to be 4.55 μm, and the photomask deposition as shown in Fig. 5 was used. After the first resist layer, the step height, that is, the distance from the top of the resist layer to the top of the substrate is reduced to 2. 6 microns, which is reduced by about 43%. After depositing the second resist layer with the same mask, the step height is reduced to 〇. 6 μm. This represents a step height reduction of about 8, and this experiment shows the yield ‘ Cpk

第15頁 1316754 五、發明說明(ίο) 算’大大增進。表一提供有關非平均色彩之結果’於表一 中’001Α光罩為一傳統光罩,用以於主動區2〇2上形成一 平坦層204a °〇〇lB為如第5圖所示之光罩。因此,標號為 ."1X001A光罩"之行所示為一傳統製程,平均值和標準差為 彩色濾光片之訊號誤差。 L 一 P •顔色P IX 001 Α 女 t罩β 1X001B光軍並行 使用001 A光軍p 2X 001B光罩 使用00 1 A今 並行 卜軍β 平均β 樺準 差^ 平均ρ 檫準 差ρ 平均p 棵準 盖P 藍P 含.49%·、 3.93%., -Ci. ο δ .1 1.16%, 0.93%, 0.84%, 4.38%, 0.53%, 1.96, .綠P 6.45%., 】.δ 4 % .1 0.12., X, X, X, h4.13%.. ύ.45%. 2.5, 紅P i, 6 S % ,ι 0.43., X, Γ χ. Γ X-, 4.34%, Γ〇.51%, Γ 2.07, 於表一中,標號為"1X001B光罩並行使用οοΐΑ光罩"之行所 示之製程,其中如第5圖所示之ooiB光罩係當於主動區2〇2 上形成一平坦層204a後,用來於刻畫線中沈積一層阻層, 以部分填充此刻晝線。標號為"2X0 01B光罩並行使用〇〇1 a 光罩"之行所示之製程,其中如第5圖所示之〇〇1B光罩係當 於主動區202上形成一平坦層2〇4a後,用來於刻晝線中沈 積兩層阻層’以部分填充此刻晝線。如表所示,一Cpk值 為0. 5之良率約為85%,一Cpk值為1. 9之良率近於1〇〇%。 因此’在形成彩色阻層211和213前,利用阻層部分或完全 填充刻晝線,可形成一較平坦之表面,以增進後續形成彩 色濾、光片層之平均度。 雖然,以使用一例子說明使用兩層阻層來作沈積,然而端 視刻畫線之深度,任何數目之阻層沈積均可被使用。Page 15 1316754 V. Description of invention (ίο) The calculation is greatly enhanced. Table 1 provides the results of the non-average color. In Table 1, the '001' mask is a conventional mask for forming a flat layer 204a on the active area 2〇2, as shown in Figure 5. Photomask. Therefore, the line labeled ."1X001A reticle" is shown as a conventional process, with the mean and standard deviation being the signal error of the color filter. L a P • Color P IX 001 Α Female t hood β 1X001B light army parallel use 001 A light army p 2X 001B reticle using 00 1 A present parallel army β average β birch quasi ^ average ρ 檫 standard deviation ρ average p The green cover P blue P contains .49%·, 3.93%., -Ci. ο δ .1 1.16%, 0.93%, 0.84%, 4.38%, 0.53%, 1.96, . Green P 6.45%., 】.δ 4 % .1 0.12., X, X, X, h4.13%.. ύ.45%. 2.5, Red P i, 6 S % , ι 0.43., X, Γ χ. Γ X-, 4.34%, Γ〇.51%, Γ 2.07, in Table 1, the process indicated by the line of "1X001B reticle using οοΐΑ光罩", where the ooiB reticle as shown in Figure 5 is active After forming a flat layer 204a on the region 2〇2, a resist layer is deposited on the patterned line to partially fill the inscribed line. The process is as follows: <2X0 01B reticle is used in parallel with the process shown in the 〇〇1 a reticle", wherein the 〇〇1B reticle as shown in Fig. 5 forms a flat layer 2 on the active region 202. After 〇4a, it is used to deposit two layers of resist layer in the engraved line to partially fill the inscribed line. As shown in the table, a Cpk value of 0.5 is about 85%, and a Cpk value of 1.9 is close to 1%. Therefore, before the color resist layers 211 and 213 are formed, a relatively flat surface can be formed by partially or completely filling the engraved layer with a resist layer to enhance the subsequent formation of the color filter and the average of the photo sheet. Although two layers of resistive layers are used for deposition using an example, the depth of the lines can be traced and any number of resist layer deposits can be used.

第16頁 !316754 -- —__ 五、發明說明(11) 第9圖所示為另一具體實施例之剖面圖,其中接腳墊222之 步階高度被降低,除此之外刻畫線之步階高度亦被降低, ,程cis之方法顯示於第6_9圖。 .百先參閱第6圖,製程CIS以形成一絕緣層於基板207上開 始’沈積並摻雜一半導體(如多晶矽)層205,接著沈積 一保護層214之底部,並沈積頂金屬層203和接腳墊222, 材料例如為銅/紹。然後沈積保護層2 1 4之頂端,同時餘刻 保護層214以暴露出接腳墊222。接腳墊222頂端和保護層 2 14頂端間之步階高度2丨8約為丨.5微米至2微米,如上述所 強調’當第一平坦層2〇4a和第二平坦層204b被加入時,若 無任何措施來降低此步階高度,則此步階高度會增加到6 微米至6 · 5微米間。 如同第6圖所示,一加進之步驟包括在接腳墊222之頂端沈 積一後保護接腳部分(post_passivati〇n pad p〇rti〇n) 224,用以形成接腳墊結構,包括接腳墊222和後保護接腳 部分2 24,此結構之高度高於接腳墊,而步階高度小於接 腳墊。其中形成後保護接腳部分224之材料與接腳塾222之 材料相同,可使用如一濺鍍製程、一微影製程或光阻蝕刻 製程形成。後保護接腳部分2 24之厚度與需被降低或移除 之步階高度攸關’約為1. 5微米至6微米。 ”Page 16! 316754 --___ V. DESCRIPTION OF THE INVENTION (11) FIG. 9 is a cross-sectional view showing another embodiment in which the step height of the pad 222 is lowered, and the line is drawn. The step height is also reduced, and the method of cis is shown in Figure 6_9. Referring to FIG. 6, the process CIS begins to form an insulating layer on the substrate 207 to begin to deposit and dope a semiconductor (eg, polysilicon) layer 205, then deposit a bottom of a protective layer 214, and deposit a top metal layer 203 and The pad 222 is made of copper/shoe. The top of the protective layer 2 14 is then deposited while the protective layer 214 is left to expose the pads 222. The step height 2丨8 between the top end of the pad 222 and the top end of the protective layer 2 14 is about 微米5 μm to 2 μm, as emphasized above, when the first flat layer 2〇4a and the second flat layer 204b are joined. If there is no measure to reduce the height of this step, the step height will increase to between 6 microns and 6.5 microns. As shown in FIG. 6, an additional step includes depositing a post-protection pin portion (post_passivati〇n pad p〇rti〇n) 224 on top of the pad 222 for forming a pad structure, including The foot pad 222 and the rear protection pin portion 2 24 have a height higher than the foot pad and the step height is smaller than the foot pad. The material forming the rear protective pin portion 224 is the same as the material of the pin 222, and can be formed using, for example, a sputtering process, a lithography process, or a photoresist etch process. 5微米至6微米。 The thickness of the post-protection pin portion 2 24 and the height of the step to be reduced or removed is about 1. 5 microns to 6 microns. ”

第7圖所示為第6圖於沈積第一平坦層2〇4a後之結構,較佳 地,第一平坦層20 4a具高敏感型與高穿透性。在某些具體 實施例中,第一平坦層2〇切之材料’如光阻,如上^述會 填充刻畫線210,同時請參閱第4圖之圖號412所指。較佳B 1316754Fig. 7 is a view showing the structure of Fig. 6 after depositing the first flat layer 2? 4a. Preferably, the first flat layer 20 4a is highly sensitive and highly penetrating. In some embodiments, the material of the first planar layer 2, such as a photoresist, is filled with the scribe line 210 as described above, and reference is made to Figure 412 of Figure 4. Preferred B 1316754

直到切割步驟(dicing 僅後保護接腳部分2 2 4 五、發明說明(12) 地’此材料41 2會保留在刻畫線中 ),在第7圖所示之具體實施例中 被曝光。 較佳地,後保護接腳部分224是(精確地或)趨近 平坦層204a之頂端,造成在後保護接腳部分224盥坌:: 坦層204a間趨近於〇步階高度。一些良率之增進;^ :二 小之後保護接腳部分224高度達成,形成降低但非〇之^ 面度’然而’將後保護接腳部分224之高度趨近於第一 坦層204a之頂端,可讓良率増進更多。於第7圖中,:: 護接腳部分224之高度是些微高於第一平坦層2〇“之^保 端,最終具有一平坦之外觀之結構展示於第7圖中, 降低在彩色光阻層211和213間之條型缺陷有报大之幫; 在其他之具體實施例中(於圖中並未展示出),提供一;5 保護接腳部分224,且位於主動區202上之第一平坦^2後 相對於接腳部分224具有一趨近於〇之步階高度,&而,= 畫線210中並未填充平坦層材料412。雖然,如此之具體^ 實施例相對於之前展示於第1C圖之結構可提供一增進之 率,然而,將平坦層材料41 2如第7圖所示填充於^畫線又 210中可獲得一較佳之良率增進。 第8圖顯示形成彩色濾光片層21ι和213和第二平坦層2〇^ 之步驟。形成第二平坦層層2〇4b之材料與第一平坦層2〇4 之材料相同,並第二平坦層層204b會完全覆蓋彩色阻層a 211和213。在一較佳具體實施例中,第二平坦層2〇仆亦覆 蓋刻晝線’因此僅暴露出後保護接腳部分224,最終之钟Until the cutting step (dicing only the rear protection pin portion 2 2 4 5, the invention description (12) ground] the material 41 2 will remain in the scribe line), it is exposed in the specific embodiment shown in FIG. Preferably, the rear protective pin portion 224 is (accurately) or toward the top end of the flat layer 204a, causing the rear protective pin portion 224:: between the layers 204a to approach the step height. Some yield enhancements; ^: The protective pin portion 224 is reached after two small heights, forming a reduced but non-defective 'degree of 'but' to bring the height of the rear protective pin portion 224 closer to the top of the first layer 204a Can make yields more. In Fig. 7, the height of the guard leg portion 224 is slightly higher than that of the first flat layer 2, and finally has a flat appearance. The structure shown in Fig. 7 is lowered in the colored light. The strip type defect between the resist layers 211 and 213 has a large contribution; in other specific embodiments (not shown in the figure), a protection pin portion 224 is provided and located on the active area 202. The first flat surface 2 has a step height closer to the crucible relative to the pin portion 224, and the flat layer material 412 is not filled in the drawn line 210. Although such a specific embodiment is relative to The structure previously shown in Figure 1C provides a rate of improvement, however, a better yield enhancement can be obtained by filling the flat layer material 41 2 as shown in Figure 7 in the line 210. Figure 8 shows The steps of forming the color filter layers 21 and 213 and the second planar layer 2〇. The material forming the second planar layer 2〇4b is the same as the material of the first planar layer 2〇4, and the second planar layer 204b The color resist layers a 211 and 213 are completely covered. In a preferred embodiment, the second flat layer 2 is also covered. Cover the engraved ’ line so that only the rear protection pin portion 224 is exposed, the final clock

第18頁 1316754 五、發明說明(13) 構如第8圖所示,其具有一平坦之頂表面,對於 鏡206内之條型缺陷有很大之幫助。於第二平挺層 _頂端和後保護接腳部分224間之步階高疮s由μ J没疋實質小於宾麼 • Π8和高度119之總和’其中高度119 ’如第κ 示: 第二平坦層104b頂端和接腳墊122間之古疮 、 馬 加上(1 · 5微米至2微米)之高度,j:力门她又从、勺為4,5微米 6.5微米,如第所示。门度、加總後約為6微米至 第9圖展示形成微鏡206後之結構圖。於 一熱量回流微鏡材料。 兄後’施加 =1。〇圖所示為根據另一實施例形成之感光耦合元件剖面 =本發明已以一較佳實施例揭露如上,然其並 疋本發明’任何熟習此技藝者,纟不脫離本發明:限 範圍内,當可作各種之更動與潤飾,因此本發c 圍當視後附之申請專利範圍所界定者為準。 呆瘦範Page 18 1316754 V. DESCRIPTION OF THE INVENTION (13) As shown in Fig. 8, it has a flat top surface which is of great help to the strip defects in the mirror 206. The step between the second flat layer _ top and the rear protective pin portion 224 is higher than the sum of the μ • 8 and the height 119 'the height 119 ' as shown in the first κ: second The height of the flat layer 104b between the top of the flat layer 104b and the foot pad 122, the height of the horse plus (1 · 5 μm to 2 μm), j: the force door she again, the spoon is 4, 5 microns 6.5 microns, as shown . The gates, after summing up to about 6 microns, are shown in Figure 9 after forming the micromirrors 206. Reflowing the micromirror material with a heat. After the brother's application =1. The present invention is shown in a cross-section of a photosensitive coupling element formed according to another embodiment. The present invention has been disclosed in a preferred embodiment as described above, and the present invention is not limited to the invention. Within the scope of this patent, the scope of the patent application is subject to the definition of the patent application. Stay thin

第19頁 1316754Page 19 1316754

【圖式簡單說明】 為讓本發明之上 懂,下文特舉一 明如下: J和其他目的、特徵、和優點能更明顯易 較佳實施例,並配合所附圖式,作詳細說 具有條型缺陷主動 第1A圖和第1B圖所示為複數彩色濾光片 區之平面圖; =ic圖所示為一傳統影像感測器之剖面結構圖 主動區之 第2圖所示為一以具體實施例形成之影像 刮面結構圖; ^3圖所示為第2圖位於基板上之光罩平面圖; 第4圖所示為一於製程中使用不同光罩形成之影像感測器 主動區之剖面結構圖; 峨 第5圖所示為第4圖用來沈積光阻於彩色影像感測器上所 用光罩之平面圖; 第6圖至第9圖所示為形成彩色影像感測器之另一具體實施 例:以及 第1 0圖所示為根據另一實施例形成感光耦合元件之概略 圖。 【元件代表符號簡單說明】 100 CMOS影像感測器(CIS ) 101和201濾光片區域 102和202主動區 103和203底金屬區 10 4a和204a第一平坦層 1 04b和204b第二平坦層 106 和 206 微鏡(microlens)層BRIEF DESCRIPTION OF THE DRAWINGS In order to make the present invention understand, the following detailed description is made as follows: J and other objects, features, and advantages will be more obvious and preferred embodiments, and in conjunction with the drawings, The strip type defect active 1A and 1B shows a plan view of the complex color filter area; the =ic diagram shows the cross section of a conventional image sensor. The active area of the active area is shown in Fig. 2 FIG. 4 is a plan view of a photomask on a substrate; FIG. 4 is an image sensor active region formed by using different masks in a process. FIG. 5 is a plan view showing a photomask used for depositing a photoresist on a color image sensor in FIG. 4; and FIG. 6 to FIG. 9 are diagrams showing a color image sensor. Another embodiment: and FIG. 10 is a schematic view showing the formation of a photosensitive coupling element according to another embodiment. [Simplified Description of Component Symbols] 100 CMOS Image Sensors (CIS) 101 and 201 Filter Regions 102 and 202 Active Regions 103 and 203 Bottom Metal Regions 10 4a and 204a First Flat Layers 104b and 204b Second Flat Layer 106 and 206 microlens layers

第20頁 1316754 圖式簡單說明 107和207基板 108和208接腳塾區域 109和210刻畫線 111、113、211和213彩色阻層 .114和214保護層 118 、 119 、 218和220 高度 122和222接腳墊頂端 200和300彩色濾光片元件 224 後保護接腳部分(P〇st-passivati〇n pad portion 212和412阻層 302方形區域 40 0光罩Page 20 1316754 Schematic description 107 and 207 substrates 108 and 208 pinch regions 109 and 210 scribe lines 111, 113, 211 and 213 color resist layers 114 and 214 protective layers 118, 119, 218 and 220 height 122 and 222 pad top 200 and 300 color filter elements 224 rear protection pin parts (P〇st-passivati〇n pad portion 212 and 412 resist layer 302 square area 40 0 mask

第21頁Page 21

Claims (1)

1316754 六、申請專利範圍 — ' 1. 一種於一半導體基板上形成彩色濾光片之方法,其中該 基板具有至少一具有複數接腳墊之濾光片區域,一第一平 -坦層形成於該基板上,且至少一彩色阻層形成於該至少一 .濾光片區域之第-平垣層上,該方法至少包含: · (a) 沈積一金屬層於該些接腳墊上用以降低其中之步階高. 度;以及 (b) 形成一第二平坦層,使得該沈積之金屬層具有一近於 該平坦層高度之高度。 2·如申請專利範圍第!項所述之方法,其中步驟(a)包括使 # 用濺鍍之方法沈積金屬層。 3 _如申清專利範圍第丨項所述之方法,其中該沈積之金屬 層具有一略大於平坦層之高度。 4. 如申明專利範圍第i項所述之方法,更包含形成第二平 坦層層於該彩色阻層之上,該第二平坦層層具有一略大於 該沈積金屬層之高度。 5. —種於一半導體基板上形成彩色濾光片之方法,其中該 基板具有複數刻晝線用以形成至少一具有複數接腳墊之濾 光片區域°亥些刻晝線係環繞該些接腳墊,至少一彩色阻 層形成於基板上之此至少一濾光片區域中,此方法至少包 含:1316754 VI. Scope of Application - ' 1. A method of forming a color filter on a semiconductor substrate, wherein the substrate has at least one filter region having a plurality of pads, a first flat-tank layer formed on On the substrate, and at least one color resist layer is formed on the first-level layer of the at least one filter region, the method at least comprising: (a) depositing a metal layer on the pads to reduce the a step height; and (b) forming a second planar layer such that the deposited metal layer has a height close to the height of the planar layer. 2. If you apply for a patent range! The method of item wherein step (a) comprises causing # to deposit a metal layer by sputtering. The method of claim 1, wherein the deposited metal layer has a height slightly larger than the flat layer. 4. The method of claim ii, further comprising forming a second planar layer over the color resist layer, the second planar layer having a height slightly greater than the deposited metal layer. 5. A method of forming a color filter on a semiconductor substrate, wherein the substrate has a plurality of scribe lines for forming at least one filter region having a plurality of pads. a pad, at least one color resist layer formed in the at least one filter region on the substrate, the method comprising: 第22頁 1316754Page 22 1316754 (a)沈積一金屬層於該些接腳墊上用以降低其中之步階高 .阻層材料部分地填充該刻晝線以降低刻畫線之 步1¾冋没;以及 中 )形成至少一彩色阻層,同時阻層材料保持在該刻晝線 If專利範圍第5項所述之方法,其中由該沈積金屬 層和邊阻層材料所組成群組中之至少一個具有一個盥一 =層趨近相同之高度,其中該平垣層位於基板和彩色阻層 7. 如申#專利範圍第6項所述之方法,其中形成該平坦層 和使用阻層材料部分填充刻畫線係於同一步驟完成,且单 坦層係以阻層材料形成。 鄉-成且千 8. 如申請專利範圍第5項所述之方法,更包括在步驟(1?)之 後保持阻層材料於該些刻畫線中直到切割製程。 9. 如申請專利範圍第5項所述之方法,其中該步驟(b)& 括: 形成一阻層材料層於該基板上; 使用一光罩架構來暴露該阻層材料層使得不溶解之阻層材 料遣留在刻晝線中,用以降低步階高度:以及(a) depositing a metal layer on the pads to reduce the step height therein. The resist material partially fills the engraved line to reduce the step of drawing the line; and the middle portion forms at least one color resistance The method of claim 5, wherein the resistive layer material is maintained in the method of claim 5, wherein at least one of the group consisting of the deposited metal layer and the edge resist material has a === layer approaching The same height, wherein the flat layer is located on the substrate and the color resist layer 7. The method of claim 6, wherein forming the flat layer and partially filling the line using the resist material is performed in the same step, and The single-tank layer is formed of a barrier material. The method of claim 5, further comprising maintaining the barrier material in the scribe lines after the step (1?) until the cutting process. 9. The method of claim 5, wherein the step (b) & comprises: forming a layer of a barrier material on the substrate; using a mask structure to expose the layer of the barrier material so as not to dissolve The barrier material is retained in the engraved line to reduce the step height: 第23頁 1316754 六、申請專利範圍 移除位於刻畫線外之阻層材料。 • 1 〇. —種製程一半導體基板之方法,此方法至少包含: _(a )提供一基板,該基板具有至少一具有複數接腳墊之濾 光片區域; (b)沈積一金屬層於該些接腳墊上用以降低其中之步階高 度; (b) 形成一平坦層,使得該沈積之金屬層具有一近於該平 坦層高度之高度;以及Page 23 1316754 VI. Scope of Application The material of the barrier layer outside the line is removed. A method of manufacturing a semiconductor substrate, the method comprising: at least: _(a) providing a substrate having at least one filter region having a plurality of pads; (b) depositing a metal layer thereon The pad pads are used to reduce the step height therein; (b) forming a flat layer such that the deposited metal layer has a height close to the height of the flat layer; (c) 形成至少一彩色阻層於該平坦層之上。 11.如申請專利範圍第10項所述之方法,其中步驟(b)包括 使用濺鍍之方法沈積金屬層。 1 2.如申請專利範圍第1 0項所述之方法,其中該沈積之金 屬層具有一略大於平坦層之高度。(c) forming at least one color resist layer over the planar layer. 11. The method of claim 10, wherein the step (b) comprises depositing a metal layer using a sputtering method. 1 2. The method of claim 10, wherein the deposited metal layer has a height that is slightly greater than a flat layer. 1 3.如申請專利範圍第1 0項所述之方法,更包含形成第二 平坦層層於該彩色阻層之上,該第二平坦層層具有一略大 於該沈積金屬層之高度。 1 4.如申請專利範圍第1 0項所述之方法,其中該基板具有 複數刻晝線環繞該至少一濾光片區域排列,該方法更包括 使用形成該平坦層之材料來至少部分填充該些刻畫線。1 3. The method of claim 10, further comprising forming a second planar layer over the color resist layer, the second planar layer having a height slightly greater than the deposited metal layer. 1 4. The method of claim 10, wherein the substrate has a plurality of engraved lines arranged around the at least one filter region, the method further comprising at least partially filling the material using the planar layer. Some lines are drawn. 第24頁 1316754Page 24 1316754 六、申請專利範圍 15·如申請專利範園第1 〇項所述之方法,其中該些刻畫線 疋於步驟(c)中被至少部分填充。 1 6·如申請專利範固第1 0項所述之方法,其中該基板具有 複數刻畫線環繞該至少一濾光片區域排列,該方法更包栝 使用阻層材料來至少部分填充該些刻畫線。 1 7.如申請專利範園第16項所述之方法’更包括在步驟(d)VI. Application for Patent Scope 15. The method of claim 1, wherein the scribe lines are at least partially filled in step (c). The method of claim 10, wherein the substrate has a plurality of scribe lines arranged around the at least one filter region, the method further comprising using a resist material to at least partially fill the characterizations line. 1 7. The method described in claim 16 of the patent application is further included in step (d) 之後保持阻層材料於該些刻畫線中直到該彩色遽光片被切 割。 " 18. —彩色濾光片結構,此結構至少包含: 一具有至少一濾光片區域之基板,其中該濾光片區域具有 複數導體接腳墊結構; 一平坦層位於該基板上,該接腳墊結構具有近於該平坦層 高度之高度;以及 至少一彩色阻層形成於該平坦層之上,位於該至少一濾光 片區域之中。 1 9.如申請專利範圍第1 8項所述之彩色濾光片結構,其 中: 該基板具有複數刻畫線排列形成該至少一滤光片區域’一 阻層材料來被使用來至少部分填充該些刻畫線以葬低該些The barrier material is then held in the scribe lines until the color grading sheet is cut. < 18. A color filter structure, the structure comprising: at least one substrate having at least one filter region, wherein the filter region has a plurality of conductor pad structures; a flat layer is on the substrate, The pad structure has a height close to the height of the flat layer; and at least one color resist layer is formed over the flat layer in the at least one filter region. The color filter structure of claim 18, wherein: the substrate has a plurality of patterned lines arranged to form the at least one filter region 'a resistive layer material to be used to at least partially fill the Some lines are drawn to bury these 1316754 六、申請專利範圍 刻畫線之步階高度,以及 由該接腳墊結構和阻層材料所形成之群組中之至少一個具 _有一與平坦層高度趨近相同之高度。 2 0.如申請專利範圍第1 9項所述之彩色濾光片結構,其中 該平坦層是以阻層材料形成。 2 1.如申請專利範圍第1 9項所述之彩色濾光片結構,其中 接腳墊結構具有一略大於平坦層之高度。1316754 VI. Scope of Patent Application The step height of the line is drawn, and at least one of the groups formed by the pad structure and the barrier material has a height that is close to the height of the flat layer. The color filter structure of claim 19, wherein the flat layer is formed of a barrier material. 2 1. The color filter structure of claim 19, wherein the pad structure has a height slightly larger than the flat layer. 2 2.如申請專利範圍第1 8項所述之彩色濾光片結構,更包 含一第二平坦層層位於該彩色阻層之上,該第二平坦層層 具有一略大於接腳墊結構之高度。2. The color filter structure of claim 18, further comprising a second planar layer above the color resist layer, the second planar layer having a slightly larger pad structure The height. 第26頁Page 26
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