TWI315488B - Scheduler and scheduling method for use in a microprocessor that supports data-speculative execution - Google Patents

Scheduler and scheduling method for use in a microprocessor that supports data-speculative execution

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Publication number
TWI315488B
TWI315488B TW092121785A TW92121785A TWI315488B TW I315488 B TWI315488 B TW I315488B TW 092121785 A TW092121785 A TW 092121785A TW 92121785 A TW92121785 A TW 92121785A TW I315488 B TWI315488 B TW I315488B
Authority
TW
Taiwan
Prior art keywords
scheduler
microprocessor
scheduling method
speculative execution
supports data
Prior art date
Application number
TW092121785A
Other languages
English (en)
Other versions
TW200405201A (en
Inventor
T Sander Benjamin
Alsup Mitchell
Filippo Michael
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of TW200405201A publication Critical patent/TW200405201A/zh
Application granted granted Critical
Publication of TWI315488B publication Critical patent/TWI315488B/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
TW092121785A 2002-08-28 2003-08-08 Scheduler and scheduling method for use in a microprocessor that supports data-speculative execution TWI315488B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/229,563 US6950925B1 (en) 2002-08-28 2002-08-28 Scheduler for use in a microprocessor that supports data-speculative execution

Publications (2)

Publication Number Publication Date
TW200405201A TW200405201A (en) 2004-04-01
TWI315488B true TWI315488B (en) 2009-10-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW092121785A TWI315488B (en) 2002-08-28 2003-08-08 Scheduler and scheduling method for use in a microprocessor that supports data-speculative execution

Country Status (8)

Country Link
US (1) US6950925B1 (zh)
EP (1) EP1532521B1 (zh)
JP (1) JP4170292B2 (zh)
KR (1) KR100981168B1 (zh)
CN (1) CN1320452C (zh)
AU (1) AU2003252081A1 (zh)
TW (1) TWI315488B (zh)
WO (1) WO2004021174A2 (zh)

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9547602B2 (en) 2013-03-14 2017-01-17 Nvidia Corporation Translation lookaside buffer entry systems and methods
US9569214B2 (en) 2012-12-27 2017-02-14 Nvidia Corporation Execution pipeline data forwarding
US9582280B2 (en) 2013-07-18 2017-02-28 Nvidia Corporation Branching to alternate code based on runahead determination
US9645929B2 (en) 2012-09-14 2017-05-09 Nvidia Corporation Speculative permission acquisition for shared memory
US9740553B2 (en) 2012-11-14 2017-08-22 Nvidia Corporation Managing potentially invalid results during runahead
US9766893B2 (en) 2011-03-25 2017-09-19 Intel Corporation Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US9811377B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for executing multithreaded instructions grouped into blocks
US9823931B2 (en) 2012-12-28 2017-11-21 Nvidia Corporation Queued instruction re-dispatch after runahead
US9823930B2 (en) 2013-03-15 2017-11-21 Intel Corporation Method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US9842005B2 (en) 2011-03-25 2017-12-12 Intel Corporation Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
US9858080B2 (en) 2013-03-15 2018-01-02 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9875105B2 (en) 2012-05-03 2018-01-23 Nvidia Corporation Checkpointed buffer for re-entry from runahead
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
US9886416B2 (en) 2006-04-12 2018-02-06 Intel Corporation Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US9891972B2 (en) 2012-12-07 2018-02-13 Nvidia Corporation Lazy runahead operation for a microprocessor
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9898412B2 (en) 2013-03-15 2018-02-20 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9921845B2 (en) 2011-03-25 2018-03-20 Intel Corporation Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
US9934042B2 (en) 2013-03-15 2018-04-03 Intel Corporation Method for dependency broadcasting through a block organized source view data structure
US9940134B2 (en) 2011-05-20 2018-04-10 Intel Corporation Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
US9965281B2 (en) 2006-11-14 2018-05-08 Intel Corporation Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer
US10001996B2 (en) 2012-10-26 2018-06-19 Nvidia Corporation Selective poisoning of data during runahead
US10031784B2 (en) 2011-05-20 2018-07-24 Intel Corporation Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US10146548B2 (en) 2013-03-15 2018-12-04 Intel Corporation Method for populating a source view data structure by using register template snapshots
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US10169045B2 (en) 2013-03-15 2019-01-01 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US10191746B2 (en) 2011-11-22 2019-01-29 Intel Corporation Accelerated code optimizer for a multiengine microprocessor
US10198266B2 (en) 2013-03-15 2019-02-05 Intel Corporation Method for populating register view data structure by using register template snapshots
TWI652618B (zh) 2013-03-15 2019-03-01 英特爾股份有限公司 用以管理儲存在硬體結構中的元素的方法與設備
US10228949B2 (en) 2010-09-17 2019-03-12 Intel Corporation Single cycle multi-branch prediction including shadow cache for early far branch prediction
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US10324725B2 (en) 2012-12-27 2019-06-18 Nvidia Corporation Fault detection in instruction translations

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7415597B2 (en) * 2004-09-08 2008-08-19 Advanced Micro Devices, Inc. Processor with dependence mechanism to predict whether a load is dependent on older store
US7552318B2 (en) * 2004-12-17 2009-06-23 International Business Machines Corporation Branch lookahead prefetch for microprocessors
US7444498B2 (en) * 2004-12-17 2008-10-28 International Business Machines Corporation Load lookahead prefetch for microprocessors
US7421567B2 (en) 2004-12-17 2008-09-02 International Business Machines Corporation Using a modified value GPR to enhance lookahead prefetch
US8046558B2 (en) * 2005-09-16 2011-10-25 The Research Foundation Of State University Of New York File system having predictable real-time performance
GB0519981D0 (en) 2005-09-30 2005-11-09 Ignios Ltd Scheduling in a multicore architecture
JP5146444B2 (ja) * 2007-03-20 2013-02-20 富士通株式会社 マルチプロセッサシステム及びその制御方法
US7730289B2 (en) * 2007-09-27 2010-06-01 Faraday Technology Corp. Method for preloading data in a CPU pipeline
TWI469055B (zh) * 2008-06-27 2015-01-11 Realtek Semiconductor Corp 網路工作卸載裝置與方法
US20100070730A1 (en) * 2008-09-17 2010-03-18 Sebastian Pop Minimizing memory access conflicts of process communication channels
CN101789952A (zh) * 2009-01-23 2010-07-28 瑞昱半导体股份有限公司 网络工作卸载装置与方法
GB2469822B (en) * 2009-04-28 2011-04-20 Imagination Tech Ltd Method and apparatus for scheduling the issue of instructions in a multithreaded microprocessor
US8977837B2 (en) * 2009-05-27 2015-03-10 Arm Limited Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes
US9052890B2 (en) 2010-09-25 2015-06-09 Intel Corporation Execute at commit state update instructions, apparatus, methods, and systems
US20150039859A1 (en) 2011-11-22 2015-02-05 Soft Machines, Inc. Microprocessor accelerated code optimizer
TWI610224B (zh) * 2011-11-23 2018-01-01 英特爾股份有限公司 微處理器加速編碼最佳化器
US10108424B2 (en) 2013-03-14 2018-10-23 Nvidia Corporation Profiling code portions to generate translations
US10061589B2 (en) 2014-12-24 2018-08-28 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10387158B2 (en) 2014-12-24 2019-08-20 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10387156B2 (en) 2014-12-24 2019-08-20 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10303525B2 (en) 2014-12-24 2019-05-28 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10061583B2 (en) * 2014-12-24 2018-08-28 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US9785442B2 (en) 2014-12-24 2017-10-10 Intel Corporation Systems, apparatuses, and methods for data speculation execution
US10942744B2 (en) 2014-12-24 2021-03-09 Intel Corporation Systems, apparatuses, and methods for data speculation execution
CN108279928B (zh) * 2018-01-30 2021-03-19 上海兆芯集成电路有限公司 微指令调度方法及使用此方法的装置
CN108415730B (zh) * 2018-01-30 2021-06-01 上海兆芯集成电路有限公司 微指令调度方法及使用此方法的装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5511172A (en) * 1991-11-15 1996-04-23 Matsushita Electric Co. Ind, Ltd. Speculative execution processor
JPH09500989A (ja) * 1993-05-14 1997-01-28 インテル・コーポレーション 分岐ターゲット・バッファにおける推論履歴
US5452426A (en) * 1994-01-04 1995-09-19 Intel Corporation Coordinating speculative and committed state register source data and immediate source data in a processor
US6185668B1 (en) 1995-12-21 2001-02-06 Intergraph Corporation Method and apparatus for speculative execution of instructions
US5966544A (en) 1996-11-13 1999-10-12 Intel Corporation Data speculatable processor having reply architecture
US6212626B1 (en) 1996-11-13 2001-04-03 Intel Corporation Computer processor having a checker
US6205542B1 (en) 1997-12-24 2001-03-20 Intel Corporation Processor pipeline including replay
US6094717A (en) 1998-07-31 2000-07-25 Intel Corp. Computer processor with a replay system having a plurality of checkers
US6163839A (en) 1998-09-30 2000-12-19 Intel Corporation Non-stalling circular counterflow pipeline processor with reorder buffer
US6367004B1 (en) * 1998-12-31 2002-04-02 Intel Corporation Method and apparatus for predicting a predicate based on historical information and the least significant bits of operands to be compared
US6564315B1 (en) 2000-01-03 2003-05-13 Advanced Micro Devices, Inc. Scheduler which discovers non-speculative nature of an instruction after issuing and reissues the instruction
JP2003259295A (ja) * 2002-03-04 2003-09-12 Canon Inc 撮像装置
US6845442B1 (en) 2002-04-30 2005-01-18 Advanced Micro Devices, Inc. System and method of using speculative operand sources in order to speculatively bypass load-store operations

Cited By (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10289605B2 (en) 2006-04-12 2019-05-14 Intel Corporation Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US11163720B2 (en) 2006-04-12 2021-11-02 Intel Corporation Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US9886416B2 (en) 2006-04-12 2018-02-06 Intel Corporation Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US9965281B2 (en) 2006-11-14 2018-05-08 Intel Corporation Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer
US10585670B2 (en) 2006-11-14 2020-03-10 Intel Corporation Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer
US10228949B2 (en) 2010-09-17 2019-03-12 Intel Corporation Single cycle multi-branch prediction including shadow cache for early far branch prediction
US10564975B2 (en) 2011-03-25 2020-02-18 Intel Corporation Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
US9766893B2 (en) 2011-03-25 2017-09-19 Intel Corporation Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
US9842005B2 (en) 2011-03-25 2017-12-12 Intel Corporation Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
US9990200B2 (en) 2011-03-25 2018-06-05 Intel Corporation Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
US9921845B2 (en) 2011-03-25 2018-03-20 Intel Corporation Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
US11204769B2 (en) 2011-03-25 2021-12-21 Intel Corporation Memory fragments for supporting code block execution by using virtual cores instantiated by partitionable engines
US9934072B2 (en) 2011-03-25 2018-04-03 Intel Corporation Register file segments for supporting code block execution by using virtual cores instantiated by partitionable engines
US10372454B2 (en) 2011-05-20 2019-08-06 Intel Corporation Allocation of a segmented interconnect to support the execution of instruction sequences by a plurality of engines
US10031784B2 (en) 2011-05-20 2018-07-24 Intel Corporation Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines
US9940134B2 (en) 2011-05-20 2018-04-10 Intel Corporation Decentralized allocation of resources and interconnect structures to support the execution of instruction sequences by a plurality of engines
US10191746B2 (en) 2011-11-22 2019-01-29 Intel Corporation Accelerated code optimizer for a multiengine microprocessor
US10146545B2 (en) 2012-03-13 2018-12-04 Nvidia Corporation Translation address cache for a microprocessor
US9880846B2 (en) 2012-04-11 2018-01-30 Nvidia Corporation Improving hit rate of code translation redirection table with replacement strategy based on usage history table of evicted entries
US9875105B2 (en) 2012-05-03 2018-01-23 Nvidia Corporation Checkpointed buffer for re-entry from runahead
US10241810B2 (en) 2012-05-18 2019-03-26 Nvidia Corporation Instruction-optimizing processor with branch-count table in hardware
US9645929B2 (en) 2012-09-14 2017-05-09 Nvidia Corporation Speculative permission acquisition for shared memory
US10628160B2 (en) 2012-10-26 2020-04-21 Nvidia Corporation Selective poisoning of data during runahead
US10001996B2 (en) 2012-10-26 2018-06-19 Nvidia Corporation Selective poisoning of data during runahead
US9740553B2 (en) 2012-11-14 2017-08-22 Nvidia Corporation Managing potentially invalid results during runahead
US9891972B2 (en) 2012-12-07 2018-02-13 Nvidia Corporation Lazy runahead operation for a microprocessor
US9569214B2 (en) 2012-12-27 2017-02-14 Nvidia Corporation Execution pipeline data forwarding
US10324725B2 (en) 2012-12-27 2019-06-18 Nvidia Corporation Fault detection in instruction translations
US9823931B2 (en) 2012-12-28 2017-11-21 Nvidia Corporation Queued instruction re-dispatch after runahead
US9547602B2 (en) 2013-03-14 2017-01-17 Nvidia Corporation Translation lookaside buffer entry systems and methods
US9858080B2 (en) 2013-03-15 2018-01-02 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US10275255B2 (en) 2013-03-15 2019-04-30 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US9823930B2 (en) 2013-03-15 2017-11-21 Intel Corporation Method for emulating a guest centralized flag architecture by using a native distributed flag architecture
US10169045B2 (en) 2013-03-15 2019-01-01 Intel Corporation Method for dependency broadcasting through a source organized source view data structure
US10146576B2 (en) 2013-03-15 2018-12-04 Intel Corporation Method for executing multithreaded instructions grouped into blocks
US10198266B2 (en) 2013-03-15 2019-02-05 Intel Corporation Method for populating register view data structure by using register template snapshots
TWI652618B (zh) 2013-03-15 2019-03-01 英特爾股份有限公司 用以管理儲存在硬體結構中的元素的方法與設備
US9811377B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for executing multithreaded instructions grouped into blocks
US10140138B2 (en) 2013-03-15 2018-11-27 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US10248570B2 (en) 2013-03-15 2019-04-02 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US10255076B2 (en) 2013-03-15 2019-04-09 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US10146548B2 (en) 2013-03-15 2018-12-04 Intel Corporation Method for populating a source view data structure by using register template snapshots
US9811342B2 (en) 2013-03-15 2017-11-07 Intel Corporation Method for performing dual dispatch of blocks and half blocks
US10289419B2 (en) 2013-03-15 2019-05-14 Intel Corporation Method and apparatus for sorting elements in hardware structures
US9904625B2 (en) 2013-03-15 2018-02-27 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US11656875B2 (en) 2013-03-15 2023-05-23 Intel Corporation Method and system for instruction block to execution unit grouping
US10503514B2 (en) 2013-03-15 2019-12-10 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9886279B2 (en) 2013-03-15 2018-02-06 Intel Corporation Method for populating and instruction view data structure by using register template snapshots
US9891924B2 (en) 2013-03-15 2018-02-13 Intel Corporation Method for implementing a reduced size register view data structure in a microprocessor
US9934042B2 (en) 2013-03-15 2018-04-03 Intel Corporation Method for dependency broadcasting through a block organized source view data structure
US10740126B2 (en) 2013-03-15 2020-08-11 Intel Corporation Methods, systems and apparatus for supporting wide and efficient front-end operation with guest-architecture emulation
US9898412B2 (en) 2013-03-15 2018-02-20 Intel Corporation Methods, systems and apparatus for predicting the way of a set associative cache
US9582280B2 (en) 2013-07-18 2017-02-28 Nvidia Corporation Branching to alternate code based on runahead determination
US9804854B2 (en) 2013-07-18 2017-10-31 Nvidia Corporation Branching to alternate code based on runahead determination

Also Published As

Publication number Publication date
JP4170292B2 (ja) 2008-10-22
KR20050037596A (ko) 2005-04-22
EP1532521A2 (en) 2005-05-25
JP2005537567A (ja) 2005-12-08
CN1320452C (zh) 2007-06-06
WO2004021174A2 (en) 2004-03-11
EP1532521B1 (en) 2014-03-12
AU2003252081A1 (en) 2004-03-19
KR100981168B1 (ko) 2010-09-10
US6950925B1 (en) 2005-09-27
TW200405201A (en) 2004-04-01
WO2004021174A3 (en) 2004-06-17
CN1678986A (zh) 2005-10-05

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