TWI314383B - A dc to dc converter having linear mode and switch mode capabilities,a controller,a control method and an apparatus of said converter - Google Patents

Description

1314383 IX. Description of the Invention: [Technical Field] The present invention relates to a DC/DC converter, and more particularly to a controller of a DC/DC converter. ° 'Before [Previous Technology] At present, many electronic devices, such as laptops, portable PDAs, and other portable and non-existing devices, use multiple or multiple DC/DC converters. . Direct production converts an input DC voltage to another voltage. In a typical electronic device, DC/straight is applied to various loads. The DC/DC converter, ° can be used to respond to low loads and become a relatively high load. This kind of ^ may be from the "phase" and / or the heart '^ difference. The line is either low or high negative. It is suitable for supplying power to a low load. It also takes the DC_change and provides = the whole unit will monitor and maintain the output at the desired value. S3, transistor, with 0,, LD 〇 H__ ^ electric = adjuster can be relatively small migration and relatively low miscellaneous positive - the low load. Switching mode DC/DC output 'provides power to the opposite unit, which maintains the round output by switching at least one, = one DC/DC conversion and OFF: ^Transistor transistor 〇N switching mode can be W value. Under such an electric running cycle, an IP060267-TW-spec-X (〇22〇〇7〇i〇8) ^ 1314383 modulated output voltage is provided with relatively high efficiency. ❿ In order to respond to situations where the load may be high or low under different conditions, it is customary to provide a DC/DC converter (eg, an LD〇) with a low load and provide another separate DC/DC converter ( For example, the plate DC/Nucle conversion 11) is matched with the high (four) and switches between two DC/DC conversions H in a specific environment. This method of knowing requires two DC/DC registers and additional components and pins to achieve switching between the two, thus increasing cost and complexity. Therefore, there is a need for a controller that has both linear and switching mode capabilities. The invention provides a controller package for DC 7 DC conversion 11 from the aspect of the invention. The shirt mode control circuit and the switching mode control electric power mode control circuit can provide a - control signal of the first control system: one of the text control devices. The controlled device should be controlled by the other as a variable resistor. Converter-output voltage. The cut-and-control control of the straight/DC conversion signal to the DC/straight circuit can provide a second control should be compared with the control device and the switch _. The switch control circuit state can be Enabled to control the controlled response of the consistent energy signal - on behalf of the money / A_i ^ set the security road is set to signal and - under voltage threshold::: the pressure of the signal and the representative if The output voltage of the TP060267-TW-spec-X (〇2 20070108) 8 1314383 signal is less than the undervoltage threshold level - or the second control signal. The number and the overvoltage threshold of the controlled splitting Level ratio _, the path is further set to make the signal larger than The overvoltage threshold is used to compensate the signal of the voltage - or the second control signal. The first control signal is supplied to the controlled device. The _ packet = mold set = control circuit and protection The linear mode controls the second control U to the controlled device of the money/DC wire. The receiving device = direct response =; the control signal acts as a variable electric H to control the straight-like voltage. The city mode (4) circuit can provide a first-control number to the controlled device of the money/DC converter. The controlled device responds to the second control signal as a switch operation to switch ON and =, to (4) the DC/DC conversion The output of the device (4). One of the linear mode control circuit and the switching mode control circuit responds to the state of the uniform energy signal, which can be caused by the control. The wire protection circuit is set to receive - on behalf of the money / New The signal of the _ _ & voltage and compare the signal to the threshold of the under-limit, if the signal representing the output voltage is less than the threshold of the money, the first- or the a second control signal. The protection circuit is further configured to send the letter Comparing with the over-voltage threshold, if the signal representative of the output electrical calendar is greater than the over-voltage threshold level, the first or second control signal provided to the controlled device is compensated. In one aspect, a control method is provided. The method TP060267-TW-spec-X (〇2 20070108) 9 1314383 = ^: time period providing - first control signal to - DC conversion state one of the controlled devices, the first And the mode control circuit provides a linear variability _ _ the first - (four) signal as one of the output voltages of the DC 7 DC converter. The method is further included in the second time Providing a first two! to the DC/money turn (4) controlling the % control device of the 爪^ claw age, the second time period does not overlap with the smash period, and the second control signal is switched by the controller mold

= The control circuit provides that the controlled device screams the control number to cut: , ON and OFF to control the output voltage of the DC/DC converter. 2 = method-step includes - representing the output two-voltage signal of the DC/DC converter and a voltage threshold level and - under-power threshold level ratio and 'if the signal representing the output voltage is greater than The over-voltage threshold is either less than the social threshold threshold, _ repayment - or the second control signal. According to yet another aspect of the present invention, an apparatus is provided. The device includes an integrated circuit that can be selected from a plurality of charging mode wipes to charge the rechargeable battery. The Wei type of charge includes a _ switching mode and a linear mode. [Embodiment] FIG. 1 illustrates a block diagram of an electronic device 100 including a power source 102, a DC/DC converter 1〇4, and a load 1〇6. The electronic device 100 can be a variety of devices such as a notebook computer, a cell phone, a personal digital assistant (PDA), and the like. The power source 102 can be a variety of power sources, such as a battery (e.g., a lithium battery) that provides an unregulated DC voltage (Vin) to the TP060267-TW-spec-X (02 20070108) 10 1314383 converter ι〇4. The DC/DC converter 104 provides an adjustment 1 to the voltage 106 (V〇Ut) to the load 106. For simplicity, while the DC/DC converter 104 and associated load 106 are shown, the configuration (10) may include multiple money/DC converters to accommodate multiple loads. This = 2 is a detailed block diagram of the DC/DC converter (10). ^ 曰冰转换 benefits 104 generally include a controller 201 that controls to

The cancer of the body Q1 is controlled to control the voltage of the DC/DC converter. The consuming crystal Q1 can be a transistor of any face. 1 〇2〇1 may include a linear mode control circuit 202* a switching mode circuit. The "circuitry" described herein may include, for example, a single solid, programmable circuit, state machine circuit, and/or a block of programmable instructions, or a combination of the above. The mode control circuit 202 or the switching mode control circuit 204 can respond to the state of the enable signal of the terminal in different, non-repeating time intervals, and control the state of the transistor (1) in which the DC/DC is difficult to switch. If the enable signal is digital, the switch mode control circuit 2〇4 will be disabled without providing any control signals to the transistor φ. Conversely, the linear mode control circuit 202 will be enabled ( Enabled), by switching back to the digital 0 enable signal, the switch sw is turned off to control the state of the transistor Q1. When the switch sw is closed, the linear mode control circuit 202 can set a first control signal (eg Hdrjd〇) is supplied to the transistor Q1. The transistor Q1 operates in response to the first control signal from the linear mode control circuit 2〇2 in a linear region and controls the DC/DC converter TP060267-TW-spec-X ( 02 The first control signal may be an analog voltage signal. If the enable signal is a digital one, the switching mode control circuit is enabled to provide a second control signal to the electrical Crystal.... At this time, the rounding of the device 209 will become 〇, and the switch sw will be output and turned on. Therefore, the linear mode control circuit 202 will not be able to control the transistor Q1 in this case. Responding to the second control signal from the switching mode control circuit 204, the transistor Q1 can be switched ON and OFF to control the output voltage of the DC/DC converter. A feedback signal representing the output voltage V〇Ut Provided to the linear mode control circuit 202 and the switching mode control circuit 2〇4, and the first and second control signals from the linear mode control circuit 2〇2 and the switching mode control circuit 204 are at least according to The feedback signal is compared with a reference voltage level. Figure 3 illustrates an embodiment of a DC/DC converter 104a that is identical to the DC/DC converter 1〇4 of Figure 2. Controller 2 〇1& A low dropout voltage regulator (LDO) circuit 202a is provided which operates as the linear mode control circuit 202. The control module 201a also includes a pulse width modulation (pWM) circuit 204a which acts as the switching mode control circuit 2〇4 In a preferred embodiment as shown in FIG. 3, the pWM circuit 2〇4& can operate as a voltage controlled mode asynchronous PWM control H. In other embodiments, the switching mode control circuit 204 can also Contains other controllers, such as current control surface control (four), synchronous control (four) or pulse fresh modulation controller, etc., but not limited to this. The transistor Q1 may be a p-type metal oxide semiconductor field effect transistor (M〇SFET) or pM〇s, and its gate electrode may be adapted to receive from the LD0 circuit 202a depending on the state of the enable (d) (iv) state. The first control signal or the second control signal from the pwM TP060267-TW-spec-X (02 20070108) 12 1314383. If the enable signal is digital, the PWM circuit 2〇4a is disabled by causing the driver 316 to be in a high impedance state. The LD 电路 circuit 202a can also be enabled to provide its control signal (hdr_ldo) to the control terminal of the PMOS transistor Q1 by turning off the switch Sw. The control signal (hdr-1do) provided by the LD〇 circuit 202a may be an analog voltage signal 'and the transistor Q1 may respond to the control signal while operating in its linear region' and controlling the amount of current to adjust the output voltage. The standard is said. ♦ When the transistor Q1 is operated under the control of the LDO circuit 202a and in its linear region, the output voltage of the DC/DC converter is advantageously a very low ripple voltage and the control The device 201a consumes a low static current. ~ The LD0 circuit 202a includes an amplifier 322 that operates as a same error amplifier. The amplifier 322 can receive a feedback signal representative of the output voltage Vout at its inverting input. The feedback signal can have a voltage level vi which is obtained by a voltage divider comprising resistors RfM and Rfb2 calling the feedback resistor network 328 to reduce Vout. The amplifier 322 can also receive a reference voltage signal at its non-inverting input via a reference terminal 334. The reference voltage # can be of various sources, such as a bandgap circuit. During DC operation, the amplifier 322 of the ldo circuit 202a can compare the reference voltage signal with the voltage level VI, and according to the difference between the voltage signal or a voltage error signal, via a closed switch SW &amp The appropriate output control signal (hdr-1do) is supplied to the transistor Q1 to operate as the same error amplifier. The transistor q should be controlled back to TP060267-TW-spec-X (〇2 20070108) 13 1314383 ^The word operates in the linear region, and the correction of the voltage level v(10) is corrected, which may drive the voltage error signal close to zero. For example, if the output voltage v〇ut on terminal 336 is increased beyond an expected voltage, the dragon voltage level V1 will also increase. Therefore, the error voltage between the two inputs of the amplifier 322 produces a control signal _Jd0) which causes the transistor Q1 to conduct less current to lower the output voltage V〇ut. Conversely, if the output power on terminal 336 is reduced to more than an expected voltage level, the voltage level VI will also decrease. Thus, the error voltage between the two inputs of the amplifier 322 produces a control signal (hdr-1do) that causes the transistor Qi to conduct more current to increase the output voltage V?ut. If the enable signal is a digital one, the driver 316 of the PWM circuit 2 can be enabled to provide a PWM control signal (hdr) to the pM〇s transistor Q1. In addition, the output of the inverter 209 can be digital, and the switch sw can be turned on in response to the output to effectively block the control signal (hdr_ldo) from the LD〇 circuit 202a to control the pmS transistor Q1. The PMOS transistor Q1 can be switched ON and OFF in response to the duty cycle of the PWM control signal (hdr) to adjust the output voltage v〇ut. Therefore, when the enable signal is digital 1, the controller 201a operates as a PWM controller, and the PMOS transistor Q1 has an ON-OFF frequency that is determined by the ramp signal of the oscillator 314, which can be achieved. High efficiency of more than 90 〇 / 〇. The PWM circuit 204a includes an error amplifier 310, an oscillator 314 for generating a ramp signal, a comparator 312, a compensation capacitor Cc and a resistor Rc, and a driver 316. The error amplifier 310 can be inverted in its TP060267-TW-spec-X (〇2 20070108) 14 1314383 «r • human terminal ^ the feedback signal (10). The feedback signal can represent V〇ut on terminal 336.赖纽Α|| The village receives a reference to the dust signal from terminal 334 at its non-inverting input and provides a = signal based on the difference. The comparator 312 can receive this at its non-inverting input. The signal is received at its inverting input - the ramp L number from oscillator 314 and provides an output PWM signal 342 (pwm_in) having a duty cycle based on the intersection of the comparison signal and the ramp signal. The control $201a may also include an overvoltage and undervoltage protection circuit 326 for protecting the DC/DC converter from overvoltage and undervoltage conditions. The controller 20U may also include a soft start circuit 332. 4 illustrates the comparison signal 402 of the non-inverting input of the comparator 312 and the ramp signal provided to the comparator 312 of FIG. 3, from the oscillator 314 of FIG. As the value of the comparison signal 4〇2 increases and decreases, the intersection of the comparison 彳§ 402 and the ramp signal changes accordingly. The resulting pwm_in signal 342 from the comparator 312 thus has a pulse visibility and its duty cycle is based on the value of the intersection. When the comparison signal is lowered, the duty cycle of the pwm_in signal 342 is lowered, and the comparison signal is raised, and the duty cycle of the pwm_in signal 342 is also raised. The driver 316 accepts the pwm_in signal 342 and provides an output PWM signal (hdr) to the PMOS transistor Q1. The output pwM signal (hdr) is the inverse of the pwm_in signal 342, as shown in FIG. Figure 5 illustrates in more detail one embodiment of the driver 316 driver 316a in the PWM circuit 204a of Figure 3. The driver 316a includes a plurality of inverters 502, 506, 508, 510, 514, 516, 518, an inter-N0R 504, a NAND gate 512, and transistors Q2, Q3. The transistor Q2 can be a TP060267-TW-spec-X (02 20070108) 15 1314383. The transistor Q3 can be an N-type metal oxide semiconductor field effect transistor (MOSFET) or an NM0S transistor. When the enable signal is digital, the output of inverter 5〇2 is digit 1. Since one of the inputs of the NOR gate 504 is a digital 丨, the output of the N 〇 R gate 5 〇 4 is also a digital 〇. Therefore, the output of the inverter 5〇6 is digital, the output of the inverter 508 is the digit 0, and the output of the last inverter 51〇 is the digit 1. Since the transistor Q2 is a PM〇s transistor in this embodiment, the transistor Q2 responds to the digital 丨 from the inverter 51, and is 〇FF. When the enable signal is digital, the output of NAND gate 512 is digital. Thus, the output of inverter 514 is digital 0, the output of inverter 516 is digital 1, and the output of last inverter 518 is digital. Since the transistor Q3 is an NMOS transistor in this embodiment, the state of the transistor Q3 is also 〇FF, and when the enable signal is digital, the driver 316a is effectively disabled. Since the terminal 522 of the driver 316a that supplies the hdr control signal is coupled to a pair of PMOS transistors Q2 and NMOS transistors Q3 that are both OFF, the driver 316a does not output the signal hdr when the enable signal is digital. Therefore, the driver 316a is effectively disabled. In other words, when the enable signal is digital, the driver 316a will be in a high impedance state. When the symptom is § §, the hdr signal is the inverse of the pwm_in signal as shown in Fig. 4. The pwm_in signal may be digit 〇 or digit 1. When the pwm_in signal is the digit 1 and the enable signal is the digit 1 'the output of the NOR gate 5〇4 is the digit 〇. Therefore, the output of inverter 5〇6 is digit 1, the output of inverter 508 is digital 〇, and the output of the last inverted state is digit 1. The PM〇s transistor responds to bit 1 of inverter 510 and is 0FF. When the Pwm__in signal is the digit 1 and the enable signal TP〇60267-TW-spec-X(〇22〇〇7〇1〇8) 16 1314383 - is the digit 1 day, the 3 inputs of the NAND gate 512 are all digits. Therefore, the output of the NAND (5) 512 is digital. This causes the output of the inverter to be digital 1, and thus the NM〇s transistor Q3 is 〇N. When the pwm-in signal is digital and the enable signal is digital i, the turn-off of the NAND gate 512 is digital, and thus the output of the inverter 518 is digit 0. In response to this, the NM〇s transistor Q3 is 〇FF. In this case, the three inputs of the NOR gate 504 are all digital. Therefore, the output of the NOR gate 504 is a digital bit and the output of the inverter 51 is a digital bit | In response to this, the PMOS transistor Q2 is 〇Νβ. Therefore, when the enable # is a digit 1, the hdr signal is the inverse of the pwm_in signal, as shown in FIG. 4, and when the enable signal is digital, The driver 316a can achieve effective de-energization by switching the % sa bodies Q2 and Q3 to OFF. Figure 6 illustrates in more detail an embodiment of the overvoltage/undervoltage protection circuit 326 shown in Figure 3 as an overvoltage/undervoltage protection circuit 32. In general, if no overvoltage or undervoltage condition is detected, the c〇mp and hdr_ldo彳§ numbers in Figure 3 will not be compensated. When an undervoltage condition is detected, the c〇mp | 彳§ number will be pulled up and the hdr_ldo signal will be pulled down to drive up the output voltage v〇ut. When an overvoltage condition is detected, the comp signal will be pulled down and the hdr_ldo signal will be pulled up to drive down the output voltage v〇ut. The overvoltage/undervoltage protection circuit 326a includes two comparators 602 and 604. The undervoltage comparator 602 compares the feedback signal (fb) representing the output voltage with an undervoltage threshold level. If the feedback signal is not below the undervoltage threshold level, the comparator 602 outputs a digit 〇. If the feedback signal is equal to or lower than the undervoltage threshold level, the comparator 602 outputs a TP060267-TW-spec-X (02 20070108) 17 1314383 digit 1. Similarly, the overvoltage comparator 604 compares the feedback signal to an overvoltage threshold level. The comparator 604 outputs a digit 〇 if the feedback signal is not above the overvoltage threshold level. The comparator 6〇4 outputs a digit i if the feedback signal is equal to or towards the overvoltage threshold level. During operation, if the enable signal is digital, indicating that the PWM circuit 204a is used, and the feedback voltage level is not lower than the undervoltage threshold level or higher than the overvoltage threshold level, the comparison is performed. The rounds of the 6〇2 and 6〇4 are all digital. Therefore, the output of the NAND gate 006 is digital. In response to this, the PMOS transistor Q4 is 〇ff. The turn of inverter 608 is digital 1' and the output of NAND gate 610 is digital 0. In response to this, the NM0S transistor q5 is also 〇FF. Therefore, no compensation will be applied to the comp signal in this case. Further, during operation, if the enable signal is a digit 0, indicating that the LDO circuit 202a is used, and the feedback signal is not below the undervoltage threshold level or above the overvoltage threshold level, then the comparator The outputs of both 602 and 604 are still digital. Therefore, both inputs of the n〇R gate 612 are digit 0, and their outputs are digits 1. In response to this, the PM0S transistor Q6 is OFF. The output of NOR gate 620 is a digit 0. In response to this, the NMOS transistor Q7 is also 〇FF. Therefore, no compensation will be applied to the hdr_ldo signal in this case. If the enable signal is a digital bit indicating that the PWM circuit 204a' is being used and the feedback signal is below the undervoltage threshold level, the output of the undervoltage comparator 602 is a digital 丨. Since both inputs of NAND gate 6〇6 are digital 1 in this case, their output is digit 0. In response to this, the PM0S transistor Q4 is 0N, and the c〇mp signal is pulled up to c〇mph. TP060267-TW-spec-X (02 20070108) 18 This number of 1314383 is pulled up to comph by the signal comp signal, the pWm duty cycle will increase to increase the output voltage level, and therefore 3 has been granted Voltage level. 9

If the enable signal is a digit 1 ' indicating that the PWM power 204a is used and the feedback signal is above the overvoltage threshold level, then the output of the overvoltage comparator 604 is a digital one. Therefore, the rotation of the inverter 608 is digit 0. The input one given by NAND gate 610 is a digit and the digit is 〇 ', and its output is digit 1. In response to this, the NMOS transistor q5 is ON, and the comp signal is pulled down to c〇mpl. By pulling the signal signal down to compl, the duty cycle of the pwm_in signal will decrease by two to lower the output voltage value and thus lower the feedback voltage level. If the enable signal is digital, indicating that the Ld〇 circuit 202a is used, and the feedback signal is above the overvoltage threshold level, the output of the overvoltage comparator 604 is given by the digital hNQR gate 612. Input one is a digit 0 - is a digit 1 and its output is a digit 〇. In response to this, the PMOS transistor Q6 is ON. Therefore, the hdr_ldo signal is pulled up to hdr_ldoh, which then pulls down the output voltage v〇ut. If the enable signal is a digital 〇 indicating that the LD 〇 circuit 202a is used and the feedback signal is below the undervoltage threshold level, the output of the undervoltage comparator 602 is digital! . If the two rounds of the NAND gate 618 are digital because the output QN of the D flip-flop 616 is also the digit 1 then the output of the NAND gate 618 is the digital gate 62. Both inputs are digit 0, then the NOR gate The output is digital. In response to this, the NMOS transistor Q7 is ON. Therefore, the hdr_ldo signal is pulled down to hdr_Idol, which in turn pulls up the output voltage v〇ut. TP060267-TW-spec-X (02 20070108) 19 1314383 - When entering the controller mode, it is used to switch from linear mode to switched mode, 兮back =, 通昂' in switching mode And linearly squeezing V, which becomes two and two ''to make a power out of the wheel and 1 between a and M and the undercurrent limit. The ferroelectric is accompanied by causing the output VGUt to be higher than the overvoltage Η The limit is arbitrarily used in the large (2) 2〇1 to use the overvoltage/under-thunder only. The magic mode control state ^ MrJd〇 (hysteresis) working mode \, "^ position quasi-Asia work in " lag behind this cloth , the concept can also be used to describe the operation of the comparator. A phased comparator is in the two inputs of the comparator (for example, ν_ * V - phase; in the case of the position (tGggle). For the county ratio (four) in this In the case of Zhensheng, the “hysteresis comparator can be used. The hysteresis comparator is rounded to the digital G when its two inputs are equal, for example, Vinp=Vinm. The hysteresis comparator is at Vinp=Vinm+ In the case of Δ V, the output is digital!, where Δ v can be a small part of Vinm. Figure 6 "Lagged working mode, class For operation of the hysteresis comparator. For example, when the output voltage of the DC/DC converter 1〇4a of FIG. 3 is also controlled by the overvoltage/undervoltage protection circuit 326a of FIG. 6, v〇ut may not be equal to an ideal. The value is set. Conversely, Vout can have a non-zero peak-to-peak value AV, which is determined by the threshold levels UVJh and 〇v-th according to the formula AV=ov_th-uv_th. The overvoltage/undervoltage protection circuit 326a can be represented by, for example, the comparator 604 in the embodiment of FIG. 6, which will represent the DC/DC converter TP060267-TW-spec-X (02 20070108) 20 1314383 ==== The _: comparison:: factory sangha DC, DC converter = two:: compared with - under-power limit for the 4th C house followed by the _ limit on time: over-power: f6a can also, The rim to the right represents the output of the DC/DC converter ^ :=, the _ undervoltage protection 2 == and _ are guaranteed in the linear mode voltage range 'the DC/DC converter output difference is defined Within the range of π limit sheep, the counter 616 can have a reset signal (reset) input. The reset Lu test about G volts increase sincerely _ The turn-off voltage avoids the occurrence of false undervoltage during soft-start. In the case of dynamic, the initial low output voltage may touch the 0N°D flip-flop. The output may return to the reset signal for one digit 0. The output of the NAND gate 618 is digitized i and the wheel of the gate 620 is digitally digitized to maintain the NM〇s transistor (7) as a voltage/undervoltage protection circuit 326a capable of starting at about 0 volts and towards one A soft start condition is identified during the desired or adjusted increase in the output voltage level. The overvoltage/undervoltage protection can also effectively disable the comparison operation performed by the comparator 602 to avoid false undervoltage conditions in the soft start condition. /, b The enable signal can be provided from a variety of sources. Figure 7 illustrates the enabling signal TP060267-TW-spec-X (〇22〇〇7〇1〇8) 21 1314383. The possible source is - Microcontroller 7Q2. Once the controller presses the button 704, the microcontroller 702 in the handset will be powered. ", Figure 8 does not specifically describe another embodiment that provides the enable signal in response to varying load conditions. A sense resistor 8 〇 2 is used for the inductive load. The voltage drop across the sense resistor 8G2 is proportional to the load current. The resistance of the sense resistor is relatively small with 2, and can be amplified by a sense amplifier _ Provide - can represent the voltage level or Vil of the load current. - Comparator 806 then compares the voltage Vil with a reference voltage level, such as a Laibi supply. If the voltage level Vil is greater than the reference voltage level refl, the comparator provides an enable signal in the digital 1 state. If the voltage level Vil is less than the reference voltage level, the comparator_provided enable signal is in the digital G state. In other words, the controller can operate the PWM circuit 2G4a to maintain high efficiency with the heavy load when the patient's stomach load is relatively heavy. When the load is two relatively light loads, the controller can operate the LD〇 circuit to provide a low noise output. _ • Figure 9 shows the simulation results of the DC/DC converter 104a of Figure 3. The line segment 9〇2 depicts the enable signal (4). The line segment 9〇4 indicates that the load current of the DC/DC converter varies from lmA to 1〇〇mA. The line segment 9〇6 indicates the DC/DC converter's turn-off voltage ν_, and the line segment 9()8_ indicates the gate drive signal for the PMOS transistor Q1 control terminal. Between time and ti, the line segment 9 〇 2 of the enable signal is a digital 〇. Accordingly, the controller operates in the LDO mode, and the LD〇 circuit provides an inter-drive signal to the PMOS transistor Q1. During this time (1) and u, as indicated by line 904, the load current remains relatively low and is fixed at imA. As shown in the TP060267-TW-spec-X (02 20070108) 22 !314383 segment 906, the output voltage is also relatively fixed during this period. The LDO circuit supplies the pM〇s to the circuit = the drive signal is also -__ If the test 9G8 = Q between N and t, the enable signal is converted from the digital transmutation mode to the _ mode, where _ electric =: = = dynamic signal to the PMOS transistor Q1. The p-signal representing the compensation transition 2 can be lower than a certain level (for example, ιν), then the p-plane h: It is: the 乍 period is. . Thus, during the period between U and t2, L ίί = s transistor Q1 asks for the hdr signal to be a digit 1, as shown by Line & 908. And between time tl#〇t2, with load current

Increase (line 904) and the output voltage decreases (line segment 9〇6). The L ^ den comp signal reaches the threshold level (eg, ιν). At time t2, the duty cycle of the pwm_m signal 342 starts from 〇, and the generated hdr signal from the driver 316 is at time t2 and ts. Inter-oscillation, as indicated by line 908 (see also Figure 1 〇). Between times t2 and t3, the output voltage begins to increase and returns to the desired value of 3 3V, as indicated by the line segment alone.

Between time t2 and t3, since the PM〇s transistor φ is switched between 〇N and 〇FF, the output voltage may have a chop. At time t3, the enable signal is converted from digital 数 to digital 〇, and the reference = kPWM mode is switched back to ld〇 mode, where the circuit 2〇2a provides a gate drive signal (eg hdr_ldo) to the PMOS Crystal Q1. During the time between time t3 and t4, as the load current drops (line segment 9〇4), the gate drive signal is increased (line segment 908) to drive the turn-off voltage (line segment 906) to its regulated value of 3.3V. 10 is an enlarged view of the controller 2〇la changing from ld〇 mode to TP060267-TW-spec-X (02 20070108) 23 1314383 in FIG. 9 during the transition period of the p-purchase mode (centered on time t2); FIG. 2 is another enlarged view of the controller 2 in FIG. 9 when the PWM mode is changed to the equation (centered on time t3). As is well known in the game, the biggest challenge of LDO design is the stability of the loop over a wide range of current carrying currents. For light load, LD〇 can be stable and unstable for heavy load. This requires increased cost and complexity to compensate for LDO. For example, the equivalent series resistance (Resr) of the capacitor q in Fig. 3 is utilized to achieve the purpose of compensation. This requires a capacitance a and a well defined series resistance and will be reduced to the temporary output performance of the output voltage ν_. Other compensation greens can also be used, which also increases the LD() complex. Person, Table 1 shows an LD. An example of AC fractals in the case of light load (1 mA in this embodiment) and heavy load (1 GQ mA for this actual package). As shown in Table 1, the phase range of 78.5882 degrees (Li (4) is suitable for light load conditions but negative for heavy loads. This LD 需要 requires some compensation for stability under heavy load conditions. Table 1

Index ii〇ad gain(db) unit freq phase temper alter# _______margin___ 1mA 72.1337 i.673e+〇3 78.5882 60.0000 !.〇〇〇〇 100mA 80.7657 5.640e+04 -0.9238 60.0000 !.〇〇〇〇 . Advantageously, the controller 2〇la of Fig. 3 can operate only in a light load condition: operating the LDO circuit 202a' and switching to the PWM f path 204a under heavy load conditions. Therefore, the LD〇 circuit 2〇2a can be stabilized with only a small amount of cost and complexity for the additional compensation method to ensure stability in the heavier TP060267-TW-spec-X (02 20070108) 24 1314383 i::: Degree, and the controller (10) is under the -wide range load current graph. The test result of the DC/DC converter of 3 is straight. 4/·^# does not enable the voltage of the signal (Ven), and channel 2 illustrates a feedback voltage _ of the representative wheel voltage. Channel 3 illustrates the gate drive signal (Μ), while channel 4 illustrates the load current (IlGad) of DC / is ; Figure 13 is an enlarged view of the Ven, Lion and Vhdr edges from the LD0 mode to the PWM 1 when the enable signal is changed from 1 to h: i. ® 14 is an enlarged view of when the enable signal changes from 0 to modulo 4, and her Ven, Vfb, and Vhdr plots from PWM mode to LD0. As shown, the tests of Figures 12 through 14, and . The simulations of Figures 9 through 11 are supported. = illustrates operation 1500 in accordance with one of the embodiments. Operation of the dirty packet time period provides - the first - control signal to - DC / DC transfer ^ (four) control device, the first control signal is provided by a linear mode of a controller, the m device responds to the first - control signal and operates 2 The resistor 'controls the output voltage of one of the DC/DC converters. Operation = 5 = includes at - H provides - a second control signal to the controlled device of the direct, machine converter, the second time period does not overlap with the first time period 'The second control signal is controlled by the second control signal The switching mode control circuit provides that the controlled device responds to the second control signal to switch (10) to OFF to control the output voltage of the DC/DC converter. The operation shall include comparing - the signal representing the output electric star of the DC/DC converter with the over-current threshold level and the - under-power limit, and the operation 2: including the signal if the output is representative of the output Greater than the over-power threshold TP060267-TW-spec-X (02 20070108) 25 !314383 . The first or second control signal is compensated if it is less than or less than the undervoltage threshold level. Figure 16 is another embodiment 104b of the DC/DC converter 1A4a of Figure 3. Elements similar to those in FIG. 3 are denoted by like reference numerals and will not be described again. - The DC/DC converter l〇4b may include a switch SW2 connected in parallel with the inductor L1. When the enable signal is digital, the switches SW1 and SW2 are both turned off in response to the output bit 1 from the inverted 209. When ld〇 circuit 202a provides an analog control signal to controlled device 1604, switch SW2 can cause a better transient effect. The controlled device 1604 can be a plurality of devices that can operate as a variable resistor when receiving the analog control signal from the LD〇 circuit 2〇2a, and can act as a control signal when receiving the PWM control signal from the PWM circuit 204b. The switch works to switch ON and OFF. In an embodiment, the controlled attack can be a transistor. The transistor may be a plurality of types of transistors, such as a bipolar junction transistor (BJT) 'insulated gate bipolar power field effect transistor (IGBT) or field effect transistor (FET), for example comprising the PMOS transistor Qi _ MOSFET. - Figure 17 is a circuit diagram of the PWM circuit 204b of Figure 16. The PWM circuit can include an oscillator 314, an error amplifier 310, a comparator 312, and another embodiment 316b that is compatible with the driver 316 of FIG. Elements in Fig. 17 that are similar to those in Fig. 3 are denoted by like reference numerals and will not be described again. The driver 316b may include a first inverter 1704, a NOR gate 1706, a second inverter 1708, a NAND gate 1710, a third inverter 1712, and transistors Q8 and Q9 on the output stage of the driver 316b. The transistor Q8 can be a PMOS thunder 曰曰 body, and the Q9 can be an NMOS transistor. The output control signal of the driver 316b TP060267-TW-spec-X (〇2 20070108) 26 1314383 hdr can be rotated from the node 1724, which is located between the pm〇S transistor Q8 and the NMOS terminal Q9. When the enable signal is a digital zero, the output of the first inverter 1704 is a digital one. Since an input of the NOR gate 1706 is a digital bit, its output is a digit 0. The output of the second inverter 1708 is therefore a digital one. Since the transistor Q8 is a PMOS transistor in this embodiment, the output bit 1' transistor Q8 in response to the second inverter 1708 is OFF. When the enable signal is digital and the output of the second inverter 1708 to the NAND gate 1710 is a digital one, the output of the NAND gate 1710 is a digital one. The output of the third inverter ι712 is therefore a digit 0. In response to this, the NMOS transistor Q9 is also OFF. Therefore, when the response enable signal is digital, both transistors Q8 and Q9 are OFF, and driver 316b is effectively disabled in this case. In other words, when the enable signal is digital, driver 316b is in a high impedance state. When the enable § § is digit 1, the hdr signal can be the inverted signal of pwm_in as shown in Figure 4. The pwm_in signal may be digital or digital. When Pwm-in is digital and the enable signal is digital 1, the output of NAND gate 1710 is digital 1 ' and the output of third inverter 1712 is digital. In response to this, the NMOS transistor Q9 is OFF. The three rounds of NOR gate 1706 are in this case all digits zero. Therefore, the output of NOR gate 1706 is 1, and the output of second inverter 1708 is digital. In response to this, pm〇S transistor Q8 is ON. When the pwm_in signal is a digit 1 and the enable signal is a digit 1... (10) The output of gate 1706 is a digital 〇. Accordingly, the output of the second inverter 17A is digital one. The PM0S transistor Q8 is responsive to the digital 1 output of the second inverter 1708 and is 0FF. When the Pwm_in signal is digit 1 and the enable signal is TP060267-TW-spec-X (〇2 20070108) 27 1314383 =丄• The three inputs of 171〇 are all digits, so the input is 〇. The output of the second inverter 1712 thus obtains the digits /, and therefore = the material 0N. According to this, when the money domain is enabled, hdr 1 Lu can hide the inversion of pwm in, ^ ^ signal is digit 0, by making the transistor ^ not, and when enabling 3 is effectively removed Q8 And Q9 are both clear, the driver is advantageous in that, in these embodiments, a controller is operable to pull the circuit and switch the mode circuit. Therefore, the operation of the two-factor/DC converter and the two controllers is conventionally required, and only the controller and the _straight-converter are required to perform. This reduces costs. Control_ can switch between the neutral mode and the switching mode to capture each mode line. For example, if the linear mode circuit includes an LD〇 circuit, the controller is in a light load condition. Work. Therefore, the switching mode circuit includes a -PWM circuit, and the control device (4) can be used in the PWM mode to provide the _p domain to the controlled device of the DC/DC controller. According to this situation, high efficiency can be relied upon. More advanced, if the coffee circuit is only 2, the load can avoid the county LDQ circuit (four) and complex, :=〇 circuit for heavier loads 'these expensive and complex complements', the terminology used in this article; Language is used to describe and not to limit these terms and phrases and is not intended to exclude any equivalents that have the features (or features) as described in this document. It should be understood that there may be Various modifications and changes are possible. Therefore, the scope of the patent application is intended to cover all of this, etc., TP 〇6〇267-TW-spec-X (02 20070108) 28 I314383 Simple illustration of the diagram] Figure 1 is a system 2 is a schematic diagram of a DC/DC converter of FIG. 1; FIG. 3 is a circuit of an embodiment of the DC/DC converter of FIG. 2, including a DC/DC converter Controller

4 is a diagram showing a pulse width modulation type signal of the control n in FIG. 3; FIG. 5 is a circuit diagram showing an embodiment of the pulse width modulation circuit of the controller of FIG. 3; 6 is a circuit diagram of an embodiment of an overvoltage/undervoltage protection circuit of the controller of FIG. 3; <FIG. 7 is a circuit diagram showing an example of providing an enable signal to the controller of FIG. 2 or 3; A circuit diagram for providing an enable signal to the other embodiment of the controller of FIG. 2 or 3; only FIG. 9 illustrates a green diagram showing the simulation of the DC/DC converter of FIG. 3; FIG. 10 is a plot of FIG. Enlarged view from LD◦ mode to pwM mode change period; 'Turn

Figure 11 is an enlarged view of the period from the pWM mode to the LD〇 mode in the drawing of Figure 9; W Figure 12 illustrates a plot of the test results of the DC/DC converter of Figure 3;

Figure 13 is an enlarged view of the period from the LDO mode to the pwM mode in the drawing of Figure 12; W Figure 14 is an enlarged view of the switching period from the pwM mode to the LDO mode in the drawing of Figure 12; ' ^ TP060267 - TW-spec-X (02 20070108) 29 1314383 Figure 15 is a flow chart showing an operation of an embodiment of the present invention; Figure 16 is a schematic diagram of another embodiment of the DC/DC converter of Figure 3; Figure 16 is a circuit diagram of the pulse width modulation circuit. [Main component symbol description] 100: electronic device 102: power supply 104: DC/DC converter 104a, 104b: DC/DC converter 106: load 201: controller 201a, 201b: controller 202: linear mode control circuit 202a: Low dropout voltage regulator (LDO) circuit 204: switching mode control circuit 204a, 204b: pulse width modulation (PWM) circuit 209: inverter 212: terminal 310: error amplifier 312: comparator 314: oscillator 316: driver 316a, 316b: driver 322: amplifier TP060267-TW-spec-X (02 20070108) 30 1314383 _ 326: overvoltage/undervoltage protection circuit 326a: overvoltage/undervoltage protection circuit 328: feedback resistor network 332: soft Startup circuit 334: terminal 336: terminal 342: PWM signal 402: comparison signal • 404: ramp signal 502: inverter 504: NOR gate 506: inverter 508: inverter 510: inverter 512: NAND gate 514: inverter § 516: inverter 518: inverter 522: terminal 602: comparator 604: comparator 606: NAND gate 608: inverter 610: NAND gate 612: NOR gate TP060267-TW-spec- X (02 20070108) 31 1314383

Inverter D forward and reverse NAND gate NOR gate microcontroller power supply by ugly sensation resistance induction amplification comparator line segment line segment line segment: Operation: Operation: Operation: Operation: Operation: Controlled device: Inverter: NOR Gate: Inverter: NAND Gate: Inverter: Node TP060267-TW-spec-X (02 20070108) 32

Claims (1)

The scope of the patent application: L two, the controller of the DC/DC converter, and the switching between the TM switching modes, and the linear mode line * the shank type control circuit, which can raise the DC/DC converter - Controlled loading ¥-4—control signal to the control signal as a variable resistor: receiving, returning the DC converter-wheeling voltage; to control the DC/switching loose control circuit, which can provide DC The controlled converter of the /DC converter - the control signal to the second control signal as a switch; the switching control device should make the DC/DC conversion, 0N 〃, 0FF to control the output voltage of the emperor The linear m-channel and the switching mode control electric control are enabled to control the controlled device two enable 15 and configured to receive an undervoltage, such as - money and use - Then the i (hysteresis) comparator compares the threshold level, if 哕俨嘹ru, the person electric 4 "唬 is less than the undervoltage threshold, the second circuit is stepped - the step is configured to provide compensation to the controlled device. 20 years, month, repair (more) Page ____ 忒 彳 彳 或 或 s or the second control signal, the protection "step is configured to use - over-voltage lag comparator will represent the read output voltage of the signal and - over-voltage threshold level Comparing, if the signal representing the output voltage is greater than the overvoltage threshold level, the protection circuit compensates the first control signal or the second control signal provided to the controlled device 'the undervoltage hysteresis comparator and the The overvoltage hysteresis comparator is configured to drive the first control signal, the desired power 0212-TW-OA1 -CH Claim-AmdSet(sandra.t-20090211)1 25 ------------- --------------丨丨--.-一r13⁄4 43 83]Repair (more) is replacing page ί ϋβ. 2. 2.^ .-above. Pressure level; change mode The control circuit includes a pulse width modulation number, wherein if the control signal includes a generic output signal, the received circuit is enabled to control the controlled switching, and wherein if the output S is representative of the undervoltage threshold level The protection circuit compensates the interesting output signal by a period, and if the voltage of the circuit is greater than the overvoltage Limiting the limit, the PWM output signal is compensated by reducing the duty cycle; and the PWM circuit includes an error amplifier and a driver to provide a PWM round-trip signal, when the enable signal is at - -^ sorrow, each of the error amplifier and the driver individually responds to an enable signal to provide the 15 PWM round-out number, and when the enablement is in the "second state, each error And the driver does not provide the second control signal. 2. The controller of claim i, wherein the 20 includes: a first inverter to receive the enable signal and provide a wheel number; and the S-NOR gate receives the first-reverse The output signal of the phase comparator, and receiving one of the comparators from the PWM circuit, pWM^in 25 signal; 0212-TW-OA1-CH Claim-AmdSet(sandra.t-20090211)2 1314383 is replacing i the first counter a phaser 'receives an output signal from the NOR gate and provides the first control signal; - a first transistor receives the first control signal; - a NAND gate receives the first control from the second inverter ^5, and receiving the enable signal and receiving the pwM input signal; a third inverter receiving an output signal from the NAND gate and providing the second control signal; and - a second transistor receiving The second control signal, the second control signal 10, is coupled to a terminal of the driver coupled to the first transistor and the second transistor. 3. The controller of claim 2, wherein - the first 15 and the second transistor are - 0N to return a value of pw = 1 to the value provided by the driver The pWM output signal is the inverse of the PWM input signal. ^ The controller of claim 1 of the scope of the patent, wherein the linear = system includes - linear mode error A | §, which side responds to the 5-energy signal. 20 The controller of the fourth aspect of the patent, wherein the linear 具有 Ϊ 具有 has a switch effective furnace to the linear mode: the output of the large device, and the open relationship is individually returned to = 6. - DC / DC A converter comprising: a controlled device; and a controller for controlling the controlled device, the controller comprising: 0212-TW-OA1-CH Claim-AmdSet (sandra.t-20090211) 3 25 lW Kiss and flow/DC conversion a second control signal is set, the controlled switch switch TM is back = 2 to control the output of the DC/DC converter 2 'the line is controlled and the one of the line is enabled To control the controlled device in response to a state of a consistent month number; and, the protection circuit 'returns the enable signal and is configured to receive a signal representing the output voltage of the DC/DC converter' and The signal is compared to an undervoltage threshold level using an undervoltage hysteresis comparator, and if the signal representative of the output voltage is less than the undervoltage threshold level, the protection circuit is further configured to compensate for the controlled device The first control signal or the second control signal, the protection circuit is further configured to compare the signal with an overvoltage threshold level using an overvoltage hysteresis comparator, if the signal representative of the output voltage is greater than the overvoltage threshold a level, the protection circuit compensating the first control signal or the second control signal provided to the controlled device, the undervoltage hysteresis comparator and the overvoltage hysteresis The comparator is configured to drive the first control signal to a desired voltage level; 0212 TW-OA1-CH Claim-AmdSet(sandra.t-20090211)4 1314383 .. i Λ νι, cold farming, the switching mode control The circuit includes a chirped pulse width (shun) circuit, and the second control signal includes a =#u, wherein if the PWM circuit is enabled to = controlled device, the corrected back should be PWM output as: Switching between ON and 〇FF, and wherein: the signal of the output voltage of the second meter is less than the undervoltage criterion, the protection circuit increases the operation by selecting the output signal, and if the output voltage is greater than The voltage threshold is used to compensate for the warfare. The error is reduced by red. The PWM circuit includes an error amplifier and the drive provides the P WM turn-off signal. When the enable signal is 15 20 = - shape · 4 o' each time the error A|| and the driver individually respond to the enable signal to provide the pwM input number, when the enable signal is in a second state, each of the errors ^ The amplifier and the driver do not provide the second control number. 7. For example, (4) DC/DC conversion of item 6 of the patent scope: where = the package: the transistor 'operates in the 'linear region' in response to the signal. The switch is responsive to the second control. 8. The DC/DC converter of claim 7 is inductively coupled to a terminal of the transistor, and wherein the sense is connected in parallel, when the linear mode control circuit provides the ^ = When the signal is applied to the transistor, the switch should be enabled to close. 0212-TW-0A1 -CH CIaim-AmdSet(sandra.t-20090211)5 25 9. The DC/DC converter of claim 6 wherein the driver comprises: 5 a first inverter to Receiving the enable signal and providing an output signal; a NOR gate receiving the output signal from the first inverter, and receiving a PWM input signal from one of the comparators of the PWM circuit; ίο a second inversion Receiving an output signal from the NOR gate and providing the first control signal; a first transistor receiving the first control signal; and a NAND gate receiving the first control signal from the second inverter And receiving the enable signal and receiving the PWM input signal; 15 a third inverter receiving an output signal from the NAND gate and providing the second control signal; and a second transistor receiving the first And a second control signal outputting a terminal coupled to the first transistor and the driver of the second transistor. 20 10. The DC/DC converter of claim 6, wherein one of the first transistor and the second transistor is ON to respond to a value of the PWM input signal, thereby enabling the driver The PWM output signal is provided as an inverse of the PWM input signal. 0212-TW-OA1-CH Claim-AmdSet(sandra.t-20090211)6 J314383 Hanging) For the #V Patent Application No. 6 DC This linear mode control circuit includes a linear mode error amplifier, which is individually back The signal should be enabled. " 12· For example, the DC/DC converter of the 11th patent application scope, wherein f linearity; ^-type error A ^ has -_ effective she is connected to the output of the Qin mode error amplifier, and the relationship is individual Ground _ the enable signal. 13. A DC/DC converter control method comprising: 10 15 providing a uniform energy signal; providing - during the - time period - a control signal to - a DC method - a controlled device, and returning One of the signals should be enabled. First: The first control signal is provided by a linear mode circuit of a controller that operates as a variable resistor to return the first control signal to control the One of the DC/DC converters ϋ voltage; the annihilation is provided in the second time period - the second control money is supplied to the dc, the controlled device of the converter, and the response signal is -second = evil, The second time period does not overlap with the first time period, and the second (4) signal is controlled by the controller-switching mode control circuit, and the controlled device switches (10) and OFF to respond to the second control. a signal to control the output voltage of the DC/DC converter; and a second-to-initial-overvoltage 卩m level-to-electrical limit level comparison of the output voltage of the DC/DC converter; If the representative read voltage is cut in the over t-gate 25 The undervoltage threshold level 'compensates the first-control (four) 0212-TW-OAl-CH Claim-AmdSet(sandra.t-20090211)7 I sound 8 net El repair (history) soil replacement page 2. 2β or the first a control signal; wherein the switching mode control circuit comprises a pulse (s) circuit, and the second control signal comprises a singular signal, wherein if the PWM f path is enabled to control the receiving, the double The control device responds to the P WM turn-off signal - the duty cycle is switched between ON and OFF ' and the PWM circuit includes an error amplification state and a driver to provide the pWM output signal when the enable flag is in the first state And each of the error amplifier and the driver individually responds to an enable signal to provide the pWM output signal, and when the enable signal is in the second state, each of the error amplifier and the driver does not provide the second control signal. . 14. The method of claim 13 wherein the compensation operation comprises transitioning between the first time period and the second time period - the output voltage of the DC/DC converter is switched to The desired output voltage level is maintained such that the output voltage is maintained within a range defined by the difference between the overvoltage threshold level and the undervoltage threshold level. 1 15. The method of claim 13, wherein the switching mode control circuit comprises a pulse width modulation (PWM) circuit, and the second = system signal comprises a P WM output signal, and wherein the method is The reserving operation includes: increasing the duty cycle of the PWM output signal if the signal representative of the output voltage is less than the undervoltage threshold level; and decreasing if the signal representing the output voltage is greater than the overvoltage threshold level The duty cycle of the PWM signal is small. 0212-TW-OA1-CH Claim-AmdSet(sandra.t-20090211)8 1314383 A: όΒ., Da ....—— * 16. The method of claim 13 further includes: The feedback signal of one of the DC/DC converters outputs a current level and a threshold level comparison, and if the feedback signal is below the threshold level, the linear mode control circuit is selected to provide the first control 5 signal And to the controlled device, and if the feedback signal is higher than or equal to the threshold level, the switching mode control circuit is selected to provide the second control signal to the controlled device. 17. The method of claim 13, wherein the linear mode φ control circuit comprises a linear mode error amplifier that individually responds to the enable signal. 18. The method of claim 13, wherein the linear mode error amplifier has a switch operatively coupled to the output of the linear mode error amplifier, and the open relationship individually responds to the enable signal. 15 0212-TW-OA1 -CH Claim-AmdSet(sandra.t-20090211)9