TWI313829B - - Google Patents

Description

, 1313 829 IX, invention description: [Technical field of invention] The present invention is an ic circuit verification platform, which is a platform for simple verification and easy operation for verification of integrated circuit design, in order to make the verification process more Convenient, fast and accurate. [Prior Art] _ Digital is very important for human beings. The basic unit is the so-called dimension, which is the application technology consisting of 0 and 1. In addition to directly drawing the schematic Schematic, there is also a way to implement the circuit directly in language. This language is called the Hardware Descripition Language (HDL). Of course, for a complex digital circuit implementation, the process of drawing a circuit is quite time consuming. This is the first of two languages in the hardware description language (HDL), one of which is the HDL of VERIL0G. The second is VHDL. However, when using the HDL language to design logic circuits, FPGA (Field pr〇grammable • Gate Array) and CPLD (Complex Programmable Logic Device) components can be said to provide the best method. f?ga is in the ultra-large Jixian Road, super large circuit (pass

• ¥ is a 84 chat or larger 1C package), evenly configured - a large stack of programmable logic cells (called 4 for CLB). Each CLB has basic combinational logic and sequential logic, and a uniform array of programmable ge^(Rc)Utings is also configured between CLB and CLB. By controlling these wirings, a single CLB can be integrated into A complete and complex large-scale circuit; finally, the programmable wheel-in and out-out (called I0B) distributed around the periphery provides the interface between the FpGA and the external circuit. The most special 疋 'Logical unit (CLB) in FPGA tl, output wheel 阜 (10)) and wiring (10) 叩) 5, 1313 829 This error detection and design calibration steps until the error-free design data is obtained Up to the event tester. A further aspect of the invention is a verification device for a composite integrated circuit design, the verification device of the design being constructed by different devices for achieving the acceptance method of the above design, which utilizes the combination of the event tester and the FPGA or the event The combination of the tester and the simulator board for high speed test pattern application and response evaluation as well as design debug and error correction. According to the invention, the event tester and the on-line programming of the FPGAs can be used to verify the design to replace the slow-leg simulation tool used. Because the full-chip level simulation is not used and the software is used to run faster on the FPGA, the amplification verification that is not feasible in the current technology can be completed. L invention content] At present, Lin Shaozhi is also based on the riding board. Most of the secrets are not directly connected to the PC. After the circuit is downloaded to the FPGA, all the data input is transmitted to the _ 'output and connect to the logic. On the money, through the analyzer to store and observe the execution results of the circuit, _ get the bribe secret execution wire and then change the Wei, the circuit is re-revisioned (4), but if the test program has errors, need to be modified, Still need to rewrite the program benefits ^ immediately modify the test program, it still shows the domain line results of the logic analyzer, of course, there are 4 damage prototype board is the PCI interface, directly inserted, the type of mine m, * price users The driver development process is verified in the circuit ^, but the driver writing program is cumbersome, and "can not assist the small module to do the verification work, and the system uses the CI interface to test the circuit. We provide quite a lot of innovations on the software side, so that users can, good and easy to directly finance the results of the work of the circuit, no need to 1313929

User program 50: Users can generate real-time data during the run-up according to the requirements of the hardware circuit to provide the use of circuit simulation, and receive real-time data from the hardware for processing or storage. This function helps. In the SOC (System on Chip) HW / SW Co-simulation / co-verification, the actual way can be achieved by using the DynamicUnk Library or Class library, so that it can be directly connected to the Tunnel.

Tunnel 51 is an application that provides an interface for transferring data to the end of the book for simulation use at runtime-time with the interface application pr〇gram. This program can also be used by the host computer to control the book-end clock based on the data, and the other end is connected to the user program (user program) for the exchange of data. Waveform checker: Used to compare with the prepared data.

Waveform display : Display the returned data in a waveform.

Data Storage 53: Used to store large amounts of uploaded and returned data such as hard drives.

Waveform Editor 52: Use the graphical interface to edit the simulation to the current data (according to the clock). Then, for the process, the second description, as shown in the seventh figure, assumes that after the user has programmed the designed logic circuit to the Slave FPGA, the user can use the Editor 52 or the user program User Program. 5〇 (T_ei 5ι means that when the user program calls the APIs, the APIs will establish a communication channel with the system software through the Ipc〇nter p pulse _ιυ provided by the operating system.) The generated input data or has been stored. In the Data Storage 53 Interface Application Program 55, the data to be tested and the hardware control signal are placed in the memory of the PC, and the data in the 1313829 format is available for access, data and time related information, in the Slave FPGA. To write data to Buffers, you must also update the conten1: • field in the table' and the Control Chip must refer to the content when moving the data back to Host Computer.

The information in the Table is updated as appropriate.

The data that Multiplexer uses to switch is the circuit to be passed to Level 1 Buffer or Level 2 Buffer. When there is no data transmission between the Host computer and the Level 1 Buffer, the multiplexer points to the Level 1 Buffer, otherwise it points to the Level 2 Buffer, 9 and its action is controlled by the Control Chip.

Level 1 Buffer is a Volatile memory (such as SRAM or DRAM). Its function is to store the data that the Slave FPGA needs to return to the Host computer for use by its system software. There is no data between the host computer and the book. When the transfer is used, once the Buffer has too many negative materials, it must be transferred back to the Host computer in Burst mode, and its content status is stored in the Buffer controller & content table, which can reduce Host • computer and HW. The number of transmissions between to increase efficiency.

Level 2 Buffer has the same function as Level 1 Buffer. The difference is that when Host Computer and Level 1 Buffer perform data backhaul action, if Slave fpga cannot suspend its action due to any factor, its action and state must continue and be When recording, its data will be saved to

In Level 2 Buffer, after the Level 1 Buffer data is transmitted and can be written again, the data of the Slave FPGA is transferred to the Levei 1 buffer. At this time, the Level 2 Buffer resource 14 1313829 is returned to the Host computer. · According to the flow chart shown in the figure, a detailed explanation is given. c〇n廿^ will receive the I/F 60 signal, and take the clock signal and clock control signal to ^ to control the source of the clock. With the clock action, the pulse source can come from MW _ 6i (fr〇m I/F 60) 'the clock signal provided by the HW board and the peripheral IC. Control the clock action to make the appropriate source or temporary disposal of the silk source, and read the execution of the Slave off 66 single step execution or the execution of the break point. C〇ntr〇i chip 61 (5) will receive the test data and control signals stored in Data/Control Buffer 63. The Data/Control Buffer 63 inputs the signal to the Slave FpGA 66 based on each clock. The peripheral circuit is also connected to the Slave FPGA 66 on the hardware board. Because the sieve FPGA 66 may be down or suspended, the Peripheral 1C's clock must be controlled by the Clock Gen System 62.

The output signal generated by the Slave FPGA 66 is judged according to the amount of data in the two Buffers included in the Buffer contr〇i & c〇ntent Description Table 64, whether the format is available for access, data and time related information, and The output signal is passed to level 1 Buffer 68or level 2 Buffer 69, and Multiplexer 67 is used to switch the path of the transmitted data. The fields in the Buffer control & content Description Table 64 must also be updated when the Slave FPGA 66 is to write data to the Buffers. To avoid frequent transmissions between the Host computer and the HW, use two Buffers (Level 1 Buffer 68 and Level 2 Buffer 69) and transfer the data in the Buffer to the Host computer in Burst mode. When Level 1 Buffer is 15

Claims (1)

,-1313829 资""乂一..................! + · " i. ..·» , · ί '· ί , Apply for a patent garden: ί. 二ί二 "一丨... .....:'....~ .. ...1 1· A 1C circuit verification platform, which includes: - a user end, the user inputs an instruction into a software platform to execute The program of the order; the software is from the 'Bao _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ And outputting the value to the data processing system; The X-body D-system is mainly equipped with a test analog circuit, and the main control chip receives the instruction request given by the software platform, and tests the analog circuit; the data processing line is connected to the software platform. The following instructions require processing of the data, and the output signal (value) is entered into a display device. The 1C circuit verification platform, the software platform includes 2. As one of the claims in the first item, there are the following four units: the maker and the frequency communication interface, the listening is for the side age and the hybrid body and the The hardware platform is used to communicate with each other, and the programming language is communicated with each other. The data is changed to the data interface, and the real-time test hardware can be loaded. The analog circuit can also provide modifications to the FPGA analog circuit. Interface for test data; a data analysis interface that performs the analysis and processing of the input signal (value) and transmits the data to an image presentation interface; , 'The image presentation interface' is a data analysis interface The image-editing process is transferred to the data processing system for display on the display for viewing by the user. 3. If you declare a patent, you must be a criminal! The ic circuit verification platform described in the item, the hardware platform includes 1313829 has the following four units: control sa slice ', control a test signal generation, a temporary memory area interface processing, an FPGA analog circuit test data transfer integrated read wafer; control buffer, which integrates test data stack to Temporary storage area, and monitor and exchange processing data; temporary storage area placement device, which gives space for test output, input signal data exchange and temporary storage; - FPGA installation device 'is supplied with an FPGA analog circuit chip The load is placed for testing of the test analog circuit. 4. An IC circuit verification platform as described in claim i, wherein the data processing system can be a PC personal computer. 5. An IC circuit verification platform as described in claim i, wherein the data processing system can be a large computer. 6. If you apply for a patent scope! An IC circuit verification platform according to the item, wherein the data processing system can be a PDA. 7. As one of the Dragon Circuit Verification Platforms described in the scope of the patent application, the data processing system can be a mobile phone and a PDA mobile phone. 8. For the IC circuit verification platform described in item 2 of the patent application scope, the software platform can be subdivided into: - User PlOgram (user program), which performs user circuit test; 20 1313829 is called "The Tunnel" is the communication interface between the user program software. A WaveformEditoK waveform editing platform is used to edit the input and output signals (values) into waveform signals (values). A Data St〇rage (data storage platform) for temporarily storing and storing the input and output signals (values); a WaveformDisplay/Checket• (waveform display/comparison platform) for inputting and outputting signals (values) Compare the analysis; an Operating System (the operating system), in charge of the overall operation of the software; a Driver (driver), will be transferred to the ι / F (soft and hardware interface) data delivery format and sent to the hardware end; I/F (software interface) is a software and hardware communication interface. An Interface Application Program, the interface application application through the operating system 〇perating (10), the driver and the driver The soft and hard interface I/F transfers and converts data to each other. 9. An ic circuit verification platform according to claim 2, The platform can be subdivided into: an I/F (soft and hardware interface), which is a software and hardware communication interface; a Control Chip (control chip) that controls the overall integration of the hardware; a Clock Gen SystemC clock generation system) , control clock source and clock action; a Control Buffer (control buffer), will receive the data to be tested and the control signal storage and according to each clock, the signal is input to the Slave FPGA (slave FPGA) 21 1313829 ! A Buffer Controller & Content Table, the test data and time related information, judged processing and update and the output signal to Level i Buffer (the first layer Punch) or Level 2 Buffer (second layer buffer); - Peripheral Chip (peripheral control unit chip), providing test pulse; - Slave FPGA (slave FPGA), where the analog circuit FPGA is placed; - Mux ( The multiplexer's data is used to switch to the circuit of LeveU (the first layer buffer) or Level 2 Buffer (the second layer buffer); ► —Level 1 BuffeK first layer buffer ), the first layer of f material storage space; - Level 2 Buffer (second layer buffer), the second layer of data storage space. 10. An IC circuit verification platform as described in claim 8 or 9, wherein the I/F soft and hardware interface can be a parallel interface. 11. An IC circuit verification platform as described in the first paragraph of the Shenqing patent scope, the (4) interface is PCI. 12. An ic circuit verification platform as described in claim 10, wherein the parallel interface is PCi-χ. 13. A circuit verification platform as described in claim 8 or claim 9, wherein the soft and hard interface can be a serial interface. 14. An IC circuit verification platform as described in claim 13 of the patent application, wherein the interface (10) is USB. 15. A type 1 (the circuit verification platform according to claim 13), wherein the serial interface is 1394. 22.1313829 16. A 1C circuit verification platform according to claim 13 of the patent application, serial The interface is Ethernet. 17. A 1C circuit verification platform according to claim 13 of the patent application, wherein the serial interface is PCI Express. 18. A 1C circuit verification platform according to claim 13 of the patent application scope, The serial interface is Giga Ethernet. 19. A 1C circuit verification platform according to claim 8 or 9, wherein the I/F soft hardware interface is a wireless interface. 20. A 1C circuit verification platform according to claim 19, wherein the wireless interface is an Ultra Wide Band. 21. A 1C circuit verification platform according to claim 19, wherein the wireless interface is 802.11x. 23 1313829 one;: rc 1 1313829 \ <m 咏 1313829 _ data processing system fourth picture 1313829 Fifth picture 1313829 Figure 6 1313829 Seventh figure 1313829 Eighth picture