TWI313508B - Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same - Google Patents

Description

1313508 IX. Description of the Invention: [Technical Field] The present invention relates to a non-volatile memory cell, and more particularly to a non-volatile memory cell including a multilayer insulating structure, and a memory array including the memory cell And its manufacturing method. φ [Prior Art] Non-volatile memory (NVM) refers to semiconductor memory that continuously stores information even when the power supply of components including the NVM memory cell is removed. NVM includes Masked Read Only Memory (Mask ROM), Programmable Read Only Memory (PR〇M), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and flash memory. Non-volatile memory systems are used in large quantities in the semiconductor industry and are a type of memory used to prevent loss of stylized data. Typically, the non-volatile memory can be programmed, read, and/or erased according to the end use requirements of the component, and the programmed S material can be stored for long periods of time. Non-volatile memory components can be used in a variety of different designs, including the "floating gate type" of the shoulder charge storage layer, and the charge trapping layer, which will be stored locally. The local consumption (four) charge storage (or capture) refers to the ability to store the charge in the off-charge trapping layer, and does not cause a large (four) horizontal shift in the storage layer. The conventional "floating (4) memory cell system includes a charge storage layer, which is a conductor and the stored charge is horizontally dispersed in the entire layer of the towel (ie, dispersed throughout the entire surface of the 1313508). In the past 20 years, the computer and electronic communication industry has grown by a large percentage, and the portable (VLSI) and the ultra-large integrated body have become the conductor super-large integrated circuit. This is low power consumption and high density _ LSI The main driving force of design. Because the system has a very large market demand; ===== Memory is a heavy erase of the semi-guided embryo industry

Poor body; Γ ’ 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观 观Gan Li 705 has recalled the 'in this field, but it has not been greatly embarrassed. /, the two-bit 7-inch memory cells have multiple threshold voltage levels, where each of the two threshold voltages (four) stores - different bits. This double-dimensional memory cell (10) relies on complexity, thus blocking its widespread application. 1 His two-dimensional memory cell uses a charge trapping layer and has two separate storage devices, which store information on the two sides of the same memory cell. One of the two-dimensional alpha occult cells is a nitride-reading memory (5), and the 5' nitride traPping memory uses a thicker channel oxide layer in the semi-conductor The charge traps between the nitride layers to avoid charge loss during data storage. However, a thicker channel oxide layer may affect the channel erase speed. Therefore, the band-to-band wear-through thermal hole (BTBTHH) erasing method is often used to inject holes into the channel to offset previously stored electrons. However, the BTBTHH erasing method can cause reliability problems. For example, the performance characteristic coefficients of the NVM component using the btbthh erase method may degrade rapidly after multiple 131313508 of the stylization/erase (p/E) cycle because the semiconductor layer/oxide interface may be due to the BTBTHH method. And it caused damage. In the present invention, the term "semiconductor layer" refers to a layer structure in which a source/drain region is adjacent to a surface of the layer, and "semiconductor substrate" or "substrate" refers to a support or insulating structure adjacent to the semiconductor layer but does not include Source/drainage area. Not all semiconductor elements have a semiconductor substrate, and in the case of not having a semiconductor substrate, the semiconductor layer is generally also considered to be a substrate. Another charge trapping NVM memory cell design is a germanium-oxide-nitride-oxide-germanium (SONOS) device that can include a thin tunneling oxide layer between the semiconductor layer and the charge trapping layer. An erase operation that allows the tunnel to tunnel directly. Although this design achieves excellent erase speeds, data retention performance is generally poor, in part because direct tunneling can occur at low field strengths, while low field strengths already exist in the memory state of the memory device. Therefore, there is a need in the art for a non-volatile memory cell design and array that can be programmed and erased multiple times without being subjected to thermal tunneling from the semi-φ conductor layer to the semiconductor layer/ The oxide interface is damaged. SUMMARY OF THE INVENTION The present invention relates to a non-volatile memory cell and an element including the same, and more particularly to a non-volatile memory cell design including a multilayer structure including an insulating polysilicon disposed on a charge storage layer and Between the gates, the positive voltage wipes the storage operation and allows the gate to be injected into the hole. The invention also relates to methods of operating such memory cells. According to the practice of the present invention, the positive voltage erasing operation of the semiconductor layer/oxide method can reduce the damage caused by the semiconductor layer/oxide method for the injection of the thermal hole between the semiconductor layers. The partial use is used as the erasing method of the memory cell. A negative gate is not required in this method, so the required peripheral circuitry can be simpler and more dense. </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> The structure of the channel region; the charge layer 0 above the τ insulating layer... the upper insulating layer i is overlaid on the 叆 charge storage layer, wherein the upper insulating layer structure is interposed between a first dielectric layer and a second dielectric layer = 曰, and a gate disposed over the upper insulating multilayer structure. Another embodiment of the present invention includes a memory cell, the package comprising: - a stone semiconductor layer comprising at least two source/drain regions disposed under the surface of the semiconductor layer and separated by a channel region - the Wei compound insulation is placed in the channel region; the niobium cut charge storage layer is disposed on the = insulating layer; the upper insulating multilayer structure is disposed on the milk, wherein the upper insulating multilayer structure includes - The crystal layer is deposited on the -th-thorium oxide dielectric layer and the second germanium oxide layer: wherein the thickness of the polycrystalline frequency layer is about 10 to 3 Å, 'oxide dielectric The thickness of the layer is about 1 〇 to 4 _ 〜 弟 矽 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Above the upper insulating multilayer structure, wherein the gate system comprises a doped polycrystalline layer. The invention also includes non-volatile memory elements, a plurality of memory cells (i.e., arrays) including a plurality of memory cell embodiments in accordance with the present invention. In the present invention, the words "plural" and "at least two" 1313508 and the like 鲞^ _„ ' are referred to as two or more 疋 数 singular "one" and singular: in the present invention, no object, Unless the sentence is clear: °5~" includes a plurality of designations that can include a plurality of such memories so that 'for example, "-memory cells" A memory device of the present invention shows large (two-charge storage and improved durability): Quality 'includes a reduction in heart damage. About 1 () volts 5 ports ^ erasing caused the erase voltage is lower than a reverse and closed (NA = p = already a dog. This erase voltage. At the same time, the present invention can be used in the body of the body The interface of the invention occurs near the gate 】 = damage 'because the reason for the damage reduction of the present invention is far less than the band ^ ^ ^, the present invention also includes the operation of non-volatile memory = method. One of the embodiments of the method includes a square pole of a single enthalpy, which is sufficient for the hole to pass a positive voltage from the gate to the gate structure (the fourth) and the purpose of the section and the present invention. The invention is defined by the application = enclosure. The advantages of the invention, the advantages of the invention, and the like, will be fully understood through the following description of the patent scope and the drawings.

[Embodiment J] Reference will now be made in detail to the preferred embodiments of the invention, In the description of the present invention, in order to be concise, directional words such as top, bottom, left, right, up, down, top, bottom, bottom, back end, front end, etc. are used only in the corresponding drawings. These directional words 1313508 茱 are not used in the drawings herein, although the description of the present invention is in any way. These examples are for illustrative purposes only, and the example 'is understood that the process steps and structures are not covered: the sword can understand the complete process of the present invention. The present invention can be used in conjunction with the integrated circuit circuit technology required for the entire integrated circuit, the memory cells of the present invention which are well known or under development in the field, and including more than two and including such Memory cells and /. The memory of the cell V1V [some reliability problems in the component, especially estimated, can be overcome = memory element. The memory cell junction of the present invention; the charge storage/primary thermal cavity erasing method has positive voltage and gate storage characteristics. The various aspects of the present invention are dependent on maintaining the thermal tunnel tunneling erase method: the two columns are degraded for a plurality of stages in the semiconductor layer after a band pass/erase cycle. The peripheral circuit used in the simplified and denser use of the interface-related damage can be lower than; and the erase voltage i required for the flash memory is reduced, because the interface of the present invention is reduced. This is a cross-sectional view of the memory cell 1GG of the present invention, which is caused by the fact that the money is close to the gate and not close to the surface damage. The memory cell includes a semiconductor layer 101' which includes at least two source/drain electrodes = 11 Å, m, wherein each of the source/drain regions 110, 112 can function as a source depending on the applied electric dust. The semiconductor layer ι〇ι is further wrapped between the two source/drain regions. The memory cell (10) further includes a 10.1313508 lower insulating layer 120 disposed over the channel region 115, but not necessarily directly on the surface of the semiconductor layer 101. For example, an additional layer structure may be selectively disposed between the surface of the semiconductor layer and the lower insulating layer, for example, a gate oxide layer (not shown) is disposed on the surface of the semiconductor layer. The memory cell 100 further includes a charge storage layer 130 disposed on the lower insulating layer 120. The memory cell 100 further includes an upper insulating multilayer structure 140 having a polysilicon layer 144 interposed between a first dielectric layer 142 and a second dielectric layer 146. The memory cell 100 further includes a gate 150 disposed over the upper insulating layer structure 140. The invention can also be applied to a memory cell having a conventional germanium semiconductor layer which does not have a substrate, or an insulating overlying germanium (SOI) and thin film transistor (TFT) process or a vertical transistor process. For the purposes of the present invention, a "semiconductor layer" refers to a layer structure in which a source/drain region is adjacent to a surface of the layer, and a "semiconductor substrate" or "substrate" refers to a support or insulating structure adjacent to the semiconductor layer. But does not include the source/drain region. Not all semiconductor elements have a semiconductor substrate, and in the case of not having a semiconductor substrate, the semiconductor layer is generally also considered to be φ. The memory cell of the present invention comprises a semiconductor layer. Any layer of semiconductor material suitable for use in half of the conductor elements can be used. In many preferred embodiments of the invention, the semiconductor layer comprises a germanium material. Tantalum wafers fabricated using standard techniques can be used to prepare suitable semiconductor layers. For example, a suitable wafer can be formed using a suitable process in which a lanthanide is drawn from a tiny crystal (referred to as a seed crystal) via rotation and slowly drawn from a molten south to form a cylindrical crystal, which is then sliced. A thin disk is obtained, which is then sliced, finely ground, and cleaned to obtain a wafer. Thus, for example, 11 1313508, such as the semiconductor layer 1 〇 1 in Fig. 1, can be scooped according to several preferred embodiments of the present invention. The thousand conductor layer includes a p-type 矽. The inclusion of a slight antimony doping may be used in a preferred embodiment of the invention, the domain comprising an embodiment of n+ doped implants. In the present invention, the source/drain regions of the present invention will be advantageous in semiconductors that are slightly doped by the reverse bias of the junction. Such as the implementation of the semi-conducting and semi-conducting methods of stylization and reading, such as the use of butterfly, "doping can be used any suitable

The element of the semiconductor material can be used for the semiconductor material: any: from the electron-doped doping system at a dose of from about l〇i3/cm2 to about 62, preferably, p-type, b p 1015/cm2. 10 /em2 to about

It can be understood that, although the contact layer of the present invention, wherein the semiconductor layer includes a -p type semiconductor system, the source/drain region formed by the above n-type doping is formed by 曰, J s The memory cell of the present invention also includes the method of the pNp type semiconductor NPN. The method of the invention can prepare the PNP memory. pNp; and this

The inter-band hot electron injection method is programmed to = ^ to the source/drain region and apply a positive voltage to the gate to produce a J-sub-transfer. The erasing of the PNP is performed by applying a positive electric gate to the gate, and a Norman (FN) hole is injected to introduce the hole into the trap layer. A Field One of the inventions has a source region and a gate region. In the present invention, it is collectively referred to as at least two source/drain regions. As can be understood by those skilled in the art, each memory cell includes two source/drain regions, each of which can be used as a source or a drain, depending on the position of the applied voltage and the bit ratio. 12 • 1313508 The region used in the present invention can function as two: two regions" - the word is used to refer to the dual function of the primary pole. When referring to the memory cell of the present invention = the % applied voltage is used as the source and the other region acts as the drain; the two words can be used separately to refer to the specific area, and "/, / °" is not used for mosquitoes. The work of these regions, the use of the second word capsule is limited to a specific region _ _ cutting the source and the drain of the present invention. (IV) The memory device of the present invention may comprise a semiconductor layer having two source regions on the 续And constitute a plurality of memory cells. It can be understood that the =-hetero/ & polar region can act as the source of the adjacent two memory cells or not... or it can act as a immersive and adjacent neighbor in the source region of the -memory cell The role of the memory cell in the bungee region is the source. For example, please refer to Figure 1 'Source/drain region 110 can function as source/no-polar region m and an adjacent memory cell (located on the left side of memory cell! (10), not shown)_ The source/pole region (not the source) of the source, and the source/drain region m and other source/drain regions act as drains. Conversely, source/pole/drain regions can be applied to the drains of both, while source/drain regions H2 and other source/drain regions act as sources. Or, for example, when the source/drain region 112 acts as a source, the source/drain region n〇 can be used as a drain and in a neighboring memory cell (on the left side of the memory cell 1〇〇, When the other source/drain regions of the unillustrated) function as the drain, the source/drain region j 1〇 acts as the source. In general, each of the at least two source/drain regions includes a region underneath the surface of the semiconductor layer in a doping manner complementary to the doping pattern of the semiconductor layer. In other words, when a p-type semiconductor layer is used, the source/drain region 13' 1313508 domain is n-type doped, and vice versa. (d), the embodiment of 矽, Yin, the at least two (four) thousand body layer including the p branch domain, preferably with a high dose of Γ type: m includes n + doped region structure m in H;; It is selected from Shishen, ion implant (concentration is about l〇19/cm3 to H) / (10). Thus, in a particularly preferred embodiment, the at least polar region comprises an n-type buried diffusion region implant. ° 'The life of each of the at least two source/drain regions is deep in the semiconductor layer. It can extend from the surface of the body to τ by about 3G to nanometer, depending on the component = generation or node (ie, the smallest feature) Dimensions such as 13 〇 nanometer, etc.) and in one embodiment of the present invention, the 'technical generation node system, at least two source-polar regions can have an ice density of about 100 nm in the semi-conducting county, from the semiconductor layer. The surface begins to measure down. As used herein, the source/drain regions are "under" the surface of the semiconductor layer, including the source/drain regions over which the doped regions extend and the surface itself of the semiconductor layer. In other words, the present invention does not require any source/drain regions: it must be completely under the surface of the semiconductor layer. The present invention can be applied not only to conventional semiconductor layers but also to an insulating overlying germanium (S0I), thin film transistor (TFT) process, or a vertical transistor process. The invention also includes a memory array comprising a plurality of memory cells. In this issue: the memory array is used to make mosquitoes, and the memory cells on the second array can be arranged in the column, and the source/drain regions on both sides of the memory cell will include continuous buried diffusion bits. Yuan line. Each of the individual lines includes a continuous erbium doped region that is located below the surface of the semiconductor layer. The array comprising a plurality of cells of the invention may further comprise a plurality of selection transistors and/or a common source line, and the complex is applicable to a matrix (NOR) affecting a plurality of memory types (NAND &quot;; In a particular embodiment of the invention, f&quot;remembering body../dipole region (or bit line) and conversely two heterogeneous adjacent to more than one source: Degu system such as "mut" area, can be sputum The implant b is called the π bag implanting area. For example, when the source/region includes the n+ doped region, the pocket implant can be performed for the small, domain or adjacent to the more than one lung continuation region. Because: straight m: the cell can further include doped pockets of opposite doping type, which are adjacent to more than one source private and polar regions. In the monthly application, any conventional ion cloth can be used. Planting private or any technology under development. The memory cell of the present invention can be selectively included in the semiconductor layer - Table U 1 (d) its entangled region. In the present invention, the at least two source/wave is excellent Stacked on the charm layer is set on the semiconductor layer (relative to the Jielei material ~ source / bungee area On the surface of the semiconductor) can be completely filled with poly dielectric material or any other best _ medium = degree electric (four) compound. In the present invention, the specific t #f in the present invention includes cerium oxide. Preferably, the high-solid=cell=cell may include a dielectric material/dipole region (four) dielectric material, which is disposed in each source instance, and the memory cell may be on the surface of the body layer. Some of the implementation layers are formed on the surface of the stone, and the upper surface is, for example, an open-electrode oxide detachable layer between the surface and the dielectric material. 1 pole... grows on the surface of the +conductor layer, and In a particular preferred embodiment in which the semiconductor layer package 15 1313508 includes germanium, the gate oxide layer may comprise a dioxide dioxide. Each pair of source/drain regions of the present invention is separated by a channel region. The region refers to the portion of the semiconductor layer that is located in the two-source/no-polar region, wherein when a suitable voltage is applied to the source, drain, and gate, the charge carriers will migrate from a source/drain region to Another source/drain region. So, for example, please refer to Figure 1, channel 115. The portion of the semiconductor layer between the source/drain regions 110 and 112. In this specification, "channel length" means from one source/drain region to another source/drain region. The channel area distance refers to the size of the channel area which is perpendicular to the channel length. One of the memory cells of the present invention includes a lower insulating layer. For example, referring to FIG. 1, the memory cell 100 includes a lower insulating layer 120 disposed on Above the channel region 115. The lower insulating layer is located substantially above the channel region. In the present invention, "above" the channel region means that the position of the lower insulating layer is on the surface of the channel region of the semiconductor layer, but not It is inevitable to directly contact the surface φ surface of the semiconductor layer. As described above, the memory cell of the present invention may include more than one additional layer structure between the semiconductor layer and the lower insulating layer, such as a gate oxide layer. Suitable materials for the lower insulating layer can include any high dielectric dielectric material that provides an electrical insulating effect between the semiconductor layer and the charge storage layer. A low dielectric material or pure oxide can also be used as the material for this layer because it does not capture electrons during read, program, and erase operations. When a high electric field is applied, electrons and holes can be tunneled. Suitable high dielectric dielectric materials include, for example, sulphur dioxide, oxidation groups, oxidation, oxidation, titanic acid, strontium titanate, oxidized imides, compounds, and mixtures. The insulation 16 ^ 13508 = system:: oxide formation, such as "oxide, oxidation, etc.. == In the example, - the lower insulation layer can include - conversion. Between, with the squeaking ngSt_) You 丄, (4) change from point to point. The thickness of the lower insulation layer = ί = angstroms to prevent the memory cells from being stylized (that is, lost in the middle. Therefore, the lower insulation layer acts as - insulation Door 2: Provides obstacles for the channel region of the casting layer and the charge storage layer 2. The material and thickness of the lower insulating layer may be changed as long as the barrier function of the insulating layer is applied to the voltage during the memory loss or read operation At least two sources/drain electrodes can still provide an insulation effect. And the memory cells of the present invention are also intentionally overcome, and the charge storage layer is also disposed in the lower two layers. Refers to the charge reservoir: it must be in direct contact with the lower insulating layer. The material layer of the present invention is on the lower insulating layer and the charge storage side: thus it can act as a tunneling enhancement layer or a trapping charge storage layer. Volatile storage portion. This charge storage layer is preferably; ===: Loaded material, stylized operation refers to the application-stylation of electricity to the gate and source/drain regions to trap the storage layer. The thickness of the charge storage layer may not be captured by the layer that enters the thin film. The effect, or capture effect is 150 angstroms. The layer is also not ideal because it will require a higher operating dust. Thicker 17 of the invention, or the storage layer may include one. Caoqin ^^ charge trapping material. Multi-θ A / ψ pole material, such as multi-tanning operation, because it is - conduction can set several polycrystals in a double bit / memory cell and 兀 / memory bleb mode Shi Xidian can be in the 〆

The charge storage layer comprises a charge trapping material: material in each of the preferred embodiments of the invention. It is suitable for use in the present invention, such as acid broth, barium titanate steel, and oxygen cage. Limited to 'nitriding bite, oxidation group, cobalt dioxide, I °, charge trapping layer may also include a layer of two layers of dioxins; two: = separated polycrystalline hair island, selectively placed in the formation For example, the nitrided trapping layer is preferably a vaporized material. In the present invention, "Ray 4 4 or yttrium oxide ytterbium (SiOxNy). The structure can capture local: electricity - =::r hardly == load 2: electricity τ captures the dielectric layer. Therefore, in order to promote electricity

The degree will be lower than the misplaced; = residential: the electronic barrier of the capture layer material has a higher height and the other layers of the electrical capture layer (ie, the second barrier height is ancient, and the ?y θ is lost to a lower barrier height) Material layer). For example, in the embodiment in which the iUb11 charge trapping layer is sandwiched between the two gasification layers (for example, the Xixia lower insulating layer and the Shishi oxide first-dielectric layer), the barrier height of the oxygen and the physical layer is about 31 ev, and the barrier height of the nitride layer is about! 2 1 eV. Βει ll —_ υ This an electron well is formed in the nitride layer. A can be used for the lower insulating layer and the material in the first dielectric layer, and the layer may preferably comprise an oxide, more preferably; However, the charge trapping layer in the oxide layer must include a different dielectric 18 * 1313508 material (with a lower barrier height) with different insulation, dielectric, and '舆 charge trapping two =:. Suitable for technology or development 21 = what is customary, when the TM layer includes m pull 4 material. By way of example and technology, this oxide layer can be oxidized by low pressure chemical vapor deposition (L; dimerization, chemical vapor deposition (cvd), (PECVD) ^, plasma enhanced chemical gas Phase deposition is used for sinking vapor deposition (ICP). Suitable phase deposition and plasma nitrogen/helium processes include, but are not limited to, nitriding, chemical gas in the second embodiment of the second temple. More preferably, these #八别心/1 electrical layers include an emulsified and cerium oxide. The following are the cerium, tantalum nitride, and the electric layer respectively including an oxide, and more preferably The oxygen dioxide: the second, the charge trapping layer, and the first dielectric layer respectively comprise at least two-acoustic 3, which may be an emulsified stone. In the embodiment, the at least two layers of the diatom layer are at least - Oxygen dioxygenate layer. The dioxon dioxide is composed of a thermally grown or deposited oxide. The nitrogen may be a nitrogen oxide layer. The nitride may be a nitrogen-rich layer: a layer of germanium.... Oxygen-containing tantalum nitride. The nitride may also be a nitrogen sound; Γ: two's insulation layer, charge storage layer, And the upper insulation::,,:; visibility, can correspond to the channel length and channel width. The mother layer of the 5 can be equal to the width of the at least two source/drain regions, and the length 19 1313508 degrees is equal to the separation The channel length of the at least two source/drain regions. The memory cell of the present invention may further comprise an upper insulating multilayer structure. The insulating multilayer structure of the present invention comprises a polysilicon material layer interposed between a first dielectric layer and a Between the second dielectric layers, as the term "above" of the other layers is used, the upper insulating multilayer structure may be located above the upper surface of the charge storage layer, but does not necessarily directly contact the charge storage layer. The above additional layer, such as an additional insulating layer, may be selectively disposed between the charge storage layer and the upper insulating multilayer structure. The first dielectric layer and the second dielectric layer may comprise the same material or different materials. Suitable materials for the second dielectric layer include high dielectric dielectric materials such as crushed oxides, oxidized groups, oxidized, oxidized, titanic acid, titanic acid, oxidized, and their dreams and Mixed Preferably, the first dielectric layer comprises a chopped oxide, and more preferably a dicerium oxide. Preferably, the second dielectric layer comprises a cerium oxide, and more preferably a cerium oxide. Preferably, the first and second dielectric layers each comprise a cerium oxide, and preferably both comprise cerium oxide. The first dielectric layer may have a thickness of between about 10 and about 40 angstroms. The thickness of the layer is important for tunneling between the gate and the charge storage layer. The preferred thickness is 13-18 angstroms. The thickness of the second dielectric layer can range from about 10 to about 40 angstroms. The thickness of the two dielectric layers is important for data storage and reliability, preferably 25 angstroms. The upper insulating multilayer structure comprises a polycrystalline material layer. The polycrystalline material layer may comprise undoped polysilicon. Or doped polysilicon. The doped polysilicon material can be an n-doped or p-doped material, and the doping amount is not limited. The upper insulating multilayer structure can have a thickness of from about 5 to about 40 angstroms. A preferred range is 10-20 20 * 1313508 angstroms. The polycrystalline germanium material layer can be formed by any conventional method or method in development. For example, polycrystalline can be deposited by chemical vapor deposition or vapor deposition. In embodiments in which the polycrystalline lanthanide is doped, the polysilicon can be doped using conventional or evolving ion implantation methods, or can be selectively doped during the deposition step. If the polycrystalline lanthanide is doped, its thickness should be between 10 and 40 angstroms. In a particularly preferred embodiment of the invention, the upper insulating multilayer structure comprises a layer of undoped polysilicon material having a thickness of about 30 angstroms, which is interposed between a first dielectric layer and a second dielectric layer. Between the first dielectric layer comprising cerium oxide and having a thickness of about 30 angstroms, the second dielectric layer comprising cerium oxide and having a thickness of about 30 angstroms. The memory cell of the present invention also includes a gate disposed over the upper insulating multilayer structure. As previously mentioned, "on top of the upper insulating multilayer structure" means that the gate is spatially located on the upper surface of the upper insulating multilayer structure without necessarily contacting the upper surface of the upper insulating multilayer structure. Therefore, the gate of the φ memory cell of the present invention can be directly disposed on the upper dielectric layer of the upper insulating multilayer structure, or a gate can be separated from the upper insulating multilayer structure by an additional material, and the additional material can be exemplified. Such as an extra insulation material. Preferably, a gate is directly disposed on the upper dielectric layer of the upper insulating multilayer structure. Extremely any conductive material may be included between the present invention. Preferably, the gate of the present invention comprises a polycrystalline layer which may be n-type or p-type doped, and the metallization layer is disposed over the polysilicon layer. The thickness of the polysilicon gate layer is preferably between about 30 nm and about 200 nm. In a particularly preferred embodiment of the invention, the polycrystalline lanthanide is p-type doped. The metal ruthenium 21 - 1313508 gate layer of the preferred embodiment of the present invention may comprise a metal ruthenium material selected from the group consisting of tungsten telluride, shi xi ti, shi shi ming, and shi xi hua. The gate material layer can be formed by any process suitable for depositing a metal, organic material, polysilicon, or other conductive material. Metals can be formed using conventional or evolving metallization processes. Metal-containing materials such as metal halides can be deposited by, for example, sputtering or chemical vapor deposition. The chemical vapor deposition process is preferably used to form a metallite. The polycrystalline germanium material can be formed by any conventional or evolving process, such as a chemical vapor deposition process using SiH4 or dichloro-SiH4, and the polysilicon can be doped in a deposition process or deposited on a semiconductor layer. miscellaneous. The invention also includes a method for operating a memory cell formed using any of the above embodiments. The method of the present invention includes applying a positive voltage to the gate of the memory cell of the present invention, wherein the positive voltage is sufficient to tunnel the hole from the gate to the charge storage layer. The method of the present invention includes applying a positive voltage to the gate to erase and/or reset the memory cells and array. The positive Φ pressure suitable for application to the gate of the memory cell of the preferred embodiment of the invention may range from about 10 to about 15 volts. Preferably, 13 volts is applied. In general, a positive voltage is applied to the gate of the memory cell for a period of time to reduce the threshold voltage of the memory cell to its erased state. In accordance with a preferred embodiment of the present invention, a suitable erasing time can range from about 100 to about 500 milliseconds when the positive voltage is from about 10 to about 15 volts. A preferred erasing time is from 200 to 400 milliseconds. The memory cells of the present invention can be programmed via a variety of thermoelectronic methods, including, for example, channel hot electron (CHE) operations. Other suitable stylized methods include Fuller-Nordham tunneling. It is preferred to use a positive voltage stylization. 22 1313508 The memory cell of the present invention can be read in a forward or reverse manner. For double bit/memory operation, reverse reading is used to distinguish the captured bits. • The memory cell of the present invention can be fully operated (programmed/read/erased) using all positive voltage systems. For example, as shown in Table 1, a memory cell system according to a preferred embodiment of the present invention has an NPN junction structure, wherein the lower insulating layer and the dielectric layer system comprise a dioxide dioxide, and the charge trapping layer comprises a nitride nitride layer. The polysilicon layer is undoped and the gate includes p-doped polysilicon, and each stylized, erased, and read operation can be performed with all applied voltages being positive. Table 1 Operation VG(V) VD(V) VS=VB(V) Time Stylized 9 5 0 5 microseconds erase 12.5 0 0 400 milliseconds read 3 1.6 0 - Figure 2 depicts a memory cell in a wipe Except that a positive voltage of 13 volts is applied during operation to a threshold voltage after a period of time, as described in the previous paragraph, wherein the thickness of the lower insulating layer is 50 angstroms, the thickness of the charge trapping layer is 70 angstroms, and the layer of polysilicon material The thickness is 20 angstroms, the thickness of the first dielectric layer is 18 angstroms, and the thickness of the second dielectric layer is 18 angstroms ("exemplified memory cells"). As shown in Figure 2, the threshold voltage is reduced from approximately 4.5 volts to less than 2.5 volts, while the positive gate voltage represents successful tunneling from the gate. Figure 3 illustrates the operational performance of the memory cell after 50 staging/erasing (P/E) cycles. The operating range of this memory cell is quite good, because the process of erasing the critical electric house of the 23 2313508 is quite stable. In the stylized disk wiper, the bucker current is the gate voltage. As shown in the figure 1:: the middle, the first-person and the change after 50 cycles (almost the I value is almost hidden, showing the minimum degree of i ΪΐΓ ρ. Figure 5 shows the sub-critical part of Figure 4 : ring time = memory performance after 50 cycles is still the first time

Although the present invention has been described with reference to the preferred embodiments, it is understood that 'the invention is not limited by the detailed description thereof: the rank change mode and the modified style are suggested by the first m towel, and the other two Modifications and modifications will occur to those skilled in the art, and in accordance with the structure and method of the present invention, all having substantially the same components of the present invention can achieve substantially the same results as the present invention. They do not depart from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims. Any patent application mentioned in the foregoing and the Mang* text are a series of references for this case. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a memory cell according to an embodiment of the present invention. Figure 2 is a diagram showing a memory cell of the present invention, smeared at a +13 volt. E& boundary voltage change diagram. Fig. 3 is a graph showing a threshold voltage change after a number of pass/erase (P/E) cycles of a memory cell according to an embodiment of the present invention. 24 1313508 FIG. 4 is a diagram showing the variation of the gate current versus the gate voltage during the erasing and programming operation of the memory cell according to an embodiment of the present invention. Fig. 5 is a partial enlarged view of Fig. 4. [Main component symbol description] 100 memory cell 101 semiconductor layer 110, 112 source/&gt; and polar region φ 115 channel region 120 lower insulating layer 130 140 142 charge storage layer upper insulating multilayer structure first dielectric layer 144 polysilicon layer 146 second Dielectric layer 150 • Gate 25

Claims (1)

1313508 X. Patent application i-type memory cell, comprising: (〇-semiconductor layer comprising at least two source/drain regions close to the surface of the semiconductor layer and separated by a channel region; (li)- a lower insulating layer is disposed on the channel region; (111) a charge storage layer is disposed on the lower insulating layer; (on) an upper insulating multilayer structure is disposed on the charge storage layer, and The structure includes: a polycrystalline material layer interposed between the first electricity layer a and a second dielectric layer; and (V) a gate electrode disposed on the upper insulating multilayer structure. The memory cell, wherein the memory cell dielectric layer and the semi-conductor plate system are insulating memory cells, wherein the carrier is half of the mazastatin, glass, or sapphire. The memory cell described in item 1 of the patent application scope of the second layer, wherein the semi-conducting one includes Ϊ + + 彡 彡 彡 二 二 二 二 二 二 二 二 二 二 二 二 经Buried into the diffusion planting area. The mother layer ^^^ surrounds the memory cell described in item 1, where the next The edge 26 1313508 layer is seven memory cells of the lower insulation, and the memory of the memory is stored in the memory cell of the first item, wherein the charge storage layer is a memory cell described in item (4), wherein the charge is stored. The memory cell of item 2, wherein the memory cell is 10 to 30 angstroms. 记忆 The memory cell of the second norm term, wherein each of the first cell; the electrical layer comprises a tantalum oxide. 10 to 40 The thickness of the second dielectric layer is about 1^13508, and the thickness of the dielectric layer is s 10 to 40 angstroms. The memory cell according to item 14, wherein the first 25 angstroms, and the first The thickness of the second dielectric layer is about: '= Miscellaneous:: The memory cell described in item 1 of the '4' edge sound instrument (4), wherein the lower extinction oxide The charge storage layer includes a nitride: and the::: the first dielectric layer and the second dielectric layer comprise - shixi oxide and wherein the gate system comprises a P-doped polysilicon. The seed reading array includes a plurality of memory cells as described in claim 1 of the patent application. 19. A memory cell comprising: (0 The semiconductor layer 'includes at least two source/drain regions disposed under the surface of the semiconductor layer and separated by the channel region; (ii) a tantalum oxide insulating layer is disposed over the channel region; In) a tantalum nitride charge storage layer is disposed on the tantalum oxide insulating layer; (iv) an upper insulating multilayer structure is disposed on the charge storage layer, wherein the 28 ϊ3!35〇8 〇^ insulated multilayer structure a layer of polysilicon material is interposed between a first dielectric layer and a second dielectric layer, wherein the layer=layer has a thickness of about 10 to 3 G angstroms. The electrical system is about 10 to 40 angstroms, and the thickness of the second radiant oxide dielectric layer is about 10 to 40 angstroms; and the 曰 (v)-gate is disposed on the upper ruthenium Polycrystalline;:: Above layer 4, wherein the cell described in claim 19 of the invention has a semiconductor substrate, and the substrate in the crypto, dielectric, or carrier is insulated.上上石夕, 21. The semiconductor substrate is a primary carbide as described in the second paragraph of the patent application, _, the carrier 22. An array of memory cells comprising a plurality of memory cells as described in the item &lt; Patent Application No. 19: 23. A method of operating a memory cell, comprising: (a) providing a memory cell comprising: (i) a semiconductor layer comprising at least two surfaces of the semiconductor layer and a channel region The separation/and the polar region are close to (ϋ). The insulating layer is disposed in the channel region. The second (four)-charge storage layer is disposed on the lower insulating layer. (iv) - the upper insulating multilayer structure is disposed on the 曰, °H charge storage layer Above, 29 1313508 a layer of spar material is interposed; and wherein the upper insulating multilayer structure comprises a plurality of first dielectric layers and a second dielectric layer (v) - the gate is disposed on the upper insulating layer Above the multilayer structure and a positive voltage to the gate, the positive voltage is sufficient to cause a hole to tunnel from the gate to the charge storage layer. 'The memory cell is overlaid, chopped, 24. The method of claim 23, further comprising a semiconductor substrate which is one of an insulating dielectric or a carrier. 25. The method of claim 1, wherein the conductor substrate is cut into a carbide, a glass, or a sapphire; 5: the second method of claim 23, wherein the positive voltage is obtained. It is about 10 to 15 volts. 27. The method of claim 23, wherein the length of time is between about 200 and 500 sec. 28. The method of claim 2, wherein the gate is a P-doped polysilicon. Wherein the positive voltage 29. is as described in claim 28, and the square g is about 10 to 15 volts. 30 WORK 3135 〇 8 30. Positive voltage As in the scope of the patent application, the length of time is between about 200 and the method is applied, which is applied between the leap seconds. 31