1313491 九、發明說明： 【發明所屬之技術領域】 一本發明係關於一種球狀陣列封裝基板製作方法，尤指 $ -種適用於晶穴朝下型球狀陣列封裝基板的製作方法。 【先前技術】 ★由於電子產品曰趨輕量化、薄型化、小型化、多功能 化尋需求，同時帶動積體電路晶片封裝技術的發展，進而 促使晶片封裝朝向多腳化、薄型化、及引腳微細化，甚至 10 無引腳構裝等技術。 一為因應輕薄短小的趨勢以及追求封裝的高密度化，目 則球狀陣列封裝（Ball Grid八叫）、晶片尺寸型封装（⑶p ale Package)、及覆晶（jqip 技術已成為封裝主流技 術。因此，對於小面積、1/〇接腳提高、佈線緻密化、低雜 U訊、產品可靠性、甚至製作成本等需求，已成為封裝基板 製作之重要課題。 丨隨著1C封裝輕薄短小以及發熱密度不斷提昇的趨勢， 散熱問題日益重要，如何降低封裝熱阻以增進散熱效能是 封裝設計中很重要的技術。晶穴朝下型球狀陣列封裝 20 (Cavity Down Ball Grid Array, CDBGA)，是於一般BGA基 板之一表面加上一層銅板，且基板形成有至少一開口，將 一晶片置於基板與銅板間之開口，而可透過銅板逸散掉晶 片產生之高熱，以提供較佳之散熱性。 習知製作晶穴朝下型球狀陣列封裝基板的方法如圖 5 1313491 1A-圖1Η流程圖所示。首先提供一具有内層線路之四層板， 其表面係覆有銅箔110，可分割成複數個基板單元，現以基 板單元100作說明，如圖1Α所示。然後，將基板單元100進 行鑽孔，形成複數個貫孔200與一晶穴300，如圖1Β。接著 5 使用習知之圖案化製程（pattern process)’在基板100全面（包 括貫孔200内側壁與晶穴300内側壁）形成一導電層（晶種 層）120，再貼合上一層乾膜光阻400後，進行曝光顯影，以 形成一具圖案化之乾膜光阻400，如圖1C所示。 接著以電鍍方式，增厚一層銅金屬於沒有光阻覆蓋之 10 導電層120位置上，同時，在貫孔200内側壁以及晶穴300之 側壁也鍍上一層銅金屬500，藉以隔絕雜訊，作為屏蔽效 用，如圖1D所示。隨後移除圖案化乾膜光阻400，並將原乾 膜光阻400遮蔽處之導電層120與銅箔110皆以蝕刻方式移 除，即形成一圖案化線路結構500，如圖1E所示。 15 接著以填料210填充貫孔200，並於原光阻保護位置塗 覆上一層防悍層600(基板100上表面），以及保護層601 (基板 > 100下表面），再於全部線路結構500表面鍍覆一阻障層 700，如圖1F所示。然後將一黏著層800(如prepreg)貼合於 基板100下表面保護層601上，此黏著層800係用以將基板 2〇 100與一散熱板（如一銅板）接合。 一般而言，由於基板100上已開有一晶穴300，因此黏 著層800也必須先依照晶穴300之位置，預先開一對應的開 口 801，避免遮蓋到基板100上之晶穴300，如圖1G所示。 最後將一散熱板900黏合上黏著層800後，將基板100 1313491 及散熱板900進行切割，即完成一晶穴朝下型球狀陣列封裝 基板’如圖1H所示。 然而’為了對應晶穴位置，習用之黏著層必須先依照 對應基板晶穴之位置進行開孔作業，此將增加一額外 5驟’且也因*易控制開孔位置’造成對位精確度下降嗜 低良率’不符合經濟效益。 此外，習用技術中，基板在與黏著層（如半固化片 prepreg)麼合時，多需要高達20(rc的高溫，才能使基板與 半固化片密合，此高溫卻反而容易使基板上作為習用塞孔 1〇材料之綠漆受影響，而導致脆化等現象發生。同時在壓合 過程中，也會因半固化片已經進行過開口程序，其開口處 會造成許多纖維料露’而殘留在散熱基材之晶穴位置 上’造成半ϋ化碎狀污染，使後續製程良率下降。 因此，為提高整體良率，縮短工時，亟需開發一種製 15作晶穴朝下型球狀陣列封裝基板的改善方法。 【發明内容】 、本發明提供-種晶穴朝下型球狀陣列封裝基板的製力 二二：中黏者層使用前不需經過加工’可與承载基板辰 %進行成型，可縮短工時，提升整體良率。 、本發明提供之方法中，所使用絲著層可不需要事先 對應基板晶穴之位置進行開孔作業，因此無須經過開孔愈 晶穴之對位步驟，因而可避免對位精確度不佳之問題/、 本發明之晶穴朝下型球狀陣列封裝基板的製作方法包 20 1313491 括如下步驟：⑷提供—具内層線路之含—第 二表面之電路板；（b)於電 :/、一第 透槽’且凹槽之開口係位於電路板之第一 :’⑷形成-外部線路層於電路板之第一表面盘 以及：：部：路層係延伸形成至未穿透凹槽之内側壁二 ㈣二内侧壁上’⑷’分別形成-圖案化之防焊 層”保Μ於f路板第—表面之外料 面之外部線路層上，以乃拟士 ^ 曰上，、弟一表 上.人 以㈣—阻障層於部分外部線路層 10 15 板第-矣极《保-層上，以及(f)於電路 板第表面上之未穿透凹槽間鑽孔，形成—晶穴。 本發”作方法巾，於步_之後更可包括一步驟 ^貼合Γ散熱板於黏著層上，並將電路板及散熱板進行 板^此^熱板係可作為f路板之支標，亦可協助封裝基 所果、、且之散熱。適用之散熱板材料不限，較佳可以是—鋼 貝基板，如銅板。 纟發日讀作枝步驟⑷巾所提之電路板結構不限，可 ’ ：S用之H基板、兩層或多層内部線路結構之電路板。 1本發明製作方法步驟⑷中，外部線路層的形成方式可 2〇為％用之任何方法，例如加成法。本發明所揭示之形成外 f線路層的方法’包括先依序形成-導電層於電路板之第 后 第表面貝孔之内側壁以及未穿透凹槽之内側 八中°亥電路板之第一表面及第二表面係形成有銅箔， 再形成圖案化光阻於於電路板之第一表面及第二表面，電 錢形成金屬層於電路板之第—表面、第二表面、貫孔之内 8 5 15 20 1313491 側壁以及未穿读m她 光阻所_ ㈣’移除移除圖案化光m 先阻所覆盍之導電層與銅络，並以填料填充阻以及 孔後，形成外部線路層。 、充电路板上之貫 上述外部線路層的形成方式中 限，可以是濺鍍或盔電雷m $電層的形成方式不 金屬層較佳則可以電鍵方式形成。而用、^式形成。 可以是習用之任料， 真充貝孔之材料 化外部線路層之圖案化光阻，可以是習用之V糊案 阻’較佳係可為一乾臈光阻。 任何-種光 /本發明方法步驟⑷中之防焊層材料或 佳係為綠漆或黑漆。而本發明 :二又 層未覆蓋之外部線路声上f &層形成於防焊 屬μ不县祜4 Β /、㈣在保❸卜料路層之金 :層不易被減。適用之阻障層材料 錫、鎳/把、絡/欽、錄/金、免/金、⑹⑻金'； 較佳之阻障層係為—鎳金 或，、、及口， 之阻产思队 評R日夺’本發明方法中步驟（d) ^層除了形成於電路板之第一與第二表面外，亦 ==凹槽之内側壁中’以保護未穿透凹槽中内侧壁之 本發明方法中之黏著層可為f用之任—種，較佳為— ^纖维樹脂=著層，例如—膠帶。傳統方法多需先依照電 上所開叹之晶穴位置’先行於所欲貼合之半固化片上 加工開設一開口，再行貼合。然而半固化月經過開口程序 後常殘留許多殘肩’造成貼合之污染，或是開口後之半固 化片位置與電路板上晶穴位置無法精準對位，造成製程的 9 1313491 防焊層60 保護層61 阻障層70 黏著層80 散熱板901313491 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a spherical array package substrate, and more particularly to a method for fabricating a crystal-cavity-type spherical array package substrate. [Prior Art] ★ As electronic products become lighter, thinner, smaller, and more versatile, they also drive the development of integrated circuit chip packaging technology, which in turn promotes wafer package orientation, thinning, and The foot is fine-grained, even 10 pinsless construction technology. In order to respond to the trend of thinness and shortness and to pursue high density of packaging, the goal is to package a ball array (Ball Grid), a chip size package ((3) package), and flip chip (jqip technology has become a mainstream technology for packaging). Therefore, the demand for small area, 1/〇 pin, wiring densification, low noise, product reliability, and even manufacturing cost has become an important issue in the manufacture of package substrates. 丨 With the 1C package is light and short, and heat The trend of increasing density, heat dissipation is becoming more and more important. How to reduce the thermal resistance of the package to improve the heat dissipation performance is an important technology in the package design. The Cavity Down Ball Grid Array (CDBGA) is A surface of one of the general BGA substrates is coated with a copper plate, and the substrate is formed with at least one opening, and a wafer is placed in the opening between the substrate and the copper plate, and the high heat generated by the wafer is dissipated through the copper plate to provide better heat dissipation. A method for fabricating a crystal-cavity downward-facing spherical array package substrate is shown in FIG. 5 1313491 1A-FIG. 1 . The four-layer board of the layer line is covered with a copper foil 110, which can be divided into a plurality of substrate units, and is now described by the substrate unit 100, as shown in FIG. 1A. Then, the substrate unit 100 is drilled to form a plurality of The through hole 200 and a crystal hole 300, as shown in Fig. 1. Next, a conductive layer is formed on the entire substrate 100 (including the inner side wall of the through hole 200 and the inner side wall of the crystal cell 300) using a conventional pattern process. The seed layer 120, after bonding the upper layer of the dry film photoresist 400, is exposed and developed to form a patterned dry film photoresist 400, as shown in FIG. 1C. Then, a layer of copper is thickened by electroplating. The metal is in the position of the 10 conductive layer 120 without the photoresist cover. At the same time, the inner side wall of the through hole 200 and the side wall of the crystal hole 300 are also plated with a layer of copper metal 500 to isolate the noise as a shielding effect, as shown in FIG. 1D. Then, the patterned dry film photoresist 400 is removed, and the conductive layer 120 and the copper foil 110 at the shadow of the dry film photoresist 400 are removed by etching, that is, a patterned circuit structure 500 is formed, as shown in FIG. 1E. 15 then filling the through hole 200 with the filler 210 And applying a layer of anti-mite layer 600 (the upper surface of the substrate 100) and a protective layer 601 (substrate > 100 lower surface) to the original photoresist protection position, and then plating a barrier layer 700 on the surface of the entire line structure 500, As shown in Fig. 1F, an adhesive layer 800 (e.g., prepreg) is then attached to the lower surface protective layer 601 of the substrate 100 for bonding the substrate 2100 to a heat sink such as a copper plate. Generally, since the crystal substrate 300 is opened on the substrate 100, the adhesive layer 800 must first open a corresponding opening 801 according to the position of the crystal cavity 300 to avoid covering the crystal cavity 300 on the substrate 100. 1G is shown. Finally, after bonding a heat dissipation plate 900 to the adhesive layer 800, the substrate 100 1313491 and the heat dissipation plate 900 are cut, that is, a crystal-hole-down type spherical array package substrate is completed as shown in FIG. 1H. However, in order to correspond to the position of the crystal hole, the conventional adhesive layer must first perform the opening operation according to the position of the corresponding substrate crystal hole, which will increase an additional 5 steps 'and also cause the alignment accuracy to decrease due to the easy control of the opening position. The low-yield rate is not economically viable. In addition, in the conventional technology, when the substrate is combined with an adhesive layer (such as a prepreg), it is required to have a high temperature of up to 20 (rc), so that the substrate and the prepreg are closely adhered to each other, but the high temperature is easy to make the substrate as a conventional plug hole 1 The green paint of the bismuth material is affected, which leads to embrittlement and the like. At the same time, during the splicing process, the prepreg has already been subjected to the opening procedure, and the opening will cause a lot of fiber material to be exposed and remain on the heat-dissipating substrate. At the position of the crystal hole, it causes semi-cracking and shatter-like pollution, which reduces the yield of subsequent processes. Therefore, in order to improve the overall yield and shorten the working hours, it is urgent to develop a system for making a spherical array of downward-facing spherical arrays. The present invention provides a force for the formation of a crystal-hole-down type spherical array package substrate: the middle layer of the adhesive layer does not need to be processed before use, and can be molded with the carrier substrate. The working time is shortened, and the overall yield is improved. In the method provided by the invention, the wire layer used does not need to be opened in advance corresponding to the position of the substrate crystal hole, so there is no need to open the hole. The alignment step of the healing hole can avoid the problem of poor alignment accuracy. The method for manufacturing the crystal-cavity downward-facing spherical array package substrate of the present invention includes the following steps: (4) providing - with inner wiring a circuit board comprising a second surface; (b) an electric: /, a first through slot ' and the opening of the recess is located at the first of the circuit board: '(4) forming - the outer circuit layer is on the first surface of the circuit board And:: part: the road layer is extended to the inner side wall of the non-penetrating groove, and the two (four) two inner side walls are formed by '(4)' respectively forming a patterned solder resist layer" to protect the surface of the f-plate On the external circuit layer of the surface, on the other side, on the other hand, on the table, on the table, on the table, on the table, on the part of the external circuit layer, on the outer layer of the circuit board, on the first layer, on the front layer, on the layer of the protection layer, and on (f) Drilling holes between the non-penetrating grooves on the surface of the circuit board to form a crystal hole. The method of the present invention may further comprise a step of laminating the heat sink on the adhesive layer, and The circuit board and the heat sink are used for the board. The hot board can be used as a support for the f-way board, and can also assist the package base, and Heat dissipation. Applicable heat sink material is not limited, preferably it can be - steel shell substrate, such as copper plate. The circuit board structure mentioned in the step of (4) towel is not limited, can be used for : : H substrate, two A circuit board of a layer or a plurality of internal wiring structures. 1 In the step (4) of the manufacturing method of the present invention, the external wiring layer can be formed in any manner by %, for example, an additive method. The outer f circuit layer is formed by the present invention. The method comprises the steps of: sequentially forming the conductive layer on the inner side wall of the second surface of the circuit board and the inner surface of the non-penetrating groove; the first surface and the second surface of the circuit board are formed with copper a foil, and then a patterned photoresist is formed on the first surface and the second surface of the circuit board, and the electric money forms a metal layer on the first surface, the second surface, and the through hole of the circuit board, and the sidewall is not Wearing m her photoresist _ (4) 'Removal of the patterned light m first blocking the conductive layer and the copper network, and filling the resistor and the hole with the filler to form an external circuit layer. The upper limit of the formation manner of the external circuit layer on the charging circuit board may be a sputtering method or a formation method of the helmet electric mine m $ electric layer. The metal layer is preferably formed by a key. And use, ^ form. It can be a customary material, and the patterned photoresist of the materialized external circuit layer of the true filling hole can be a conventional V paste case resistance. The preferred system can be a dry photoresist. Any kind of light / the solder mask material in step (4) of the method of the invention or the preferred system is green paint or black paint. According to the present invention, the f & layer formed on the external line of the uncovered layer is formed in the anti-welding genus 不 祜 Β Β 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Applicable barrier materials: tin, nickel/peng, ke/qin, recorded/gold, free/gold, (6) (8) gold'; the preferred barrier layer is - nickel gold or,, and mouth, the resistance of the team Comment on the step R (in step (d) of the method of the present invention, except that the layers are formed on the first and second surfaces of the circuit board, and also in the inner side wall of the groove to protect the inner side wall of the non-penetrating groove The adhesive layer in the method of the present invention may be any of those used for f, preferably - fiber resin = layer, for example, tape. In the conventional method, it is necessary to first open an opening according to the position of the crystal hole which is sighed on the electric front, and then perform the fitting on the prepreg. However, after the semi-curing month passes through the opening procedure, many residual shoulders are often left to cause contamination of the bonding, or the position of the prepreg after opening and the position of the crystal hole on the circuit board cannot be accurately aligned, resulting in a protective layer of 9 1313491 solder resist layer 60. 61 barrier layer 70 adhesive layer 80 heat sink 90
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